pagetable.hh revision 7741:340b6f01d69b
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#ifndef __ARCH_SPARC_PAGETABLE_HH__ 32#define __ARCH_SPARC_PAGETABLE_HH__ 33 34#include <cassert> 35 36#include "arch/sparc/isa_traits.hh" 37#include "base/bitfield.hh" 38#include "base/misc.hh" 39#include "config/full_system.hh" 40 41class Checkpoint; 42 43namespace SparcISA { 44 45struct VAddr 46{ 47 VAddr(Addr a) { panic("not implemented yet."); } 48}; 49 50class TteTag 51{ 52 private: 53 uint64_t entry; 54 bool populated; 55 56 public: 57 TteTag() : entry(0), populated(false) {} 58 TteTag(uint64_t e) : entry(e), populated(true) {} 59 60 const TteTag & 61 operator=(uint64_t e) 62 { 63 populated = true; 64 entry = e; 65 return *this; 66 } 67 68 bool valid() const { assert(populated); return !bits(entry,62,62); } 69 Addr va() const { assert(populated); return bits(entry,41,0); } 70}; 71 72 73class PageTableEntry 74{ 75 public: 76 enum EntryType { 77 sun4v, 78 sun4u, 79 invalid 80 }; 81 82 private: 83 uint64_t entry; 84 EntryType type; 85 uint64_t entry4u; 86 bool populated; 87 88 public: 89 PageTableEntry() : entry(0), type(invalid), populated(false) 90 {} 91 92 PageTableEntry(uint64_t e, EntryType t = sun4u) 93 : entry(e), type(t), populated(true) 94 { 95 populate(entry, type); 96 } 97 98 void 99 populate(uint64_t e, EntryType t = sun4u) 100 { 101 entry = e; 102 type = t; 103 populated = true; 104 105 // If we get a sun4v format TTE, turn it into a sun4u 106 if (type == sun4u) 107 entry4u = entry; 108 else { 109 entry4u = 0; 110 entry4u |= mbits(entry,63,63); // valid 111 entry4u |= bits(entry,1,0) << 61; // size[1:0] 112 entry4u |= bits(entry,62,62) << 60; // nfo 113 entry4u |= bits(entry,12,12) << 59; // ie 114 entry4u |= bits(entry,2,2) << 48; // size[2] 115 entry4u |= mbits(entry,39,13); // paddr 116 entry4u |= bits(entry,61,61) << 6;; // locked 117 entry4u |= bits(entry,10,10) << 5; // cp 118 entry4u |= bits(entry,9,9) << 4; // cv 119 entry4u |= bits(entry,11,11) << 3; // e 120 entry4u |= bits(entry,8,8) << 2; // p 121 entry4u |= bits(entry,6,6) << 1; // w 122 } 123 } 124 125 void 126 clear() 127 { 128 populated = false; 129 } 130 131 static int pageSizes[6]; 132 133 uint64_t operator()() const { assert(populated); return entry4u; } 134 135 const PageTableEntry & 136 operator=(uint64_t e) 137 { 138 populated = true; 139 entry4u = e; 140 return *this; 141 } 142 143 const PageTableEntry & 144 operator=(const PageTableEntry &e) 145 { 146 populated = true; 147 entry4u = e.entry4u; 148 type = e.type; 149 return *this; 150 } 151 152 bool valid() const { return bits(entry4u,63,63) && populated; } 153 154 uint8_t 155 _size() const 156 { 157 assert(populated); 158 return bits(entry4u, 62,61) | bits(entry4u, 48,48) << 2; 159 } 160 161 Addr size() const { assert(_size() < 6); return pageSizes[_size()]; } 162 Addr sizeMask() const { return size() - 1; } 163 bool ie() const { return bits(entry4u, 59,59); } 164 Addr pfn() const { assert(populated); return bits(entry4u,39,13); } 165 Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);} 166 bool locked() const { assert(populated); return bits(entry4u,6,6); } 167 bool cv() const { assert(populated); return bits(entry4u,4,4); } 168 bool cp() const { assert(populated); return bits(entry4u,5,5); } 169 bool priv() const { assert(populated); return bits(entry4u,2,2); } 170 bool writable() const { assert(populated); return bits(entry4u,1,1); } 171 bool nofault() const { assert(populated); return bits(entry4u,60,60); } 172 bool sideffect() const { assert(populated); return bits(entry4u,3,3); } 173 Addr paddrMask() const { assert(populated); return paddr() & ~sizeMask(); } 174 175 Addr 176 translate(Addr vaddr) const 177 { 178 assert(populated); 179 Addr mask = sizeMask(); 180 return (paddr() & ~mask) | (vaddr & mask); 181 } 182}; 183 184struct TlbRange 185{ 186 Addr va; 187 Addr size; 188 int contextId; 189 int partitionId; 190 bool real; 191 192 inline bool 193 operator<(const TlbRange &r2) const 194 { 195 if (real && !r2.real) 196 return true; 197 if (!real && r2.real) 198 return false; 199 200 if (!real && !r2.real) { 201 if (contextId < r2.contextId) 202 return true; 203 else if (contextId > r2.contextId) 204 return false; 205 } 206 207 if (partitionId < r2.partitionId) 208 return true; 209 else if (partitionId > r2.partitionId) 210 return false; 211 212 if (va < r2.va) 213 return true; 214 return false; 215 } 216 217 inline bool 218 operator==(const TlbRange &r2) const 219 { 220 return va == r2.va && 221 size == r2.size && 222 contextId == r2.contextId && 223 partitionId == r2.partitionId && 224 real == r2.real; 225 } 226}; 227 228 229struct TlbEntry 230{ 231 TlbEntry() 232 {} 233 234 TlbEntry(Addr asn, Addr vaddr, Addr paddr) 235 { 236 uint64_t entry = 0; 237 entry |= 1ULL << 1; // Writable 238 entry |= 0ULL << 2; // Available in nonpriveleged mode 239 entry |= 0ULL << 3; // No side effects 240 entry |= 1ULL << 4; // Virtually cachable 241 entry |= 1ULL << 5; // Physically cachable 242 entry |= 0ULL << 6; // Not locked 243 entry |= mbits(paddr, 39, 13); // Physical address 244 entry |= 0ULL << 48; // size = 8k 245 entry |= 0uLL << 59; // Endianness not inverted 246 entry |= 0ULL << 60; // Not no fault only 247 entry |= 0ULL << 61; // size = 8k 248 entry |= 1ULL << 63; // valid 249 pte = PageTableEntry(entry); 250 251 range.va = vaddr; 252 range.size = 8*(1<<10); 253 range.contextId = asn; 254 range.partitionId = 0; 255 range.real = false; 256 257 valid = true; 258 } 259 260 TlbRange range; 261 PageTableEntry pte; 262 bool used; 263 bool valid; 264 265 Addr 266 pageStart() 267 { 268 return pte.paddr(); 269 } 270 271 void 272 updateVaddr(Addr new_vaddr) 273 { 274 range.va = new_vaddr; 275 } 276 277 void serialize(std::ostream &os); 278 void unserialize(Checkpoint *cp, const std::string §ion); 279}; 280 281} // namespace SparcISA 282 283#endif // __ARCH_SPARC_PAGE_TABLE_HH__ 284 285