nativetrace.cc revision 7678
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/sparc/isa_traits.hh" 32#include "arch/sparc/registers.hh" 33#include "arch/sparc/nativetrace.hh" 34#include "cpu/thread_context.hh" 35#include "params/SparcNativeTrace.hh" 36#include "sim/byteswap.hh" 37 38namespace Trace { 39 40static const char *intRegNames[SparcISA::NumIntArchRegs] = { 41 //Global registers 42 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 43 //Output registers 44 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", 45 //Local registers 46 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", 47 //Input registers 48 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7", 49}; 50 51void 52Trace::SparcNativeTrace::check(NativeTraceRecord *record) 53{ 54 ThreadContext *tc = record->getThread(); 55 56 uint64_t regVal, realRegVal; 57 58 // Integer registers 59 60 // I doubt a real SPARC will describe more integer registers than this. 61 assert(SparcISA::NumIntArchRegs == 32); 62 const char **regName = intRegNames; 63 for (int i = 0; i < SparcISA::NumIntArchRegs; i++) { 64 regVal = tc->readIntReg(i); 65 read(&realRegVal, sizeof(realRegVal)); 66 realRegVal = SparcISA::gtoh(realRegVal); 67 checkReg(*(regName++), regVal, realRegVal); 68 } 69 70 // PC 71 read(&realRegVal, sizeof(realRegVal)); 72 realRegVal = SparcISA::gtoh(realRegVal); 73 regVal = tc->readNextPC(); 74 checkReg("pc", regVal, realRegVal); 75 76 // NPC 77 read(&realRegVal, sizeof(realRegVal)); 78 realRegVal = SparcISA::gtoh(realRegVal); 79 regVal = tc->readNextNPC(); 80 checkReg("npc", regVal, realRegVal); 81 82 // CCR 83 read(&realRegVal, sizeof(realRegVal)); 84 realRegVal = SparcISA::gtoh(realRegVal); 85 regVal = tc->readIntReg(SparcISA::NumIntArchRegs + 2); 86 checkReg("ccr", regVal, realRegVal); 87} 88 89} /* namespace Trace */ 90 91//////////////////////////////////////////////////////////////////////// 92// 93// ExeTracer Simulation Object 94// 95Trace::SparcNativeTrace * 96SparcNativeTraceParams::create() 97{ 98 return new Trace::SparcNativeTrace(this); 99}; 100