nativetrace.cc revision 7811
11689SN/A/* 22329SN/A * Copyright (c) 2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 291689SN/A */ 301689SN/A 311717SN/A#include "arch/sparc/isa_traits.hh" 321060SN/A#include "arch/sparc/registers.hh" 335529Snate@binkert.org#include "arch/sparc/nativetrace.hh" 345529Snate@binkert.org#include "cpu/thread_context.hh" 351060SN/A#include "params/SparcNativeTrace.hh" 365529Snate@binkert.org#include "sim/byteswap.hh" 374329Sktlim@umich.edu 384329Sktlim@umich.edunamespace Trace { 392292SN/A 402292SN/Astatic const char *intRegNames[SparcISA::NumIntArchRegs] = { 412292SN/A // Global registers 422292SN/A "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 435529Snate@binkert.org // Output registers 441060SN/A "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", 452292SN/A // Local registers 462292SN/A "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", 472348SN/A // Input registers 482292SN/A "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7", 492292SN/A}; 502292SN/A 512292SN/Avoid 522292SN/ATrace::SparcNativeTrace::check(NativeTraceRecord *record) 532292SN/A{ 542292SN/A ThreadContext *tc = record->getThread(); 552292SN/A 562292SN/A uint64_t regVal, realRegVal; 572292SN/A 582292SN/A // Integer registers 592292SN/A 602292SN/A // I doubt a real SPARC will describe more integer registers than this. 612292SN/A assert(SparcISA::NumIntArchRegs == 32); 622292SN/A const char **regName = intRegNames; 632292SN/A for (int i = 0; i < SparcISA::NumIntArchRegs; i++) { 642292SN/A regVal = tc->readIntReg(i); 651060SN/A read(&realRegVal, sizeof(realRegVal)); 661060SN/A realRegVal = SparcISA::gtoh(realRegVal); 671062SN/A checkReg(*(regName++), regVal, realRegVal); 681062SN/A } 692292SN/A 701062SN/A SparcISA::PCState pc = tc->pcState(); 711062SN/A // PC 722307SN/A read(&realRegVal, sizeof(realRegVal)); 731062SN/A realRegVal = SparcISA::gtoh(realRegVal); 741062SN/A regVal = pc.npc(); 751062SN/A checkReg("pc", regVal, realRegVal); 762307SN/A 771062SN/A // NPC 781062SN/A read(&realRegVal, sizeof(realRegVal)); 792292SN/A realRegVal = SparcISA::gtoh(realRegVal); 802307SN/A pc.nnpc(); 812292SN/A checkReg("npc", regVal, realRegVal); 822292SN/A 831062SN/A // CCR 842307SN/A read(&realRegVal, sizeof(realRegVal)); 851062SN/A realRegVal = SparcISA::gtoh(realRegVal); 861062SN/A regVal = tc->readIntReg(SparcISA::NumIntArchRegs + 2); 871062SN/A checkReg("ccr", regVal, realRegVal); 882307SN/A} 891062SN/A 901062SN/A} // namespace Trace 912307SN/A 922307SN/A//////////////////////////////////////////////////////////////////////// 932307SN/A// 942307SN/A// ExeTracer Simulation Object 951062SN/A// 962307SN/ATrace::SparcNativeTrace * 971062SN/ASparcNativeTraceParams::create() 981062SN/A{ 991062SN/A return new Trace::SparcNativeTrace(this); 1002307SN/A}; 1011062SN/A