miscregs.hh revision 10288
18706Sandreas.hansson@arm.com/* 28853Sandreas.hansson@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 38706Sandreas.hansson@arm.com * All rights reserved. 48706Sandreas.hansson@arm.com * 58706Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68706Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78706Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88706Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98706Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108706Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118706Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128706Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138706Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 148706Sandreas.hansson@arm.com * this software without specific prior written permission. 158706Sandreas.hansson@arm.com * 168706Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178706Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188706Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198706Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208706Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218706Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228706Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238706Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248706Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258706Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268706Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278706Sandreas.hansson@arm.com * 288706Sandreas.hansson@arm.com * Authors: Gabe Black 298706Sandreas.hansson@arm.com * Ali Saidi 308706Sandreas.hansson@arm.com */ 318706Sandreas.hansson@arm.com 328706Sandreas.hansson@arm.com#ifndef __ARCH_SPARC_MISCREGS_HH__ 338706Sandreas.hansson@arm.com#define __ARCH_SPARC_MISCREGS_HH__ 348706Sandreas.hansson@arm.com 358706Sandreas.hansson@arm.com#include "base/bitunion.hh" 368706Sandreas.hansson@arm.com#include "base/types.hh" 378706Sandreas.hansson@arm.com 388706Sandreas.hansson@arm.comnamespace SparcISA 398706Sandreas.hansson@arm.com{ 408706Sandreas.hansson@arm.comenum MiscRegIndex 418706Sandreas.hansson@arm.com{ 428706Sandreas.hansson@arm.com /** Ancillary State Registers */ 438706Sandreas.hansson@arm.com// MISCREG_Y, 448853Sandreas.hansson@arm.com// MISCREG_CCR, 458853Sandreas.hansson@arm.com MISCREG_ASI, 468853Sandreas.hansson@arm.com MISCREG_TICK, 478853Sandreas.hansson@arm.com MISCREG_FPRS, 488853Sandreas.hansson@arm.com MISCREG_PCR, 498853Sandreas.hansson@arm.com MISCREG_PIC, 508853Sandreas.hansson@arm.com MISCREG_GSR, 518853Sandreas.hansson@arm.com MISCREG_SOFTINT_SET, 528853Sandreas.hansson@arm.com MISCREG_SOFTINT_CLR, 538853Sandreas.hansson@arm.com MISCREG_SOFTINT, /* 10 */ 548853Sandreas.hansson@arm.com MISCREG_TICK_CMPR, 558706Sandreas.hansson@arm.com MISCREG_STICK, 568706Sandreas.hansson@arm.com MISCREG_STICK_CMPR, 578706Sandreas.hansson@arm.com 588706Sandreas.hansson@arm.com /** Privilged Registers */ 598706Sandreas.hansson@arm.com MISCREG_TPC, 608706Sandreas.hansson@arm.com MISCREG_TNPC, 618706Sandreas.hansson@arm.com MISCREG_TSTATE, 628706Sandreas.hansson@arm.com MISCREG_TT, 638706Sandreas.hansson@arm.com MISCREG_PRIVTICK, 648706Sandreas.hansson@arm.com MISCREG_TBA, 658706Sandreas.hansson@arm.com MISCREG_PSTATE, /* 20 */ 668706Sandreas.hansson@arm.com MISCREG_TL, 678706Sandreas.hansson@arm.com MISCREG_PIL, 688706Sandreas.hansson@arm.com MISCREG_CWP, 698706Sandreas.hansson@arm.com// MISCREG_CANSAVE, 708706Sandreas.hansson@arm.com// MISCREG_CANRESTORE, 718853Sandreas.hansson@arm.com// MISCREG_CLEANWIN, 728853Sandreas.hansson@arm.com// MISCREG_OTHERWIN, 738706Sandreas.hansson@arm.com// MISCREG_WSTATE, 748706Sandreas.hansson@arm.com MISCREG_GL, 758706Sandreas.hansson@arm.com 768706Sandreas.hansson@arm.com /** Hyper privileged registers */ 778706Sandreas.hansson@arm.com MISCREG_HPSTATE, /* 30 */ 788706Sandreas.hansson@arm.com MISCREG_HTSTATE, 798706Sandreas.hansson@arm.com MISCREG_HINTP, 808706Sandreas.hansson@arm.com MISCREG_HTBA, 818706Sandreas.hansson@arm.com MISCREG_HVER, 828706Sandreas.hansson@arm.com MISCREG_STRAND_STS_REG, 838706Sandreas.hansson@arm.com MISCREG_HSTICK_CMPR, 848706Sandreas.hansson@arm.com 858706Sandreas.hansson@arm.com /** Floating Point Status Register */ 868853Sandreas.hansson@arm.com MISCREG_FSR, 878853Sandreas.hansson@arm.com 888853Sandreas.hansson@arm.com /** MMU Internal Registers */ 898922Swilliam.wang@arm.com MISCREG_MMU_P_CONTEXT, 908706Sandreas.hansson@arm.com MISCREG_MMU_S_CONTEXT, /* 40 */ 918861Sandreas.hansson@arm.com MISCREG_MMU_PART_ID, 928853Sandreas.hansson@arm.com MISCREG_MMU_LSU_CTRL, 938706Sandreas.hansson@arm.com 948922Swilliam.wang@arm.com /** Scratchpad regiscers **/ 958706Sandreas.hansson@arm.com MISCREG_SCRATCHPAD_R0, /* 60 */ 968706Sandreas.hansson@arm.com MISCREG_SCRATCHPAD_R1, 978706Sandreas.hansson@arm.com MISCREG_SCRATCHPAD_R2, 988706Sandreas.hansson@arm.com MISCREG_SCRATCHPAD_R3, 998706Sandreas.hansson@arm.com MISCREG_SCRATCHPAD_R4, 1008861Sandreas.hansson@arm.com MISCREG_SCRATCHPAD_R5, 1018853Sandreas.hansson@arm.com MISCREG_SCRATCHPAD_R6, 1028706Sandreas.hansson@arm.com MISCREG_SCRATCHPAD_R7, 1038706Sandreas.hansson@arm.com 1048706Sandreas.hansson@arm.com /* CPU Queue Registers */ 1058706Sandreas.hansson@arm.com MISCREG_QUEUE_CPU_MONDO_HEAD, 1068861Sandreas.hansson@arm.com MISCREG_QUEUE_CPU_MONDO_TAIL, 1078853Sandreas.hansson@arm.com MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */ 1088706Sandreas.hansson@arm.com MISCREG_QUEUE_DEV_MONDO_TAIL, 1098706Sandreas.hansson@arm.com MISCREG_QUEUE_RES_ERROR_HEAD, 1108706Sandreas.hansson@arm.com MISCREG_QUEUE_RES_ERROR_TAIL, 1118706Sandreas.hansson@arm.com MISCREG_QUEUE_NRES_ERROR_HEAD, 1128861Sandreas.hansson@arm.com MISCREG_QUEUE_NRES_ERROR_TAIL, 1138706Sandreas.hansson@arm.com 1148706Sandreas.hansson@arm.com /* All the data for the TLB packed up in one register. */ 1158706Sandreas.hansson@arm.com MISCREG_TLB_DATA, 1168706Sandreas.hansson@arm.com MISCREG_NUMMISCREGS 1178706Sandreas.hansson@arm.com}; 1188861Sandreas.hansson@arm.com 1198706Sandreas.hansson@arm.comBitUnion64(HPSTATE) 1208706Sandreas.hansson@arm.com Bitfield<0> tlz; 1218706Sandreas.hansson@arm.com Bitfield<2> hpriv; 1228706Sandreas.hansson@arm.com Bitfield<5> red; 1238706Sandreas.hansson@arm.com Bitfield<10> ibe; 1248861Sandreas.hansson@arm.com Bitfield<11> id; // this impl. dependent (id) field m 1258706Sandreas.hansson@arm.comEndBitUnion(HPSTATE) 1268706Sandreas.hansson@arm.com 1278706Sandreas.hansson@arm.comBitUnion16(PSTATE) 1288706Sandreas.hansson@arm.com Bitfield<1> ie; 1298706Sandreas.hansson@arm.com Bitfield<2> priv; 1308706Sandreas.hansson@arm.com Bitfield<3> am; 1318706Sandreas.hansson@arm.com Bitfield<4> pef; 1328861Sandreas.hansson@arm.com Bitfield<7, 6> mm; 1338706Sandreas.hansson@arm.com Bitfield<8> tle; 1348706Sandreas.hansson@arm.com Bitfield<9> cle; 1358706Sandreas.hansson@arm.com Bitfield<10> pid0; 1368706Sandreas.hansson@arm.com Bitfield<11> pid1; 1378706Sandreas.hansson@arm.comEndBitUnion(PSTATE) 1388706Sandreas.hansson@arm.com 1398861Sandreas.hansson@arm.comstruct STS 1408706Sandreas.hansson@arm.com{ 1418706Sandreas.hansson@arm.com const static int st_idle = 0x00; 1428706Sandreas.hansson@arm.com const static int st_wait = 0x01; 1438706Sandreas.hansson@arm.com const static int st_halt = 0x02; 1448706Sandreas.hansson@arm.com const static int st_run = 0x05; 1458706Sandreas.hansson@arm.com const static int st_spec_run = 0x07; 1468861Sandreas.hansson@arm.com const static int st_spec_rdy = 0x13; 1478706Sandreas.hansson@arm.com const static int st_ready = 0x19; 1488706Sandreas.hansson@arm.com const static int active = 0x01; 1498706Sandreas.hansson@arm.com const static int speculative = 0x04; 1508706Sandreas.hansson@arm.com const static int shft_id = 8; 1518706Sandreas.hansson@arm.com const static int shft_fsm0 = 31; 1528706Sandreas.hansson@arm.com const static int shft_fsm1 = 26; 1538706Sandreas.hansson@arm.com const static int shft_fsm2 = 21; 1548706Sandreas.hansson@arm.com const static int shft_fsm3 = 16; 1558861Sandreas.hansson@arm.com}; 1568706Sandreas.hansson@arm.com 1578706Sandreas.hansson@arm.com 1588706Sandreas.hansson@arm.comconst int NumMiscRegs = MISCREG_NUMMISCREGS; 1598706Sandreas.hansson@arm.com 1608706Sandreas.hansson@arm.com} 1618706Sandreas.hansson@arm.com 1628706Sandreas.hansson@arm.com#endif 1638861Sandreas.hansson@arm.com