miscregs.hh revision 7741
16329Sgblack@eecs.umich.edu/* 26329Sgblack@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 36329Sgblack@eecs.umich.edu * All rights reserved. 46329Sgblack@eecs.umich.edu * 56329Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66329Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76329Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86329Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96329Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106329Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116329Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126329Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136329Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146329Sgblack@eecs.umich.edu * this software without specific prior written permission. 156329Sgblack@eecs.umich.edu * 166329Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176329Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186329Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196329Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206329Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216329Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226329Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236329Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246329Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256329Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266329Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276329Sgblack@eecs.umich.edu * 286329Sgblack@eecs.umich.edu * Authors: Gabe Black 296329Sgblack@eecs.umich.edu * Ali Saidi 306329Sgblack@eecs.umich.edu */ 316329Sgblack@eecs.umich.edu 326329Sgblack@eecs.umich.edu#ifndef __ARCH_SPARC_MISCREGS_HH__ 336329Sgblack@eecs.umich.edu#define __ARCH_SPARC_MISCREGS_HH__ 346329Sgblack@eecs.umich.edu 356329Sgblack@eecs.umich.edu#include "base/types.hh" 366329Sgblack@eecs.umich.edu 376329Sgblack@eecs.umich.edunamespace SparcISA 386329Sgblack@eecs.umich.edu{ 397741Sgblack@eecs.umich.eduenum MiscRegIndex 407741Sgblack@eecs.umich.edu{ 417741Sgblack@eecs.umich.edu /** Ancillary State Registers */ 427741Sgblack@eecs.umich.edu// MISCREG_Y, 437741Sgblack@eecs.umich.edu// MISCREG_CCR, 447741Sgblack@eecs.umich.edu MISCREG_ASI, 457741Sgblack@eecs.umich.edu MISCREG_TICK, 467741Sgblack@eecs.umich.edu MISCREG_FPRS, 477741Sgblack@eecs.umich.edu MISCREG_PCR, 487741Sgblack@eecs.umich.edu MISCREG_PIC, 497741Sgblack@eecs.umich.edu MISCREG_GSR, 507741Sgblack@eecs.umich.edu MISCREG_SOFTINT_SET, 517741Sgblack@eecs.umich.edu MISCREG_SOFTINT_CLR, 527741Sgblack@eecs.umich.edu MISCREG_SOFTINT, /* 10 */ 537741Sgblack@eecs.umich.edu MISCREG_TICK_CMPR, 547741Sgblack@eecs.umich.edu MISCREG_STICK, 557741Sgblack@eecs.umich.edu MISCREG_STICK_CMPR, 566329Sgblack@eecs.umich.edu 577741Sgblack@eecs.umich.edu /** Privilged Registers */ 587741Sgblack@eecs.umich.edu MISCREG_TPC, 597741Sgblack@eecs.umich.edu MISCREG_TNPC, 607741Sgblack@eecs.umich.edu MISCREG_TSTATE, 617741Sgblack@eecs.umich.edu MISCREG_TT, 627741Sgblack@eecs.umich.edu MISCREG_PRIVTICK, 637741Sgblack@eecs.umich.edu MISCREG_TBA, 647741Sgblack@eecs.umich.edu MISCREG_PSTATE, /* 20 */ 657741Sgblack@eecs.umich.edu MISCREG_TL, 667741Sgblack@eecs.umich.edu MISCREG_PIL, 677741Sgblack@eecs.umich.edu MISCREG_CWP, 687741Sgblack@eecs.umich.edu// MISCREG_CANSAVE, 697741Sgblack@eecs.umich.edu// MISCREG_CANRESTORE, 707741Sgblack@eecs.umich.edu// MISCREG_CLEANWIN, 717741Sgblack@eecs.umich.edu// MISCREG_OTHERWIN, 727741Sgblack@eecs.umich.edu// MISCREG_WSTATE, 737741Sgblack@eecs.umich.edu MISCREG_GL, 746329Sgblack@eecs.umich.edu 757741Sgblack@eecs.umich.edu /** Hyper privileged registers */ 767741Sgblack@eecs.umich.edu MISCREG_HPSTATE, /* 30 */ 777741Sgblack@eecs.umich.edu MISCREG_HTSTATE, 787741Sgblack@eecs.umich.edu MISCREG_HINTP, 797741Sgblack@eecs.umich.edu MISCREG_HTBA, 807741Sgblack@eecs.umich.edu MISCREG_HVER, 817741Sgblack@eecs.umich.edu MISCREG_STRAND_STS_REG, 827741Sgblack@eecs.umich.edu MISCREG_HSTICK_CMPR, 836329Sgblack@eecs.umich.edu 847741Sgblack@eecs.umich.edu /** Floating Point Status Register */ 857741Sgblack@eecs.umich.edu MISCREG_FSR, 866329Sgblack@eecs.umich.edu 877741Sgblack@eecs.umich.edu /** MMU Internal Registers */ 887741Sgblack@eecs.umich.edu MISCREG_MMU_P_CONTEXT, 897741Sgblack@eecs.umich.edu MISCREG_MMU_S_CONTEXT, /* 40 */ 907741Sgblack@eecs.umich.edu MISCREG_MMU_PART_ID, 917741Sgblack@eecs.umich.edu MISCREG_MMU_LSU_CTRL, 926329Sgblack@eecs.umich.edu 937741Sgblack@eecs.umich.edu /** Scratchpad regiscers **/ 947741Sgblack@eecs.umich.edu MISCREG_SCRATCHPAD_R0, /* 60 */ 957741Sgblack@eecs.umich.edu MISCREG_SCRATCHPAD_R1, 967741Sgblack@eecs.umich.edu MISCREG_SCRATCHPAD_R2, 977741Sgblack@eecs.umich.edu MISCREG_SCRATCHPAD_R3, 987741Sgblack@eecs.umich.edu MISCREG_SCRATCHPAD_R4, 997741Sgblack@eecs.umich.edu MISCREG_SCRATCHPAD_R5, 1007741Sgblack@eecs.umich.edu MISCREG_SCRATCHPAD_R6, 1017741Sgblack@eecs.umich.edu MISCREG_SCRATCHPAD_R7, 1026329Sgblack@eecs.umich.edu 1037741Sgblack@eecs.umich.edu /* CPU Queue Registers */ 1047741Sgblack@eecs.umich.edu MISCREG_QUEUE_CPU_MONDO_HEAD, 1057741Sgblack@eecs.umich.edu MISCREG_QUEUE_CPU_MONDO_TAIL, 1067741Sgblack@eecs.umich.edu MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */ 1077741Sgblack@eecs.umich.edu MISCREG_QUEUE_DEV_MONDO_TAIL, 1087741Sgblack@eecs.umich.edu MISCREG_QUEUE_RES_ERROR_HEAD, 1097741Sgblack@eecs.umich.edu MISCREG_QUEUE_RES_ERROR_TAIL, 1107741Sgblack@eecs.umich.edu MISCREG_QUEUE_NRES_ERROR_HEAD, 1117741Sgblack@eecs.umich.edu MISCREG_QUEUE_NRES_ERROR_TAIL, 1126329Sgblack@eecs.umich.edu 1137741Sgblack@eecs.umich.edu /* All the data for the TLB packed up in one register. */ 1147741Sgblack@eecs.umich.edu MISCREG_TLB_DATA, 1157741Sgblack@eecs.umich.edu MISCREG_NUMMISCREGS 1167741Sgblack@eecs.umich.edu}; 1176329Sgblack@eecs.umich.edu 1187741Sgblack@eecs.umich.edustruct HPSTATE 1197741Sgblack@eecs.umich.edu{ 1207741Sgblack@eecs.umich.edu const static uint64_t id = 0x800; // this impl. dependent (id) field m 1217741Sgblack@eecs.umich.edu const static uint64_t ibe = 0x400; 1227741Sgblack@eecs.umich.edu const static uint64_t red = 0x20; 1237741Sgblack@eecs.umich.edu const static uint64_t hpriv = 0x4; 1247741Sgblack@eecs.umich.edu const static uint64_t tlz = 0x1; 1257741Sgblack@eecs.umich.edu}; 1266329Sgblack@eecs.umich.edu 1276329Sgblack@eecs.umich.edu 1287741Sgblack@eecs.umich.edustruct PSTATE 1297741Sgblack@eecs.umich.edu{ 1307741Sgblack@eecs.umich.edu const static int cle = 0x200; 1317741Sgblack@eecs.umich.edu const static int tle = 0x100; 1327741Sgblack@eecs.umich.edu const static int mm = 0xC0; 1337741Sgblack@eecs.umich.edu const static int pef = 0x10; 1347741Sgblack@eecs.umich.edu const static int am = 0x8; 1357741Sgblack@eecs.umich.edu const static int priv = 0x4; 1367741Sgblack@eecs.umich.edu const static int ie = 0x2; 1377741Sgblack@eecs.umich.edu}; 1386329Sgblack@eecs.umich.edu 1397741Sgblack@eecs.umich.edustruct STS 1407741Sgblack@eecs.umich.edu{ 1417741Sgblack@eecs.umich.edu const static int st_idle = 0x00; 1427741Sgblack@eecs.umich.edu const static int st_wait = 0x01; 1437741Sgblack@eecs.umich.edu const static int st_halt = 0x02; 1447741Sgblack@eecs.umich.edu const static int st_run = 0x05; 1457741Sgblack@eecs.umich.edu const static int st_spec_run = 0x07; 1467741Sgblack@eecs.umich.edu const static int st_spec_rdy = 0x13; 1477741Sgblack@eecs.umich.edu const static int st_ready = 0x19; 1487741Sgblack@eecs.umich.edu const static int active = 0x01; 1497741Sgblack@eecs.umich.edu const static int speculative = 0x04; 1507741Sgblack@eecs.umich.edu const static int shft_id = 8; 1517741Sgblack@eecs.umich.edu const static int shft_fsm0 = 31; 1527741Sgblack@eecs.umich.edu const static int shft_fsm1 = 26; 1537741Sgblack@eecs.umich.edu const static int shft_fsm2 = 21; 1547741Sgblack@eecs.umich.edu const static int shft_fsm3 = 16; 1557741Sgblack@eecs.umich.edu}; 1566329Sgblack@eecs.umich.edu 1576329Sgblack@eecs.umich.edu 1587741Sgblack@eecs.umich.educonst int NumMiscArchRegs = MISCREG_NUMMISCREGS; 1597741Sgblack@eecs.umich.educonst int NumMiscRegs = MISCREG_NUMMISCREGS; 1607741Sgblack@eecs.umich.edu 1616329Sgblack@eecs.umich.edu} 1626329Sgblack@eecs.umich.edu 1636329Sgblack@eecs.umich.edu#endif 164