isa_traits.hh revision 3414:b57e400b2933
17584SN/A/* 28869SAli.Saidi@ARM.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 37584SN/A * All rights reserved. 47584SN/A * 57584SN/A * Redistribution and use in source and binary forms, with or without 67584SN/A * modification, are permitted provided that the following conditions are 77584SN/A * met: redistributions of source code must retain the above copyright 87584SN/A * notice, this list of conditions and the following disclaimer; 97584SN/A * redistributions in binary form must reproduce the above copyright 107584SN/A * notice, this list of conditions and the following disclaimer in the 117584SN/A * documentation and/or other materials provided with the distribution; 127584SN/A * neither the name of the copyright holders nor the names of its 137584SN/A * contributors may be used to endorse or promote products derived from 147584SN/A * this software without specific prior written permission. 157584SN/A * 167584SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177584SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187584SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197584SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207584SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217584SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227584SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237584SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247584SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257584SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267584SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277584SN/A * 287584SN/A * Authors: Gabe Black 297584SN/A */ 307584SN/A 317584SN/A#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 327584SN/A#define __ARCH_SPARC_ISA_TRAITS_HH__ 337584SN/A 347584SN/A#include "arch/sparc/types.hh" 357584SN/A#include "base/misc.hh" 367584SN/A#include "config/full_system.hh" 377584SN/A#include "sim/host.hh" 387584SN/A 397584SN/Aclass ThreadContext; 408869SAli.Saidi@ARM.comclass FastCPU; 418869SAli.Saidi@ARM.com//class FullCPU; 427584SN/Aclass Checkpoint; 437584SN/A 447584SN/Aclass StaticInst; 458869SAli.Saidi@ARM.comclass StaticInstPtr; 467584SN/A 477584SN/Anamespace BigEndianGuest {} 488869SAli.Saidi@ARM.com 497584SN/A#if FULL_SYSTEM 507584SN/A#include "arch/sparc/isa_fullsys_traits.hh" 518869SAli.Saidi@ARM.com#endif 527584SN/A 537584SN/Anamespace SparcISA 548869SAli.Saidi@ARM.com{ 558869SAli.Saidi@ARM.com class RegFile; 568869SAli.Saidi@ARM.com 578869SAli.Saidi@ARM.com //This makes sure the big endian versions of certain functions are used. 588869SAli.Saidi@ARM.com using namespace BigEndianGuest; 598869SAli.Saidi@ARM.com 608869SAli.Saidi@ARM.com // SPARC have a delay slot 618869SAli.Saidi@ARM.com #define ISA_HAS_DELAY_SLOT 1 628869SAli.Saidi@ARM.com 637584SN/A // SPARC NOP (sethi %(hi(0), g0) 647584SN/A const MachInst NoopMachInst = 0x01000000; 658869SAli.Saidi@ARM.com 668869SAli.Saidi@ARM.com const int NumIntRegs = 32; 678869SAli.Saidi@ARM.com const int NumFloatRegs = 64; 687584SN/A const int NumMiscRegs = 40; 698869SAli.Saidi@ARM.com 708869SAli.Saidi@ARM.com // These enumerate all the registers for dependence tracking. 718869SAli.Saidi@ARM.com enum DependenceTags { 728869SAli.Saidi@ARM.com // 0..31 are the integer regs 0..31 738869SAli.Saidi@ARM.com // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 748869SAli.Saidi@ARM.com FP_Base_DepTag = NumIntRegs, 758869SAli.Saidi@ARM.com Ctrl_Base_DepTag = NumIntRegs + NumFloatRegs, 768869SAli.Saidi@ARM.com //XXX These are here solely to get compilation and won't work 778869SAli.Saidi@ARM.com Fpcr_DepTag = 0, 788869SAli.Saidi@ARM.com Uniq_DepTag = 0 798869SAli.Saidi@ARM.com }; 808869SAli.Saidi@ARM.com 818869SAli.Saidi@ARM.com 828869SAli.Saidi@ARM.com // MAXTL - maximum trap level 838869SAli.Saidi@ARM.com const int MaxPTL = 2; 848869SAli.Saidi@ARM.com const int MaxTL = 6; 858869SAli.Saidi@ARM.com const int MaxGL = 3; 868869SAli.Saidi@ARM.com const int MaxPGL = 2; 878869SAli.Saidi@ARM.com 888869SAli.Saidi@ARM.com // NWINDOWS - number of register windows, can be 3 to 32 898869SAli.Saidi@ARM.com const int NWindows = 32; 908869SAli.Saidi@ARM.com 918869SAli.Saidi@ARM.com // semantically meaningful register indices 928869SAli.Saidi@ARM.com const int ZeroReg = 0; // architecturally meaningful 938869SAli.Saidi@ARM.com // the rest of these depend on the ABI 948869SAli.Saidi@ARM.com const int StackPointerReg = 14; 958869SAli.Saidi@ARM.com const int ReturnAddressReg = 31; // post call, precall is 15 968869SAli.Saidi@ARM.com const int ReturnValueReg = 8; // Post return, 24 is pre-return. 978869SAli.Saidi@ARM.com const int FramePointerReg = 30; 988869SAli.Saidi@ARM.com const int ArgumentReg0 = 8; 998869SAli.Saidi@ARM.com const int ArgumentReg1 = 9; 1008869SAli.Saidi@ARM.com const int ArgumentReg2 = 10; 1017584SN/A const int ArgumentReg3 = 11; 1027584SN/A const int ArgumentReg4 = 12; 1038869SAli.Saidi@ARM.com const int ArgumentReg5 = 13; 1047584SN/A // Some OS syscall use a second register (o1) to return a second value 1057584SN/A const int SyscallPseudoReturnReg = ArgumentReg1; 1067584SN/A 1077584SN/A //XXX These numbers are bogus 1087584SN/A const int MaxInstSrcRegs = 8; 1097584SN/A const int MaxInstDestRegs = 9; 1107584SN/A 1117584SN/A //8K. This value is implmentation specific; and should probably 1127584SN/A //be somewhere else. 1138869SAli.Saidi@ARM.com const int LogVMPageSize = 13; 1147584SN/A const int VMPageSize = (1 << LogVMPageSize); 1157584SN/A 1167584SN/A //Why does both the previous set of constants and this one exist? 1177584SN/A const int PageShift = 13; 1187584SN/A const int PageBytes = ULL(1) << PageShift; 1197584SN/A 1207584SN/A const int BranchPredAddrShiftAmt = 2; 1217584SN/A 1227584SN/A const int MachineBytes = 8; 1238869SAli.Saidi@ARM.com const int WordBytes = 4; 1247584SN/A const int HalfwordBytes = 2; 1257584SN/A const int ByteBytes = 1; 1267584SN/A 1277584SN/A void serialize(std::ostream & os); 1287584SN/A 1297584SN/A void unserialize(Checkpoint *cp, const std::string §ion); 1307584SN/A 1317584SN/A StaticInstPtr decodeInst(ExtMachInst); 1327584SN/A 1337584SN/A // return a no-op instruction... used for instruction fetch faults 1347584SN/A extern const MachInst NoopMachInst; 1358869SAli.Saidi@ARM.com} 1367584SN/A 137#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 138