isa_traits.hh revision 2680
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Korey Sewell 29 * Gabe Black 30 */ 31 32#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 33#define __ARCH_SPARC_ISA_TRAITS_HH__ 34 35#include "base/misc.hh" 36#include "config/full_system.hh" 37#include "sim/host.hh" 38 39class ThreadContext; 40class FastCPU; 41//class FullCPU; 42class Checkpoint; 43 44class StaticInst; 45class StaticInstPtr; 46 47namespace BigEndianGuest {} 48 49#if !FULL_SYSTEM 50class SyscallReturn 51{ 52 public: 53 template <class T> 54 SyscallReturn(T v, bool s) 55 { 56 retval = (uint64_t)v; 57 success = s; 58 } 59 60 template <class T> 61 SyscallReturn(T v) 62 { 63 success = (v >= 0); 64 retval = (uint64_t)v; 65 } 66 67 ~SyscallReturn() {} 68 69 SyscallReturn& operator=(const SyscallReturn& s) 70 { 71 retval = s.retval; 72 success = s.success; 73 return *this; 74 } 75 76 bool successful() { return success; } 77 uint64_t value() { return retval; } 78 79 private: 80 uint64_t retval; 81 bool success; 82}; 83 84#endif 85 86#if FULL_SYSTEM 87#include "arch/sparc/isa_fullsys_traits.hh" 88#endif 89 90namespace SparcISA 91{ 92 93 // These enumerate all the registers for dependence tracking. 94 enum DependenceTags { 95 // 0..31 are the integer regs 0..31 96 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 97 FP_Base_DepTag = 32, 98 Ctrl_Base_DepTag = 96, 99 //XXX These are here solely to get compilation and won't work 100 Fpcr_DepTag = 0, 101 Uniq_DepTag = 0 102 }; 103 104 //This makes sure the big endian versions of certain functions are used. 105 using namespace BigEndianGuest; 106 107 typedef uint32_t MachInst; 108 typedef uint64_t ExtMachInst; 109 110 const int NumIntRegs = 32; 111 const int NumFloatRegs = 64; 112 const int NumMiscRegs = 32; 113 114 // semantically meaningful register indices 115 const int ZeroReg = 0; // architecturally meaningful 116 // the rest of these depend on the ABI 117 const int StackPointerReg = 14; 118 const int ReturnAddressReg = 31; // post call, precall is 15 119 const int ReturnValueReg = 8; // Post return, 24 is pre-return. 120 const int FramePointerReg = 30; 121 const int ArgumentReg0 = 8; 122 const int ArgumentReg1 = 9; 123 const int ArgumentReg2 = 10; 124 const int ArgumentReg3 = 11; 125 const int ArgumentReg4 = 12; 126 const int ArgumentReg5 = 13; 127 // Some OS syscall use a second register (o1) to return a second value 128 const int SyscallPseudoReturnReg = ArgumentReg1; 129 130 //XXX These numbers are bogus 131 const int MaxInstSrcRegs = 8; 132 const int MaxInstDestRegs = 9; 133 134 typedef uint64_t IntReg; 135 136 // control register file contents 137 typedef uint64_t MiscReg; 138 139 typedef double FloatReg; 140 typedef uint64_t FloatRegBits; 141 142 //8K. This value is implmentation specific; and should probably 143 //be somewhere else. 144 const int LogVMPageSize = 13; 145 const int VMPageSize = (1 << LogVMPageSize); 146 147 //Why does both the previous set of constants and this one exist? 148 const int PageShift = 13; 149 const int PageBytes = ULL(1) << PageShift; 150 151 const int BranchPredAddrShiftAmt = 2; 152 153 const int MachineBytes = 8; 154 const int WordBytes = 4; 155 const int HalfwordBytes = 2; 156 const int ByteBytes = 1; 157 158 void serialize(std::ostream & os); 159 160 void unserialize(Checkpoint *cp, const std::string §ion); 161 162 StaticInstPtr decodeInst(ExtMachInst); 163 164 // return a no-op instruction... used for instruction fetch faults 165 extern const MachInst NoopMachInst; 166} 167 168#include "arch/sparc/regfile.hh" 169 170namespace SparcISA 171{ 172 173#if !FULL_SYSTEM 174 static inline void setSyscallReturn(SyscallReturn return_value, 175 RegFile *regs) 176 { 177 // check for error condition. SPARC syscall convention is to 178 // indicate success/failure in reg the carry bit of the ccr 179 // and put the return value itself in the standard return value reg (). 180 if (return_value.successful()) { 181 // no error, clear XCC.C 182 regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) & 0xEF); 183 regs->setIntReg(ReturnValueReg, return_value.value()); 184 } else { 185 // got an error, set XCC.C 186 regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) | 0x10); 187 regs->setIntReg(ReturnValueReg, return_value.value()); 188 } 189 } 190#endif 191}; 192 193#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 194