isa_traits.hh revision 2225
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 30#define __ARCH_SPARC_ISA_TRAITS_HH__ 31 32#include "arch/sparc/faults.hh" 33#include "base/misc.hh" 34#include "config/full_system.hh" 35#include "sim/host.hh" 36 37//This makes sure the big endian versions of certain functions are used. 38namespace BigEndianGuest {} 39using namespace BigEndianGuest; 40 41class ExecContext; 42class FastCPU; 43//class FullCPU; 44class Checkpoint; 45 46#define TARGET_SPARC 47 48class StaticInst; 49class StaticInstPtr; 50 51//namespace EV5 52//{ 53// int DTB_ASN_ASN(uint64_t reg); 54// int ITB_ASN_ASN(uint64_t reg); 55//} 56 57namespace SparcISA 58{ 59 typedef uint32_t MachInst; 60 typedef uint64_t Addr; 61 typedef uint8_t RegIndex; 62 63 enum 64 { 65 MemoryEnd = 0xffffffffffffffffULL, 66 67 NumFloatRegs = 32, 68 NumMiscRegs = 32, 69 70 MaxRegsOfAnyType = 32, 71 // Static instruction parameters 72 MaxInstSrcRegs = 3, 73 MaxInstDestRegs = 2, 74 75 // Maximum trap level 76 MaxTL = 4, 77 78 // semantically meaningful register indices 79 ZeroReg = 0 // architecturally meaningful 80 // the rest of these depend on the ABI 81 }; 82 typedef uint64_t IntReg; 83 84 class IntRegFile 85 { 86 private: 87 //For right now, let's pretend the register file is static 88 IntReg regs[32]; 89 public: 90 IntReg & operator [] (RegIndex index) 91 { 92 //Don't allow indexes outside of the 32 registers 93 index &= 0x1F; 94 return regs[index]; 95 } 96 }; 97 98 void serialize(std::ostream & os); 99 100 void unserialize(Checkpoint *cp, const std::string §ion); 101 102 class FloatRegFile 103 { 104 private: 105 //By using the largest data type, we ensure everything 106 //is aligned correctly in memory 107 union 108 { 109 long double rawRegs[16]; 110 uint64_t regDump[32]; 111 }; 112 class QuadRegs 113 { 114 private: 115 FloatRegFile * parent; 116 public: 117 QuadRegs(FloatRegFile * p) : parent(p) {;} 118 long double & operator [] (RegIndex index) 119 { 120 //Quad floats are index by the single 121 //precision register the start on, 122 //and only 16 should be accessed 123 index = (index >> 2) & 0xF; 124 return parent->rawRegs[index]; 125 } 126 }; 127 class DoubleRegs 128 { 129 private: 130 FloatRegFile * parent; 131 public: 132 DoubleRegs(FloatRegFile * p) : parent(p) {;} 133 double & operator [] (RegIndex index) 134 { 135 //Double floats are index by the single 136 //precision register the start on, 137 //and only 32 should be accessed 138 index = (index >> 1) & 0x1F; 139 return ((double *)parent->rawRegs)[index]; 140 } 141 }; 142 class SingleRegs 143 { 144 private: 145 FloatRegFile * parent; 146 public: 147 SingleRegs(FloatRegFile * p) : parent(p) {;} 148 float & operator [] (RegIndex index) 149 { 150 //Only 32 single floats should be accessed 151 index &= 0x1F; 152 return ((float *)parent->rawRegs)[index]; 153 } 154 }; 155 public: 156 void serialize(std::ostream & os); 157 158 void unserialize(Checkpoint * cp, std::string & section); 159 160 QuadRegs quadRegs; 161 DoubleRegs doubleRegs; 162 SingleRegs singleRegs; 163 FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this) 164 {;} 165 }; 166 167 // control register file contents 168 typedef uint64_t MiscReg; 169 // The control registers, broken out into fields 170 class MiscRegFile 171 { 172 public: 173 union 174 { 175 uint16_t pstate; // Process State Register 176 struct 177 { 178 uint16_t ag:1; // Alternate Globals 179 uint16_t ie:1; // Interrupt enable 180 uint16_t priv:1; // Privelege mode 181 uint16_t am:1; // Address mask 182 uint16_t pef:1; // PSTATE enable floating-point 183 uint16_t red:1; // RED (reset, error, debug) state 184 uint16_t mm:2; // Memory Model 185 uint16_t tle:1; // Trap little-endian 186 uint16_t cle:1; // Current little-endian 187 } pstateFields; 188 }; 189 uint64_t tba; // Trap Base Address 190 union 191 { 192 uint64_t y; // Y (used in obsolete multiplication) 193 struct 194 { 195 uint64_t value:32; // The actual value stored in y 196 const uint64_t :32; // reserved bits 197 } yFields; 198 }; 199 uint8_t pil; // Process Interrupt Register 200 uint8_t cwp; // Current Window Pointer 201 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured 202 // on the previous level) 203 union 204 { 205 uint8_t ccr; // Condition Code Register 206 struct 207 { 208 union 209 { 210 uint8_t icc:4; // 32-bit condition codes 211 struct 212 { 213 uint8_t c:1; // Carry 214 uint8_t v:1; // Overflow 215 uint8_t z:1; // Zero 216 uint8_t n:1; // Negative 217 } iccFields:4; 218 } :4; 219 union 220 { 221 uint8_t xcc:4; // 64-bit condition codes 222 struct 223 { 224 uint8_t c:1; // Carry 225 uint8_t v:1; // Overflow 226 uint8_t z:1; // Zero 227 uint8_t n:1; // Negative 228 } xccFields:4; 229 } :4; 230 } ccrFields; 231 }; 232 uint8_t asi; // Address Space Identifier 233 uint8_t tl; // Trap Level 234 uint64_t tpc[MaxTL]; // Trap Program Counter (value from 235 // previous trap level) 236 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from 237 // previous trap level) 238 union 239 { 240 uint64_t tstate[MaxTL]; // Trap State 241 struct 242 { 243 //Values are from previous trap level 244 uint64_t cwp:5; // Current Window Pointer 245 const uint64_t :2; // Reserved bits 246 uint64_t pstate:10; // Process State 247 const uint64_t :6; // Reserved bits 248 uint64_t asi:8; // Address Space Identifier 249 uint64_t ccr:8; // Condition Code Register 250 } tstateFields[MaxTL]; 251 }; 252 union 253 { 254 uint64_t tick; // Hardware clock-tick counter 255 struct 256 { 257 uint64_t counter:63; // Clock-tick count 258 uint64_t npt:1; // Non-priveleged trap 259 } tickFields; 260 } 261 uint8_t cansave; // Savable windows 262 uint8_t canrestore; // Restorable windows 263 uint8_t otherwin; // Other windows 264 uint8_t cleanwin; // Clean windows 265 union 266 { 267 uint8_t wstate; // Window State 268 struct 269 { 270 uint8_t normal:3; // Bits TT<4:2> are set to on a normal 271 // register window trap 272 uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin" 273 // register window trap 274 } wstateFields; 275 }; 276 union 277 { 278 uint64_t ver; // Version 279 struct 280 { 281 uint64_t maxwin:5; // Max CWP value 282 const uint64_t :2; // Reserved bits 283 uint64_t maxtl:8; // Maximum trap level 284 const uint64_t :8; // Reserved bits 285 uint64_t mask:8; // Processor mask set revision number 286 uint64_t impl:16; // Implementation identification number 287 uint64_t manuf:16; // Manufacturer code 288 } verFields; 289 }; 290 union 291 { 292 uint64_t fsr; // Floating-Point State Register 293 struct 294 { 295 union 296 { 297 uint64_t cexc:5; // Current excpetion 298 struct 299 { 300 uint64_t nxc:1; // Inexact 301 uint64_t dzc:1; // Divide by zero 302 uint64_t ufc:1; // Underflow 303 uint64_t ofc:1; // Overflow 304 uint64_t nvc:1; // Invalid operand 305 } cexecFields:5; 306 } :5; 307 union 308 { 309 uint64_t aexc:5; // Accrued exception 310 struct 311 { 312 uint64_t nxc:1; // Inexact 313 uint64_t dzc:1; // Divide by zero 314 uint64_t ufc:1; // Underflow 315 uint64_t ofc:1; // Overflow 316 uint64_t nvc:1; // Invalid operand 317 } aexecFields:5; 318 } :5; 319 uint64_t fcc0:2; // Floating-Point condtion codes 320 const uint64_t :1; // Reserved bits 321 uint64_t qne:1; // Deferred trap queue not empty 322 // with no queue, it should read 0 323 uint64_t ftt:3; // Floating-Point trap type 324 uint64_t ver:3; // Version (of the FPU) 325 const uint64_t :2; // Reserved bits 326 uint64_t ns:1; // Nonstandard floating point 327 union 328 { 329 uint64_t tem:5; // Trap Enable Mask 330 struct 331 { 332 uint64_t nxm:1; // Inexact 333 uint64_t dzm:1; // Divide by zero 334 uint64_t ufm:1; // Underflow 335 uint64_t ofm:1; // Overflow 336 uint64_t nvm:1; // Invalid operand 337 } temFields:5; 338 } :5; 339 const uint64_t :2; // Reserved bits 340 uint64_t rd:2; // Rounding direction 341 uint64_t fcc1:2; // Floating-Point condition codes 342 uint64_t fcc2:2; // Floating-Point condition codes 343 uint64_t fcc3:2; // Floating-Point condition codes 344 const uint64_t :26; // Reserved bits 345 } fsrFields; 346 } 347 union 348 { 349 uint8_t fprs; // Floating-Point Register State 350 struct 351 { 352 uint8_t dl:1; // Dirty lower 353 uint8_t du:1; // Dirty upper 354 fef:1; // FPRS enable floating-Point 355 } fprsFields; 356 }; 357 358 void serialize(std::ostream & os) 359 { 360 SERIALIZE_SCALAR(pstate); 361 SERIAlIZE_SCALAR(tba); 362 SERIALIZE_SCALAR(y); 363 SERIALIZE_SCALAR(pil); 364 SERIALIZE_SCALAR(cwp); 365 SERIALIZE_ARRAY(tt, MaxTL); 366 SERIALIZE_SCALAR(ccr); 367 SERIALIZE_SCALAR(asi); 368 SERIALIZE_SCALAR(tl); 369 SERIALIZE_SCALAR(tpc); 370 SERIALIZE_SCALAR(tnpc); 371 SERIALIZE_ARRAY(tstate, MaxTL); 372 SERIALIZE_SCALAR(tick); 373 SERIALIZE_SCALAR(cansave); 374 SERIALIZE_SCALAR(canrestore); 375 SERIALIZE_SCALAR(otherwin); 376 SERIALIZE_SCALAR(cleanwin); 377 SERIALIZE_SCALAR(wstate); 378 SERIALIZE_SCALAR(ver); 379 SERIALIZE_SCALAR(fsr); 380 SERIALIZE_SCALAR(fprs); 381 } 382 383 void unserialize(Checkpoint &* cp, std::string & section) 384 { 385 UNSERIALIZE_SCALAR(pstate); 386 UNSERIAlIZE_SCALAR(tba); 387 UNSERIALIZE_SCALAR(y); 388 UNSERIALIZE_SCALAR(pil); 389 UNSERIALIZE_SCALAR(cwp); 390 UNSERIALIZE_ARRAY(tt, MaxTL); 391 UNSERIALIZE_SCALAR(ccr); 392 UNSERIALIZE_SCALAR(asi); 393 UNSERIALIZE_SCALAR(tl); 394 UNSERIALIZE_SCALAR(tpc); 395 UNSERIALIZE_SCALAR(tnpc); 396 UNSERIALIZE_ARRAY(tstate, MaxTL); 397 UNSERIALIZE_SCALAR(tick); 398 UNSERIALIZE_SCALAR(cansave); 399 UNSERIALIZE_SCALAR(canrestore); 400 UNSERIALIZE_SCALAR(otherwin); 401 UNSERIALIZE_SCALAR(cleanwin); 402 UNSERIALIZE_SCALAR(wstate); 403 UNSERIALIZE_SCALAR(ver); 404 UNSERIALIZE_SCALAR(fsr); 405 UNSERIALIZE_SCALAR(fprs); 406 } 407 }; 408 409 typedef union 410 { 411 IntReg intreg; 412 FloatReg fpreg; 413 MiscReg ctrlreg; 414 } AnyReg; 415 416 struct RegFile 417 { 418 IntRegFile intRegFile; // (signed) integer register file 419 FloatRegFile floatRegFile; // floating point register file 420 MiscRegFile miscRegFile; // control register file 421 422 Addr pc; // Program Counter 423 Addr npc; // Next Program Counter 424 425 void serialize(std::ostream &os); 426 void unserialize(Checkpoint *cp, const std::string §ion); 427 }; 428 429 static StaticInstPtr decodeInst(MachInst); 430 431 // return a no-op instruction... used for instruction fetch faults 432 static const MachInst NoopMachInst; 433 434 // Instruction address compression hooks 435 static inline Addr realPCToFetchPC(const Addr &addr) 436 { 437 return addr; 438 } 439 440 static inline Addr fetchPCToRealPC(const Addr &addr) 441 { 442 return addr; 443 } 444 445 // the size of "fetched" instructions (not necessarily the size 446 // of real instructions for PISA) 447 static inline size_t fetchInstSize() 448 { 449 return sizeof(MachInst); 450 } 451 452 /** 453 * Function to insure ISA semantics about 0 registers. 454 * @param xc The execution context. 455 */ 456 template <class XC> 457 static void zeroRegisters(XC *xc); 458}; 459 460const int VMPageSize = TheISA::VMPageSize; 461const int LogVMPageSize = TheISA::LogVMPageSize; 462const int ZeroReg = TheISA::ZeroReg; 463const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; 464const int MaxAddr = (Addr)-1; 465 466#if !FULL_SYSTEM 467class SyscallReturn 468{ 469 public: 470 template <class T> 471 SyscallReturn(T v, bool s) 472 { 473 retval = (uint64_t)v; 474 success = s; 475 } 476 477 template <class T> 478 SyscallReturn(T v) 479 { 480 success = (v >= 0); 481 retval = (uint64_t)v; 482 } 483 484 ~SyscallReturn() {} 485 486 SyscallReturn& operator=(const SyscallReturn& s) 487 { 488 retval = s.retval; 489 success = s.success; 490 return *this; 491 } 492 493 bool successful() { return success; } 494 uint64_t value() { return retval; } 495 496 private: 497 uint64_t retval; 498 bool success; 499}; 500 501#endif 502 503 504#if FULL_SYSTEM 505 506#include "arch/alpha/ev5.hh" 507#endif 508 509#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 510