isa_traits.hh revision 2646
12023SN/A/* 22023SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32023SN/A * All rights reserved. 42023SN/A * 52023SN/A * Redistribution and use in source and binary forms, with or without 62023SN/A * modification, are permitted provided that the following conditions are 72023SN/A * met: redistributions of source code must retain the above copyright 82023SN/A * notice, this list of conditions and the following disclaimer; 92023SN/A * redistributions in binary form must reproduce the above copyright 102023SN/A * notice, this list of conditions and the following disclaimer in the 112023SN/A * documentation and/or other materials provided with the distribution; 122023SN/A * neither the name of the copyright holders nor the names of its 132023SN/A * contributors may be used to endorse or promote products derived from 142023SN/A * this software without specific prior written permission. 152023SN/A * 162023SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172023SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182023SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192023SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202023SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212023SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222023SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242023SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252023SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262023SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272023SN/A */ 282023SN/A 292023SN/A#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 302023SN/A#define __ARCH_SPARC_ISA_TRAITS_HH__ 312023SN/A 322225SN/A#include "base/misc.hh" 332225SN/A#include "config/full_system.hh" 342225SN/A#include "sim/host.hh" 352225SN/A 362225SN/Aclass ExecContext; 372023SN/Aclass FastCPU; 382023SN/A//class FullCPU; 392225SN/Aclass Checkpoint; 402023SN/A 412225SN/Aclass StaticInst; 422225SN/Aclass StaticInstPtr; 432023SN/A 442458SN/Anamespace BigEndianGuest {} 452023SN/A 462225SN/A#if !FULL_SYSTEM 472225SN/Aclass SyscallReturn 482225SN/A{ 492225SN/A public: 502225SN/A template <class T> 512225SN/A SyscallReturn(T v, bool s) 522225SN/A { 532225SN/A retval = (uint64_t)v; 542225SN/A success = s; 552225SN/A } 562023SN/A 572225SN/A template <class T> 582225SN/A SyscallReturn(T v) 592225SN/A { 602225SN/A success = (v >= 0); 612225SN/A retval = (uint64_t)v; 622225SN/A } 632023SN/A 642225SN/A ~SyscallReturn() {} 652023SN/A 662225SN/A SyscallReturn& operator=(const SyscallReturn& s) 672225SN/A { 682225SN/A retval = s.retval; 692225SN/A success = s.success; 702225SN/A return *this; 712225SN/A } 722023SN/A 732225SN/A bool successful() { return success; } 742225SN/A uint64_t value() { return retval; } 752023SN/A 762225SN/A private: 772225SN/A uint64_t retval; 782225SN/A bool success; 792023SN/A}; 802023SN/A 812023SN/A#endif 822023SN/A 832023SN/A 842458SN/Anamespace SparcISA 852458SN/A{ 862469SN/A 872469SN/A // These enumerate all the registers for dependence tracking. 882469SN/A enum DependenceTags { 892469SN/A // 0..31 are the integer regs 0..31 902469SN/A // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 912469SN/A FP_Base_DepTag = 32, 922469SN/A Ctrl_Base_DepTag = 96, 932501SN/A //XXX These are here solely to get compilation and won't work 942501SN/A Fpcr_DepTag = 0, 952501SN/A Uniq_DepTag = 0 962469SN/A }; 972469SN/A 982458SN/A //This makes sure the big endian versions of certain functions are used. 992458SN/A using namespace BigEndianGuest; 1002023SN/A 1012458SN/A typedef uint32_t MachInst; 1022458SN/A typedef uint64_t ExtMachInst; 1032458SN/A 1042458SN/A const int NumIntRegs = 32; 1052458SN/A const int NumFloatRegs = 64; 1062458SN/A const int NumMiscRegs = 32; 1072458SN/A 1082458SN/A // semantically meaningful register indices 1092458SN/A const int ZeroReg = 0; // architecturally meaningful 1102458SN/A // the rest of these depend on the ABI 1112458SN/A const int StackPointerReg = 14; 1122458SN/A const int ReturnAddressReg = 31; // post call, precall is 15 1132458SN/A const int ReturnValueReg = 8; // Post return, 24 is pre-return. 1142458SN/A const int FramePointerReg = 30; 1152458SN/A const int ArgumentReg0 = 8; 1162458SN/A const int ArgumentReg1 = 9; 1172458SN/A const int ArgumentReg2 = 10; 1182458SN/A const int ArgumentReg3 = 11; 1192458SN/A const int ArgumentReg4 = 12; 1202458SN/A const int ArgumentReg5 = 13; 1212510SN/A // Some OS syscall use a second register (o1) to return a second value 1222458SN/A const int SyscallPseudoReturnReg = ArgumentReg1; 1232458SN/A 1242458SN/A //XXX These numbers are bogus 1252525SN/A const int MaxInstSrcRegs = 8; 1262561SN/A const int MaxInstDestRegs = 9; 1272458SN/A 1282458SN/A typedef uint64_t IntReg; 1292458SN/A 1302458SN/A // control register file contents 1312458SN/A typedef uint64_t MiscReg; 1322458SN/A 1332458SN/A typedef double FloatReg; 1342458SN/A typedef uint64_t FloatRegBits; 1352458SN/A 1362458SN/A //8K. This value is implmentation specific; and should probably 1372458SN/A //be somewhere else. 1382458SN/A const int LogVMPageSize = 13; 1392458SN/A const int VMPageSize = (1 << LogVMPageSize); 1402458SN/A 1412458SN/A //Why does both the previous set of constants and this one exist? 1422458SN/A const int PageShift = 13; 1432458SN/A const int PageBytes = ULL(1) << PageShift; 1442458SN/A 1452458SN/A const int BranchPredAddrShiftAmt = 2; 1462458SN/A 1472474SN/A const int MachineBytes = 8; 1482458SN/A const int WordBytes = 4; 1492458SN/A const int HalfwordBytes = 2; 1502458SN/A const int ByteBytes = 1; 1512458SN/A 1522458SN/A void serialize(std::ostream & os); 1532458SN/A 1542458SN/A void unserialize(Checkpoint *cp, const std::string §ion); 1552458SN/A 1562469SN/A StaticInstPtr decodeInst(ExtMachInst); 1572458SN/A 1582458SN/A // return a no-op instruction... used for instruction fetch faults 1592458SN/A extern const MachInst NoopMachInst; 1602458SN/A} 1612458SN/A 1622458SN/A#include "arch/sparc/regfile.hh" 1632458SN/A 1642458SN/Anamespace SparcISA 1652458SN/A{ 1662458SN/A 1672458SN/A#if !FULL_SYSTEM 1682458SN/A static inline void setSyscallReturn(SyscallReturn return_value, 1692458SN/A RegFile *regs) 1702458SN/A { 1712458SN/A // check for error condition. SPARC syscall convention is to 1722458SN/A // indicate success/failure in reg the carry bit of the ccr 1732458SN/A // and put the return value itself in the standard return value reg (). 1742458SN/A if (return_value.successful()) { 1752646Ssaidi@eecs.umich.edu // no error, clear XCC.C 1762646Ssaidi@eecs.umich.edu regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) & 0xEF); 1772525SN/A regs->setIntReg(ReturnValueReg, return_value.value()); 1782458SN/A } else { 1792646Ssaidi@eecs.umich.edu // got an error, set XCC.C 1802646Ssaidi@eecs.umich.edu regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) | 0x10); 1812525SN/A regs->setIntReg(ReturnValueReg, return_value.value()); 1822458SN/A } 1832458SN/A } 1842023SN/A#endif 1852458SN/A}; 1862023SN/A 1872023SN/A#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 188