isa_traits.hh revision 2525
1955SN/A/* 2955SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 31762SN/A * All rights reserved. 4955SN/A * 5955SN/A * Redistribution and use in source and binary forms, with or without 6955SN/A * modification, are permitted provided that the following conditions are 7955SN/A * met: redistributions of source code must retain the above copyright 8955SN/A * notice, this list of conditions and the following disclaimer; 9955SN/A * redistributions in binary form must reproduce the above copyright 10955SN/A * notice, this list of conditions and the following disclaimer in the 11955SN/A * documentation and/or other materials provided with the distribution; 12955SN/A * neither the name of the copyright holders nor the names of its 13955SN/A * contributors may be used to endorse or promote products derived from 14955SN/A * this software without specific prior written permission. 15955SN/A * 16955SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17955SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23955SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24955SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25955SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26955SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27955SN/A */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 30955SN/A#define __ARCH_SPARC_ISA_TRAITS_HH__ 31955SN/A 32955SN/A#include "base/misc.hh" 333583Sbinkertn@umich.edu#include "config/full_system.hh" 34955SN/A#include "sim/host.hh" 35955SN/A 36955SN/Aclass ExecContext; 37955SN/Aclass FastCPU; 38955SN/A//class FullCPU; 39955SN/Aclass Checkpoint; 40955SN/A 41955SN/Aclass StaticInst; 42955SN/Aclass StaticInstPtr; 43955SN/A 44955SN/Anamespace BigEndianGuest {} 45955SN/A 46955SN/A#if !FULL_SYSTEM 47955SN/Aclass SyscallReturn 482023SN/A{ 49955SN/A public: 503089Ssaidi@eecs.umich.edu template <class T> 51955SN/A SyscallReturn(T v, bool s) 52955SN/A { 53955SN/A retval = (uint64_t)v; 54955SN/A success = s; 55955SN/A } 56955SN/A 57955SN/A template <class T> 58955SN/A SyscallReturn(T v) 591031SN/A { 60955SN/A success = (v >= 0); 611388SN/A retval = (uint64_t)v; 62955SN/A } 63955SN/A 641296SN/A ~SyscallReturn() {} 65955SN/A 66955SN/A SyscallReturn& operator=(const SyscallReturn& s) 67955SN/A { 68955SN/A retval = s.retval; 69955SN/A success = s.success; 70955SN/A return *this; 71955SN/A } 72955SN/A 73955SN/A bool successful() { return success; } 74955SN/A uint64_t value() { return retval; } 75955SN/A 76955SN/A private: 773584Ssaidi@eecs.umich.edu uint64_t retval; 78955SN/A bool success; 79955SN/A}; 80955SN/A 81955SN/A#endif 82955SN/A 83955SN/A 84955SN/Anamespace SparcISA 852325SN/A{ 861717SN/A 872652Ssaidi@eecs.umich.edu // These enumerate all the registers for dependence tracking. 88955SN/A enum DependenceTags { 892736Sktlim@umich.edu // 0..31 are the integer regs 0..31 902410SN/A // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 91955SN/A FP_Base_DepTag = 32, 922290SN/A Ctrl_Base_DepTag = 96, 93955SN/A //XXX These are here solely to get compilation and won't work 942683Sktlim@umich.edu Fpcr_DepTag = 0, 952683Sktlim@umich.edu Uniq_DepTag = 0 962669Sktlim@umich.edu }; 972568SN/A 982568SN/A //This makes sure the big endian versions of certain functions are used. 993012Ssaidi@eecs.umich.edu using namespace BigEndianGuest; 1002462SN/A 1012568SN/A typedef uint32_t MachInst; 1022395SN/A typedef uint64_t ExtMachInst; 1032405SN/A 1042914Ssaidi@eecs.umich.edu const int NumIntRegs = 32; 105955SN/A const int NumFloatRegs = 64; 1062811Srdreslin@umich.edu const int NumMiscRegs = 32; 1072811Srdreslin@umich.edu 1082811Srdreslin@umich.edu // semantically meaningful register indices 1092811Srdreslin@umich.edu const int ZeroReg = 0; // architecturally meaningful 1102811Srdreslin@umich.edu // the rest of these depend on the ABI 1113719Sstever@eecs.umich.edu const int StackPointerReg = 14; 1122811Srdreslin@umich.edu const int ReturnAddressReg = 31; // post call, precall is 15 1132811Srdreslin@umich.edu const int ReturnValueReg = 8; // Post return, 24 is pre-return. 1142811Srdreslin@umich.edu const int FramePointerReg = 30; 1152811Srdreslin@umich.edu const int ArgumentReg0 = 8; 1162811Srdreslin@umich.edu const int ArgumentReg1 = 9; 1172811Srdreslin@umich.edu const int ArgumentReg2 = 10; 1182811Srdreslin@umich.edu const int ArgumentReg3 = 11; 1192811Srdreslin@umich.edu const int ArgumentReg4 = 12; 1202811Srdreslin@umich.edu const int ArgumentReg5 = 13; 1212814Srdreslin@umich.edu const int SyscallNumReg = 1; 1222811Srdreslin@umich.edu // Some OS syscall use a second register (o1) to return a second value 1232811Srdreslin@umich.edu const int SyscallPseudoReturnReg = ArgumentReg1; 1242811Srdreslin@umich.edu 1252811Srdreslin@umich.edu //XXX These numbers are bogus 1262811Srdreslin@umich.edu const int MaxInstSrcRegs = 8; 1272811Srdreslin@umich.edu const int MaxInstDestRegs = 3; 1282811Srdreslin@umich.edu 1292813Srdreslin@umich.edu typedef uint64_t IntReg; 1302813Srdreslin@umich.edu 1313868Sbinkertn@umich.edu // control register file contents 1323645Sbinkertn@umich.edu typedef uint64_t MiscReg; 1333624Sbinkertn@umich.edu 1343871Sbinkertn@umich.edu typedef double FloatReg; 1353871Sbinkertn@umich.edu typedef uint64_t FloatRegBits; 1363624Sbinkertn@umich.edu 137955SN/A //8K. This value is implmentation specific; and should probably 138955SN/A //be somewhere else. 139955SN/A const int LogVMPageSize = 13; 1402090SN/A const int VMPageSize = (1 << LogVMPageSize); 141955SN/A 142955SN/A //Why does both the previous set of constants and this one exist? 1431696SN/A const int PageShift = 13; 144955SN/A const int PageBytes = ULL(1) << PageShift; 145955SN/A 146955SN/A const int BranchPredAddrShiftAmt = 2; 1471127SN/A 148955SN/A const int MachineBytes = 8; 149955SN/A const int WordBytes = 4; 1502379SN/A const int HalfwordBytes = 2; 151955SN/A const int ByteBytes = 1; 152955SN/A 153955SN/A void serialize(std::ostream & os); 1542422SN/A 1552422SN/A void unserialize(Checkpoint *cp, const std::string §ion); 1562422SN/A 1572422SN/A StaticInstPtr decodeInst(ExtMachInst); 1582422SN/A 1592422SN/A // return a no-op instruction... used for instruction fetch faults 1602422SN/A extern const MachInst NoopMachInst; 1612397SN/A} 1622397SN/A 1632422SN/A#include "arch/sparc/regfile.hh" 1642422SN/A 165955SN/Anamespace SparcISA 166955SN/A{ 167955SN/A 168955SN/A#if !FULL_SYSTEM 169955SN/A static inline void setSyscallReturn(SyscallReturn return_value, 170955SN/A RegFile *regs) 171955SN/A { 172955SN/A // check for error condition. SPARC syscall convention is to 1731078SN/A // indicate success/failure in reg the carry bit of the ccr 174955SN/A // and put the return value itself in the standard return value reg (). 175955SN/A if (return_value.successful()) { 176955SN/A // no error 177955SN/A regs->setMiscReg(MISCREG_CCR_ICC_C, 0); 1781917SN/A regs->setIntReg(ReturnValueReg, return_value.value()); 179955SN/A } else { 180955SN/A // got an error, return details 1811730SN/A regs->setMiscReg(MISCREG_CCR_ICC_C, 1); 182955SN/A regs->setIntReg(ReturnValueReg, return_value.value()); 1832521SN/A } 1842521SN/A } 1852507SN/A#endif 1862507SN/A}; 1872989Ssaidi@eecs.umich.edu 1883408Ssaidi@eecs.umich.edu#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 1892507SN/A