isa_traits.hh revision 2458
15148SN/A/* 25148SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 35148SN/A * All rights reserved. 410036SAli.Saidi@ARM.com * 58835SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 610036SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77873SN/A * met: redistributions of source code must retain the above copyright 87873SN/A * notice, this list of conditions and the following disclaimer; 97873SN/A * redistributions in binary form must reproduce the above copyright 105148SN/A * notice, this list of conditions and the following disclaimer in the 115148SN/A * documentation and/or other materials provided with the distribution; 125148SN/A * neither the name of the copyright holders nor the names of its 1310315Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 148835SAli.Saidi@ARM.com * this software without specific prior written permission. 159885Sstever@gmail.com * 169885Sstever@gmail.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711570SCurtis.Dunham@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810036SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911312Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208835SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218835SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210315Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311960Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248835SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510315Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265148SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279481Snilay@cs.wisc.edu */ 288673SN/A 2910736Snilay@cs.wisc.edu#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 3011219Snilay@cs.wisc.edu#define __ARCH_SPARC_ISA_TRAITS_HH__ 318721SN/A 3211570SCurtis.Dunham@arm.com#include "base/misc.hh" 3311570SCurtis.Dunham@arm.com#include "config/full_system.hh" 3411570SCurtis.Dunham@arm.com#include "sim/host.hh" 3511570SCurtis.Dunham@arm.com 368835SAli.Saidi@ARM.comclass ExecContext; 378835SAli.Saidi@ARM.comclass FastCPU; 3811440SCurtis.Dunham@arm.com//class FullCPU; 3911440SCurtis.Dunham@arm.comclass Checkpoint; 407935SN/A 417935SN/Aclass StaticInst; 427935SN/Aclass StaticInstPtr; 437935SN/A 447935SN/Anamespace BigEndianGuest {} 457935SN/A 467935SN/A#if !FULL_SYSTEM 478983Snate@binkert.orgclass SyscallReturn 485148SN/A{ 499885Sstever@gmail.com public: 509885Sstever@gmail.com template <class T> 519885Sstever@gmail.com SyscallReturn(T v, bool s) 5210315Snilay@cs.wisc.edu { 5310036SAli.Saidi@ARM.com retval = (uint64_t)v; 5410315Snilay@cs.wisc.edu success = s; 559885Sstever@gmail.com } 569885Sstever@gmail.com 575148SN/A template <class T> 585148SN/A SyscallReturn(T v) 599885Sstever@gmail.com { 6010315Snilay@cs.wisc.edu success = (v >= 0); 615876SN/A retval = (uint64_t)v; 629885Sstever@gmail.com } 635148SN/A 6411570SCurtis.Dunham@arm.com ~SyscallReturn() {} 655876SN/A 668835SAli.Saidi@ARM.com SyscallReturn& operator=(const SyscallReturn& s) 675876SN/A { 685148SN/A retval = s.retval; 6910036SAli.Saidi@ARM.com success = s.success; 708983Snate@binkert.org return *this; 715148SN/A } 725148SN/A 738835SAli.Saidi@ARM.com bool successful() { return success; } 749481Snilay@cs.wisc.edu uint64_t value() { return retval; } 755148SN/A 765148SN/A private: 775148SN/A uint64_t retval; 785148SN/A bool success; 795148SN/A}; 805540SN/A 8111570SCurtis.Dunham@arm.com#endif 8211570SCurtis.Dunham@arm.com 8311570SCurtis.Dunham@arm.com 8411570SCurtis.Dunham@arm.comnamespace SparcISA 858835SAli.Saidi@ARM.com{ 865148SN/A //This makes sure the big endian versions of certain functions are used. 879885Sstever@gmail.com using namespace BigEndianGuest; 885509SN/A 895509SN/A typedef uint32_t MachInst; 9010315Snilay@cs.wisc.edu typedef uint64_t ExtMachInst; 919481Snilay@cs.wisc.edu 9211960Sgabeblack@google.com const int NumIntRegs = 32; 935148SN/A const int NumFloatRegs = 64; 945148SN/A const int NumMiscRegs = 32; 955148SN/A 965148SN/A // semantically meaningful register indices 978983Snate@binkert.org const int ZeroReg = 0; // architecturally meaningful 988983Snate@binkert.org // the rest of these depend on the ABI 995148SN/A const int StackPointerReg = 14; 1009885Sstever@gmail.com const int ReturnAddressReg = 31; // post call, precall is 15 1019885Sstever@gmail.com const int ReturnValueReg = 8; // Post return, 24 is pre-return. 1029885Sstever@gmail.com const int FramePointerReg = 30; 1039885Sstever@gmail.com const int ArgumentReg0 = 8; 10410036SAli.Saidi@ARM.com const int ArgumentReg1 = 9; 1059885Sstever@gmail.com const int ArgumentReg2 = 10; 1065148SN/A const int ArgumentReg3 = 11; 1076024SN/A const int ArgumentReg4 = 12; 1088835SAli.Saidi@ARM.com const int ArgumentReg5 = 13; 10910036SAli.Saidi@ARM.com // Some OS syscall sue a second register (o1) to return a second value 1105148SN/A const int SyscallPseudoReturnReg = ArgumentReg1; 1118835SAli.Saidi@ARM.com 1128835SAli.Saidi@ARM.com //XXX These numbers are bogus 1138835SAli.Saidi@ARM.com const int MaxInstSrcRegs = 3; 1148835SAli.Saidi@ARM.com const int MaxInstDestRegs = 2; 1159885Sstever@gmail.com 11611570SCurtis.Dunham@arm.com typedef uint64_t IntReg; 11710036SAli.Saidi@ARM.com 1189885Sstever@gmail.com // control register file contents 11911570SCurtis.Dunham@arm.com typedef uint64_t MiscReg; 12011570SCurtis.Dunham@arm.com 12111570SCurtis.Dunham@arm.com typedef double FloatReg; 12211570SCurtis.Dunham@arm.com typedef uint64_t FloatRegBits; 1238835SAli.Saidi@ARM.com 1248983Snate@binkert.org //8K. This value is implmentation specific; and should probably 1258835SAli.Saidi@ARM.com //be somewhere else. 1268835SAli.Saidi@ARM.com const int LogVMPageSize = 13; 1278835SAli.Saidi@ARM.com const int VMPageSize = (1 << LogVMPageSize); 1289885Sstever@gmail.com 12911570SCurtis.Dunham@arm.com //Why does both the previous set of constants and this one exist? 13010036SAli.Saidi@ARM.com const int PageShift = 13; 1318835SAli.Saidi@ARM.com const int PageBytes = ULL(1) << PageShift; 13211570SCurtis.Dunham@arm.com 13311570SCurtis.Dunham@arm.com const int BranchPredAddrShiftAmt = 2; 13411570SCurtis.Dunham@arm.com 1358835SAli.Saidi@ARM.com const int WordBytes = 4; 1369213Snilay@cs.wisc.edu const int HalfwordBytes = 2; 13711570SCurtis.Dunham@arm.com const int ByteBytes = 1; 1388835SAli.Saidi@ARM.com 1398983Snate@binkert.org void serialize(std::ostream & os); 1408983Snate@binkert.org 1418983Snate@binkert.org void unserialize(Checkpoint *cp, const std::string §ion); 1425148SN/A 1439481Snilay@cs.wisc.edu StaticInstPtr decodeInst(MachInst); 1449481Snilay@cs.wisc.edu 14510036SAli.Saidi@ARM.com // return a no-op instruction... used for instruction fetch faults 1469481Snilay@cs.wisc.edu extern const MachInst NoopMachInst; 1475148SN/A 1486024SN/A // Instruction address compression hooks 1498835SAli.Saidi@ARM.com inline Addr realPCToFetchPC(const Addr &addr) 15010036SAli.Saidi@ARM.com { 1515148SN/A return addr; 1528835SAli.Saidi@ARM.com } 1538835SAli.Saidi@ARM.com 1548835SAli.Saidi@ARM.com inline Addr fetchPCToRealPC(const Addr &addr) 1558835SAli.Saidi@ARM.com { 1569885Sstever@gmail.com return addr; 15711570SCurtis.Dunham@arm.com } 15810036SAli.Saidi@ARM.com 1599885Sstever@gmail.com // the size of "fetched" instructions (not necessarily the size 16011570SCurtis.Dunham@arm.com // of real instructions for PISA) 16111570SCurtis.Dunham@arm.com inline size_t fetchInstSize() 16211570SCurtis.Dunham@arm.com { 16311570SCurtis.Dunham@arm.com return sizeof(MachInst); 1648835SAli.Saidi@ARM.com } 1658983Snate@binkert.org 1665148SN/A /** 1675148SN/A * Function to insure ISA semantics about 0 registers. 1685148SN/A * @param xc The execution context. 16910036SAli.Saidi@ARM.com */ 1705148SN/A template <class XC> 1715148SN/A void zeroRegisters(XC *xc); 17211960Sgabeblack@google.com} 1735148SN/A 1745148SN/A#include "arch/sparc/regfile.hh" 17510645Snilay@cs.wisc.edu 1765148SN/Anamespace SparcISA 1775148SN/A{ 1785516SN/A 1795148SN/A#if !FULL_SYSTEM 18010036SAli.Saidi@ARM.com static inline void setSyscallReturn(SyscallReturn return_value, 18111960Sgabeblack@google.com RegFile *regs) 1825148SN/A { 1835148SN/A // check for error condition. SPARC syscall convention is to 18410645Snilay@cs.wisc.edu // indicate success/failure in reg the carry bit of the ccr 18511960Sgabeblack@google.com // and put the return value itself in the standard return value reg (). 1865148SN/A if (return_value.successful()) { 18711960Sgabeblack@google.com // no error 1885148SN/A regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 0); 18911960Sgabeblack@google.com regs->intRegFile[ReturnValueReg] = return_value.value(); 1905410SN/A } else { 1915148SN/A // got an error, return details 1925148SN/A regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 1); 19310451Snilay@cs.wisc.edu regs->intRegFile[ReturnValueReg] = -return_value.value(); 1945148SN/A } 1959885Sstever@gmail.com } 1969885Sstever@gmail.com#endif 1979885Sstever@gmail.com}; 19810315Snilay@cs.wisc.edu 19910036SAli.Saidi@ARM.com#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 20010315Snilay@cs.wisc.edu