isa_traits.hh revision 2023
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 30#define __ARCH_SPARC_ISA_TRAITS_HH__ 31 32#include "arch/sparc/faults.hh" 33#include "base/misc.hh" 34#include "sim/host.hh" 35 36class FastCPU; 37//class FullCPU; 38//class Checkpoint; 39 40#define TARGET_SPARC 41 42template <class ISA> class StaticInst; 43template <class ISA> class StaticInstPtr; 44 45//namespace EV5 46//{ 47// int DTB_ASN_ASN(uint64_t reg); 48// int ITB_ASN_ASN(uint64_t reg); 49//} 50 51class SPARCISA 52{ 53 public: 54 55 typedef uint32_t MachInst; 56 typedef uint64_t Addr; 57 typedef uint8_t RegIndex; 58 59 enum 60 { 61 MemoryEnd = 0xffffffffffffffffULL, 62 63 NumFloatRegs = 32, 64 NumMiscRegs = 32, 65 66 MaxRegsOfAnyType = 32, 67 // Static instruction parameters 68 MaxInstSrcRegs = 3, 69 MaxInstDestRegs = 2, 70 71 // Maximum trap level 72 MaxTL = 4 73 74 // semantically meaningful register indices 75 ZeroReg = 0, // architecturally meaningful 76 // the rest of these depend on the ABI 77 } 78 typedef uint64_t IntReg; 79 80 class IntRegFile 81 { 82 private: 83 //For right now, let's pretend the register file is static 84 IntReg regs[32]; 85 public: 86 IntReg & operator [] (RegIndex index) 87 { 88 //Don't allow indexes outside of the 32 registers 89 index &= 0x1F 90 return regs[index]; 91 } 92 }; 93 94 void inline serialize(std::ostream & os) 95 { 96 SERIALIZE_ARRAY(regs, 32); 97 } 98 99 void inline unserialize(Checkpoint &*cp, const std::string §ion) 100 { 101 UNSERIALIZE_ARRAY(regs, 32); 102 } 103 104 class FloatRegFile 105 { 106 private: 107 //By using the largest data type, we ensure everything 108 //is aligned correctly in memory 109 union 110 { 111 double double rawRegs[16]; 112 uint64_t regDump[32]; 113 }; 114 class QuadRegs 115 { 116 private: 117 FloatRegFile * parent; 118 public: 119 QuadRegs(FloatRegFile * p) : parent(p) {;} 120 double double & operator [] (RegIndex index) 121 { 122 //Quad floats are index by the single 123 //precision register the start on, 124 //and only 16 should be accessed 125 index = (index >> 2) & 0xF; 126 return parent->rawRegs[index]; 127 } 128 }; 129 class DoubleRegs 130 { 131 private: 132 FloatRegFile * parent; 133 public: 134 DoubleRegs(FloatRegFile * p) : parent(p) {;} 135 double & operator [] (RegIndex index) 136 { 137 //Double floats are index by the single 138 //precision register the start on, 139 //and only 32 should be accessed 140 index = (index >> 1) & 0x1F 141 return ((double [])parent->rawRegs)[index]; 142 } 143 } 144 class SingleRegs 145 { 146 private: 147 FloatRegFile * parent; 148 public: 149 SingleRegs(FloatRegFile * p) : parent(p) {;} 150 double & operator [] (RegFile index) 151 { 152 //Only 32 single floats should be accessed 153 index &= 0x1F 154 return ((float [])parent->rawRegs)[index]; 155 } 156 } 157 public: 158 void inline serialize(std::ostream & os) 159 { 160 SERIALIZE_ARRAY(regDump, 32); 161 } 162 163 void inline unserialize(Checkpoint &* cp, std::string & section) 164 { 165 UNSERIALIZE_ARRAY(regDump, 32); 166 } 167 168 QuadRegs quadRegs; 169 DoubleRegs doubleRegs; 170 SingleRegs singleRegs; 171 FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this) 172 {;} 173 }; 174 175 // control register file contents 176 typedef uint64_t MiscReg; 177 // The control registers, broken out into fields 178 class MiscRegFile 179 { 180 public: 181 union 182 { 183 uint16_t pstate; // Process State Register 184 struct 185 { 186 uint16_t ag:1; // Alternate Globals 187 uint16_t ie:1; // Interrupt enable 188 uint16_t priv:1; // Privelege mode 189 uint16_t am:1; // Address mask 190 uint16_t pef:1; // PSTATE enable floating-point 191 uint16_t red:1; // RED (reset, error, debug) state 192 uint16_t mm:2; // Memory Model 193 uint16_t tle:1; // Trap little-endian 194 uint16_t cle:1; // Current little-endian 195 } pstateFields; 196 } 197 uint64_t tba; // Trap Base Address 198 union 199 { 200 uint64_t y; // Y (used in obsolete multiplication) 201 struct 202 { 203 uint64_t value:32; // The actual value stored in y 204 const uint64_t :32; // reserved bits 205 } yFields; 206 } 207 uint8_t pil; // Process Interrupt Register 208 uint8_t cwp; // Current Window Pointer 209 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured on the previous level) 210 union 211 { 212 uint8_t ccr; // Condition Code Register 213 struct 214 { 215 union 216 { 217 uint8_t icc:4; // 32-bit condition codes 218 struct 219 { 220 uint8_t c:1; // Carry 221 uint8_t v:1; // Overflow 222 uint8_t z:1; // Zero 223 uint8_t n:1; // Negative 224 } iccFields:4; 225 } :4; 226 union 227 { 228 uint8_t xcc:4; // 64-bit condition codes 229 struct 230 { 231 uint8_t c:1; // Carry 232 uint8_t v:1; // Overflow 233 uint8_t z:1; // Zero 234 uint8_t n:1; // Negative 235 } xccFields:4; 236 } :4; 237 } ccrFields; 238 } 239 uint8_t asi; // Address Space Identifier 240 uint8_t tl; // Trap Level 241 uint64_t tpc[MaxTL]; // Trap Program Counter (value from previous trap level) 242 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from previous trap level) 243 union 244 { 245 uint64_t tstate[MaxTL]; // Trap State 246 struct 247 { 248 //Values are from previous trap level 249 uint64_t cwp:5; // Current Window Pointer 250 const uint64_t :2; // Reserved bits 251 uint64_t pstate:10; // Process State 252 const uint64_t :6; // Reserved bits 253 uint64_t asi:8; // Address Space Identifier 254 uint64_t ccr:8; // Condition Code Register 255 } tstateFields[MaxTL]; 256 } 257 union 258 { 259 uint64_t tick; // Hardware clock-tick counter 260 struct 261 { 262 uint64_t counter:63; // Clock-tick count 263 uint64_t npt:1; // Non-priveleged trap 264 } tickFields; 265 } 266 uint8_t cansave; // Savable windows 267 uint8_t canrestore; // Restorable windows 268 uint8_t otherwin; // Other windows 269 uint8_t cleanwin; // Clean windows 270 union 271 { 272 uint8_t wstate; // Window State 273 struct 274 { 275 uint8_t normal:3; // Bits TT<4:2> are set to on a normal 276 // register window trap 277 uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin" 278 // register window trap 279 } wstateFields; 280 } 281 union 282 { 283 uint64_t ver; // Version 284 struct 285 { 286 uint64_t maxwin:5; // Max CWP value 287 const uint64_t :2; // Reserved bits 288 uint64_t maxtl:8; // Maximum trap level 289 const uint64_t :8; // Reserved bits 290 uint64_t mask:8; // Processor mask set revision number 291 uint64_t impl:16; // Implementation identification number 292 uint64_t manuf:16; // Manufacturer code 293 } verFields; 294 } 295 union 296 { 297 uint64_t fsr; // Floating-Point State Register 298 struct 299 { 300 union 301 { 302 uint64_t cexc:5; // Current excpetion 303 struct 304 { 305 uint64_t nxc:1; // Inexact 306 uint64_t dzc:1; // Divide by zero 307 uint64_t ufc:1; // Underflow 308 uint64_t ofc:1; // Overflow 309 uint64_t nvc:1; // Invalid operand 310 } cexecFields:5; 311 } :5; 312 union 313 { 314 uint64_t aexc:5; // Accrued exception 315 struct 316 { 317 uint64_t nxc:1; // Inexact 318 uint64_t dzc:1; // Divide by zero 319 uint64_t ufc:1; // Underflow 320 uint64_t ofc:1; // Overflow 321 uint64_t nvc:1; // Invalid operand 322 } aexecFields:5; 323 } :5; 324 uint64_t fcc0:2; // Floating-Point condtion codes 325 const uint64_t :1; // Reserved bits 326 uint64_t qne:1; // Deferred trap queue not empty 327 // with no queue, it should read 0 328 uint64_t ftt:3; // Floating-Point trap type 329 uint64_t ver:3; // Version (of the FPU) 330 const uint64_t :2; // Reserved bits 331 uint64_t ns:1; // Nonstandard floating point 332 union 333 { 334 uint64_t tem:5; // Trap Enable Mask 335 struct 336 { 337 uint64_t nxm:1; // Inexact 338 uint64_t dzm:1; // Divide by zero 339 uint64_t ufm:1; // Underflow 340 uint64_t ofm:1; // Overflow 341 uint64_t nvm:1; // Invalid operand 342 } temFields:5; 343 } :5; 344 const uint64_t :2; // Reserved bits 345 uint64_t rd:2; // Rounding direction 346 uint64_t fcc1:2; // Floating-Point condition codes 347 uint64_t fcc2:2; // Floating-Point condition codes 348 uint64_t fcc3:2; // Floating-Point condition codes 349 const uint64_t :26; // Reserved bits 350 } fsrFields; 351 } 352 union 353 { 354 uint8_t fprs; // Floating-Point Register State 355 struct 356 { 357 dl:1; // Dirty lower 358 du:1; // Dirty upper 359 fef:1; // FPRS enable floating-Point 360 } fprsFields; 361 }; 362 363 void serialize(std::ostream & os) 364 { 365 SERIALIZE_SCALAR(pstate); 366 SERIAlIZE_SCALAR(tba); 367 SERIALIZE_SCALAR(y); 368 SERIALIZE_SCALAR(pil); 369 SERIALIZE_SCALAR(cwp); 370 SERIALIZE_ARRAY(tt, MaxTL); 371 SERIALIZE_SCALAR(ccr); 372 SERIALIZE_SCALAR(asi); 373 SERIALIZE_SCALAR(tl); 374 SERIALIZE_SCALAR(tpc); 375 SERIALIZE_SCALAR(tnpc); 376 SERIALIZE_ARRAY(tstate, MaxTL); 377 SERIALIZE_SCALAR(tick); 378 SERIALIZE_SCALAR(cansave); 379 SERIALIZE_SCALAR(canrestore); 380 SERIALIZE_SCALAR(otherwin); 381 SERIALIZE_SCALAR(cleanwin); 382 SERIALIZE_SCALAR(wstate); 383 SERIALIZE_SCALAR(ver); 384 SERIALIZE_SCALAR(fsr); 385 SERIALIZE_SCALAR(fprs); 386 } 387 388 void unserialize(Checkpoint &* cp, std::string & section) 389 { 390 UNSERIALIZE_SCALAR(pstate); 391 UNSERIAlIZE_SCALAR(tba); 392 UNSERIALIZE_SCALAR(y); 393 UNSERIALIZE_SCALAR(pil); 394 UNSERIALIZE_SCALAR(cwp); 395 UNSERIALIZE_ARRAY(tt, MaxTL); 396 UNSERIALIZE_SCALAR(ccr); 397 UNSERIALIZE_SCALAR(asi); 398 UNSERIALIZE_SCALAR(tl); 399 UNSERIALIZE_SCALAR(tpc); 400 UNSERIALIZE_SCALAR(tnpc); 401 UNSERIALIZE_ARRAY(tstate, MaxTL); 402 UNSERIALIZE_SCALAR(tick); 403 UNSERIALIZE_SCALAR(cansave); 404 UNSERIALIZE_SCALAR(canrestore); 405 UNSERIALIZE_SCALAR(otherwin); 406 UNSERIALIZE_SCALAR(cleanwin); 407 UNSERIALIZE_SCALAR(wstate); 408 UNSERIALIZE_SCALAR(ver); 409 UNSERIALIZE_SCALAR(fsr); 410 UNSERIALIZE_SCALAR(fprs); 411 } 412 }; 413 414 typedef union 415 { 416 IntReg intreg; 417 FloatReg fpreg; 418 MiscReg ctrlreg; 419 } AnyReg; 420 421 struct RegFile 422 { 423 IntRegFile intRegFile; // (signed) integer register file 424 FloatRegFile floatRegFile; // floating point register file 425 MiscRegFile miscRegFile; // control register file 426 427 Addr pc; // Program Counter 428 Addr npc; // Next Program Counter 429 430 void serialize(std::ostream &os); 431 void unserialize(Checkpoint *cp, const std::string §ion); 432 }; 433 434 static StaticInstPtr<AlphaISA> decodeInst(MachInst); 435 436 // return a no-op instruction... used for instruction fetch faults 437 static const MachInst NoopMachInst; 438 439 // Instruction address compression hooks 440 static inline Addr realPCToFetchPC(const Addr &addr) 441 { 442 return addr; 443 } 444 445 static inline Addr fetchPCToRealPC(const Addr &addr) 446 { 447 return addr; 448 } 449 450 // the size of "fetched" instructions (not necessarily the size 451 // of real instructions for PISA) 452 static inline size_t fetchInstSize() 453 { 454 return sizeof(MachInst); 455 } 456 457 /** 458 * Function to insure ISA semantics about 0 registers. 459 * @param xc The execution context. 460 */ 461 template <class XC> 462 static void zeroRegisters(XC *xc); 463}; 464 465 466typedef SPARCISA TheISA; 467 468typedef TheISA::MachInst MachInst; 469typedef TheISA::Addr Addr; 470typedef TheISA::RegIndex RegIndex; 471typedef TheISA::IntReg IntReg; 472typedef TheISA::IntRegFile IntRegFile; 473typedef TheISA::FloatReg FloatReg; 474typedef TheISA::FloatRegFile FloatRegFile; 475typedef TheISA::MiscReg MiscReg; 476typedef TheISA::MiscRegFile MiscRegFile; 477typedef TheISA::AnyReg AnyReg; 478typedef TheISA::RegFile RegFile; 479 480const int VMPageSize = TheISA::VMPageSize; 481const int LogVMPageSize = TheISA::LogVMPageSize; 482const int ZeroReg = TheISA::ZeroReg; 483const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; 484const int MaxAddr = (Addr)-1; 485 486#ifndef FULL_SYSTEM 487class SyscallReturn { 488 public: 489 template <class T> 490 SyscallReturn(T v, bool s) 491 { 492 retval = (uint64_t)v; 493 success = s; 494 } 495 496 template <class T> 497 SyscallReturn(T v) 498 { 499 success = (v >= 0); 500 retval = (uint64_t)v; 501 } 502 503 ~SyscallReturn() {} 504 505 SyscallReturn& operator=(const SyscallReturn& s) { 506 retval = s.retval; 507 success = s.success; 508 return *this; 509 } 510 511 bool successful() { return success; } 512 uint64_t value() { return retval; } 513 514 515 private: 516 uint64_t retval; 517 bool success; 518}; 519 520#endif 521 522 523#ifdef FULL_SYSTEM 524 525#include "arch/alpha/ev5.hh" 526#endif 527 528#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 529