operands.isa revision 3952:092d03b2ab95 
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
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13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28//          Gabe Black
29//          Steve Reinhardt
30
31def operand_types {{
32    'sb' : ('signed int', 8),
33    'ub' : ('unsigned int', 8),
34    'shw' : ('signed int', 16),
35    'uhw' : ('unsigned int', 16),
36    'sw' : ('signed int', 32),
37    'uw' : ('unsigned int', 32),
38    'sdw' : ('signed int', 64),
39    'udw' : ('unsigned int', 64),
40    'sf' : ('float', 32),
41    'df' : ('float', 64),
42    'qf' : ('float', 128)
43}};
44
45output header {{
46    // A function to "decompress" double and quad floating point
47    // register numbers stuffed into 5 bit fields. These have their
48    // MSB put in the LSB position but are otherwise normal.
49    static inline unsigned int dfpr(unsigned int regNum)
50    {
51        return (regNum & (~1)) | ((regNum & 1) << 5);
52    }
53}};
54
55def operands {{
56    # Int regs default to unsigned, but code should not count on this.
57    # For clarity, descriptions that depend on unsigned behavior should
58    # explicitly specify '.uq'.
59
60    'Rd': 		('IntReg', 'udw', 'RD', 'IsInteger', 1),
61    # The Rd from the previous window
62    'Rd_prev':		('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
63    # The Rd from the next window
64    'Rd_next':		('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
65    # For microcoded twin load instructions, RdTwin appears in the "code"
66    # for the instruction is replaced by RdLow or RdHigh by the format
67    # before it's processed by the iop.
68    # The low (even) register of a two register pair
69    'RdLow': 		('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
70    # The high (odd) register of a two register pair
71    'RdHigh':		('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
72    'Rs1': 		('IntReg', 'udw', 'RS1', 'IsInteger', 6),
73    'Rs2': 		('IntReg', 'udw', 'RS2', 'IsInteger', 7),
74    # A microcode register. Right now, this is the only one.
75    'uReg0':		('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
76    # Because double and quad precision register numbers are decoded
77    # differently, they get different operands. The single precision versions
78    # have an s post pended to their name.
79    'Frds':		('FloatReg', 'sf', 'RD', 'IsFloating', 10),
80    'Frd':		('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
81    # Each Frd_N refers to the Nth double precision register from Frd.
82    # Note that this adds twice N to the register number.
83    'Frd_0':		('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
84    'Frd_1':		('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
85    'Frd_2':		('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
86    'Frd_3':		('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
87    'Frd_4':		('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
88    'Frd_5':		('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
89    'Frd_6':		('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
90    'Frd_7':		('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
91    'Frs1s':		('FloatReg', 'df', 'RS1', 'IsFloating', 11),
92    'Frs1':		('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
93    'Frs2s':		('FloatReg', 'df', 'RS2', 'IsFloating', 12),
94    'Frs2':		('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
95    'NPC': 		('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
96    'NNPC':		('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
97    # Registers which are used explicitly in instructions
98    'R0':  		('IntReg', 'udw', '0', None, 6),
99    'R1':  		('IntReg', 'udw', '1', None, 7),
100    'R15': 		('IntReg', 'udw', '15', 'IsInteger', 8),
101    'R16': 		('IntReg', 'udw', '16', None, 9),
102
103    # Control registers
104#   'Y':		('ControlReg', 'udw', 'MISCREG_Y', None, 40),
105#   'Ccr':		('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
106    'Y':		('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
107    'Ccr':		('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
108    'Asi':		('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
109    'Fprs':		('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
110    'Pcr':		('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
111    'Pic':		('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
112    'Gsr':		('ControlReg', 'udw', 'MISCREG_GSR', None, 46),
113    'Softint':		('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
114    'SoftintSet':	('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
115    'SoftintClr':	('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
116    'TickCmpr':		('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
117    'Stick':		('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
118    'StickCmpr':	('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
119
120    'Tpc':		('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
121    'Tnpc':		('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
122    'Tstate':		('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
123    'Tt':		('ControlReg', 'udw', 'MISCREG_TT', None, 56),
124    'Tick':		('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
125    'Tba':		('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
126    'Pstate':		('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
127    'Tl':		('ControlReg', 'udw', 'MISCREG_TL', None, 60),
128    'Pil':		('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
129    'Cwp':		('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
130#   'Cansave':		('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
131#   'Canrestore':	('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
132#   'Cleanwin':		('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
133#   'Otherwin':		('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
134#   'Wstate':		('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
135    'Cansave':		('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
136    'Canrestore':	('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
137    'Cleanwin':		('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),
138    'Otherwin':		('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),
139    'Wstate':		('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
140    'Gl':               ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
141
142    'Hpstate':		('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
143    'Htstate':		('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
144    'Hintp':		('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
145    'Htba':		('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
146    'HstickCmpr':	('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
147    'Hver':		('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
148    'StrandStsReg':	('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
149
150    'Fsr':		('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
151    # Mem gets a large number so it's always last
152    'Mem': 		('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
153
154}};
155