includes.isa revision 9022:bb25e7646c41
13101Sstever@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 23101Sstever@eecs.umich.edu// All rights reserved. 33101Sstever@eecs.umich.edu// 43101Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 53101Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 63101Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 73101Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 83101Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 93101Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 103101Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 113101Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 123101Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 133101Sstever@eecs.umich.edu// this software without specific prior written permission. 143101Sstever@eecs.umich.edu// 153101Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163101Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173101Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183101Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193101Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203101Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213101Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223101Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233101Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243101Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253101Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263101Sstever@eecs.umich.edu// 273101Sstever@eecs.umich.edu// Authors: Ali Saidi 283101Sstever@eecs.umich.edu// Gabe Black 293101Sstever@eecs.umich.edu// Steve Reinhardt 303101Sstever@eecs.umich.edu 313101Sstever@eecs.umich.edu//////////////////////////////////////////////////////////////////// 323101Sstever@eecs.umich.edu// 333101Sstever@eecs.umich.edu// Output include file directives. 343101Sstever@eecs.umich.edu// 353101Sstever@eecs.umich.edu 363101Sstever@eecs.umich.eduoutput header {{ 373101Sstever@eecs.umich.edu#include <cstring> 383101Sstever@eecs.umich.edu#include <iostream> 393101Sstever@eecs.umich.edu#include <sstream> 403101Sstever@eecs.umich.edu 413101Sstever@eecs.umich.edu#include "arch/sparc/faults.hh" 423101Sstever@eecs.umich.edu#include "arch/sparc/isa_traits.hh" 433101Sstever@eecs.umich.edu#include "arch/sparc/registers.hh" 443101Sstever@eecs.umich.edu#include "base/condcodes.hh" 453101Sstever@eecs.umich.edu#include "base/misc.hh" 463101Sstever@eecs.umich.edu#include "cpu/static_inst.hh" 473101Sstever@eecs.umich.edu#include "mem/packet.hh" 483101Sstever@eecs.umich.edu#include "mem/request.hh" // some constructors use MemReq flags 493101Sstever@eecs.umich.edu}}; 503101Sstever@eecs.umich.edu 513101Sstever@eecs.umich.eduoutput decoder {{ 523101Sstever@eecs.umich.edu#include <algorithm> 533101Sstever@eecs.umich.edu 543101Sstever@eecs.umich.edu#include "arch/sparc/decoder.hh" 553101Sstever@eecs.umich.edu#include "base/loader/symtab.hh" 563101Sstever@eecs.umich.edu#include "base/cprintf.hh" 573101Sstever@eecs.umich.edu#include "base/fenv.hh" 583101Sstever@eecs.umich.edu#include "cpu/thread_context.hh" // for Jump::branchTarget() 593101Sstever@eecs.umich.edu#include "mem/packet.hh" 603101Sstever@eecs.umich.edu 613101Sstever@eecs.umich.eduusing namespace SparcISA; 623101Sstever@eecs.umich.edu}}; 633101Sstever@eecs.umich.edu 643101Sstever@eecs.umich.eduoutput exec {{ 653101Sstever@eecs.umich.edu#include "base/fenv.hh" 663101Sstever@eecs.umich.edu 673101Sstever@eecs.umich.edu#include <cmath> 683101Sstever@eecs.umich.edu#include <limits> 693101Sstever@eecs.umich.edu 703101Sstever@eecs.umich.edu#include "arch/generic/memhelpers.hh" 713101Sstever@eecs.umich.edu#include "arch/sparc/asi.hh" 723101Sstever@eecs.umich.edu#include "base/bigint.hh" 733101Sstever@eecs.umich.edu#include "cpu/base.hh" 743101Sstever@eecs.umich.edu#include "cpu/exetrace.hh" 753101Sstever@eecs.umich.edu#include "debug/Sparc.hh" 763101Sstever@eecs.umich.edu#include "mem/packet.hh" 773101Sstever@eecs.umich.edu#include "mem/packet_access.hh" 783101Sstever@eecs.umich.edu#include "sim/full_system.hh" 793101Sstever@eecs.umich.edu#include "sim/pseudo_inst.hh" 803101Sstever@eecs.umich.edu#include "sim/sim_exit.hh" 813101Sstever@eecs.umich.edu 823101Sstever@eecs.umich.eduusing namespace SparcISA; 833101Sstever@eecs.umich.eduusing namespace std; 843101Sstever@eecs.umich.edu}}; 853101Sstever@eecs.umich.edu 863101Sstever@eecs.umich.edu