util.isa revision 3931:de791fa53d04
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// Mem utility templates and functions 34// 35 36output header {{ 37 /** 38 * Base class for memory operations. 39 */ 40 class Mem : public SparcStaticInst 41 { 42 protected: 43 44 // Constructor 45 Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 46 SparcStaticInst(mnem, _machInst, __opClass) 47 { 48 } 49 50 std::string generateDisassembly(Addr pc, 51 const SymbolTable *symtab) const; 52 }; 53 54 /** 55 * Class for memory operations which use an immediate offset. 56 */ 57 class MemImm : public Mem 58 { 59 protected: 60 61 // Constructor 62 MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 63 Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13)) 64 {} 65 66 std::string generateDisassembly(Addr pc, 67 const SymbolTable *symtab) const; 68 69 const int32_t imm; 70 }; 71}}; 72 73output decoder {{ 74 std::string Mem::generateDisassembly(Addr pc, 75 const SymbolTable *symtab) const 76 { 77 std::stringstream response; 78 bool load = flags[IsLoad]; 79 bool store = flags[IsStore]; 80 81 printMnemonic(response, mnemonic); 82 if(store) 83 { 84 printReg(response, _srcRegIdx[0]); 85 ccprintf(response, ", "); 86 } 87 ccprintf(response, "["); 88 if(_srcRegIdx[!store ? 0 : 1] != 0) 89 { 90 printSrcReg(response, !store ? 0 : 1); 91 ccprintf(response, " + "); 92 } 93 printSrcReg(response, !store ? 1 : 2); 94 ccprintf(response, "]"); 95 if(load) 96 { 97 ccprintf(response, ", "); 98 printReg(response, _destRegIdx[0]); 99 } 100 101 return response.str(); 102 } 103 104 std::string MemImm::generateDisassembly(Addr pc, 105 const SymbolTable *symtab) const 106 { 107 std::stringstream response; 108 bool load = flags[IsLoad]; 109 bool save = flags[IsStore]; 110 111 printMnemonic(response, mnemonic); 112 if(save) 113 { 114 printReg(response, _srcRegIdx[0]); 115 ccprintf(response, ", "); 116 } 117 ccprintf(response, "["); 118 if(_srcRegIdx[!save ? 0 : 1] != 0) 119 { 120 printReg(response, _srcRegIdx[!save ? 0 : 1]); 121 ccprintf(response, " + "); 122 } 123 if(imm >= 0) 124 ccprintf(response, "0x%x]", imm); 125 else 126 ccprintf(response, "-0x%x]", -imm); 127 if(load) 128 { 129 ccprintf(response, ", "); 130 printReg(response, _destRegIdx[0]); 131 } 132 133 return response.str(); 134 } 135}}; 136 137//This template provides the execute functions for a load 138def template LoadExecute {{ 139 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 140 Trace::InstRecord *traceData) const 141 { 142 Fault fault = NoFault; 143 Addr EA; 144 %(fp_enable_check)s; 145 %(op_decl)s; 146 %(op_rd)s; 147 %(ea_code)s; 148 DPRINTF(Sparc, "The address is 0x%x\n", EA); 149 %(fault_check)s; 150 if(fault == NoFault) 151 { 152 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s); 153 } 154 if(fault == NoFault) 155 { 156 %(code)s; 157 } 158 if(fault == NoFault) 159 { 160 //Write the resulting state to the execution context 161 %(op_wb)s; 162 } 163 164 return fault; 165 } 166 167 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 168 Trace::InstRecord * traceData) const 169 { 170 Fault fault = NoFault; 171 Addr EA; 172 uint%(mem_acc_size)s_t Mem; 173 %(fp_enable_check)s; 174 %(ea_decl)s; 175 %(ea_rd)s; 176 %(ea_code)s; 177 %(fault_check)s; 178 if(fault == NoFault) 179 { 180 fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s); 181 } 182 return fault; 183 } 184 185 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc, 186 Trace::InstRecord * traceData) const 187 { 188 Fault fault = NoFault; 189 %(code_decl)s; 190 %(code_rd)s; 191 Mem = pkt->get<typeof(Mem)>(); 192 %(code)s; 193 if(fault == NoFault) 194 { 195 %(code_wb)s; 196 } 197 return fault; 198 } 199}}; 200 201//This template provides the execute functions for a store 202def template StoreExecute {{ 203 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 204 Trace::InstRecord *traceData) const 205 { 206 Fault fault = NoFault; 207 //This is to support the conditional store in cas instructions. 208 //It should be optomized out in all the others 209 bool storeCond = true; 210 Addr EA; 211 %(fp_enable_check)s; 212 %(op_decl)s; 213 %(op_rd)s; 214 %(ea_code)s; 215 DPRINTF(Sparc, "The address is 0x%x\n", EA); 216 %(fault_check)s; 217 if(fault == NoFault) 218 { 219 %(code)s; 220 } 221 if(storeCond && fault == NoFault) 222 { 223 fault = xc->write((uint%(mem_acc_size)s_t)Mem, 224 EA, %(asi_val)s, 0); 225 } 226 if(fault == NoFault) 227 { 228 //Write the resulting state to the execution context 229 %(op_wb)s; 230 } 231 232 return fault; 233 } 234 235 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 236 Trace::InstRecord * traceData) const 237 { 238 Fault fault = NoFault; 239 bool storeCond = true; 240 Addr EA; 241 %(fp_enable_check)s; 242 %(op_decl)s; 243 %(op_rd)s; 244 %(ea_code)s; 245 DPRINTF(Sparc, "The address is 0x%x\n", EA); 246 %(fault_check)s; 247 if(fault == NoFault) 248 { 249 %(code)s; 250 } 251 if(storeCond && fault == NoFault) 252 { 253 fault = xc->write((uint%(mem_acc_size)s_t)Mem, 254 EA, %(asi_val)s, 0); 255 } 256 if(fault == NoFault) 257 { 258 //Write the resulting state to the execution context 259 %(op_wb)s; 260 } 261 return fault; 262 } 263 264 Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc, 265 Trace::InstRecord * traceData) const 266 { 267 return NoFault; 268 } 269}}; 270 271//This delcares the initiateAcc function in memory operations 272def template InitiateAccDeclare {{ 273 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 274}}; 275 276//This declares the completeAcc function in memory operations 277def template CompleteAccDeclare {{ 278 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 279}}; 280 281//Here are some code snippets which check for various fault conditions 282let {{ 283 # The LSB can be zero, since it's really the MSB in doubles and quads 284 # and we're dealing with doubles 285 BlockAlignmentFaultCheck = ''' 286 if(RD & 0xe) 287 fault = new IllegalInstruction; 288 else if(EA & 0x3f) 289 fault = new MemAddressNotAligned; 290 ''' 291 TwinAlignmentFaultCheck = ''' 292 if(RD & 0x1) 293 fault = new IllegalInstruction; 294 else if(EA & 0xf) 295 fault = new MemAddressNotAligned; 296 ''' 297 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 298 # are split into ones that are available in priv and hpriv, and 299 # those that are only available in hpriv 300 AlternateASIPrivFaultCheck = ''' 301 if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) || 302 !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)) 303 fault = new PrivilegedAction; 304 else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) 305 fault = new PrivilegedAction; 306 ''' 307 308}}; 309 310//A simple function to generate the name of the macro op of a certain 311//instruction at a certain micropc 312let {{ 313 def makeMicroName(name, microPc): 314 return name + "::" + name + "_" + str(microPc) 315}}; 316 317//This function properly generates the execute functions for one of the 318//templates above. This is needed because in one case, ea computation, 319//fault checks and the actual code all occur in the same function, 320//and in the other they're distributed across two. Also note that for 321//execute functions, the name of the base class doesn't matter. 322let {{ 323 def doSplitExecute(code, execute, name, Name, asi, opt_flags, microParam): 324 microParam["asi_val"] = asi; 325 codeParam = microParam.copy() 326 codeParam["ea_code"] = '' 327 codeIop = InstObjParams(name, Name, '', code, opt_flags, codeParam) 328 eaIop = InstObjParams(name, Name, '', microParam["ea_code"], 329 opt_flags, microParam) 330 iop = InstObjParams(name, Name, '', code, opt_flags, microParam) 331 (iop.ea_decl, 332 iop.ea_rd, 333 iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb) 334 (iop.code_decl, 335 iop.code_rd, 336 iop.code_wb) = (codeIop.op_decl, codeIop.op_rd, codeIop.op_wb) 337 return execute.subst(iop) 338 339 340 def doDualSplitExecute(code, eaRegCode, eaImmCode, execute, 341 faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags): 342 executeCode = '' 343 for (eaCode, name, Name) in ( 344 (eaRegCode, nameReg, NameReg), 345 (eaImmCode, nameImm, NameImm)): 346 microParams = {"ea_code" : eaCode, "fault_check": faultCode} 347 executeCode += doSplitExecute(code, execute, name, Name, 348 asi, opt_flags, microParams) 349 return executeCode 350}}; 351