util.isa revision 3441:24b9d6cbad0d 
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28//          Gabe Black
29//          Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// Mem utility templates and functions
34//
35
36output header {{
37        /**
38         * Base class for memory operations.
39         */
40        class Mem : public SparcStaticInst
41        {
42          protected:
43
44            // Constructor
45            Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
46                SparcStaticInst(mnem, _machInst, __opClass)
47            {
48            }
49
50            std::string generateDisassembly(Addr pc,
51                    const SymbolTable *symtab) const;
52        };
53
54        /**
55         * Class for memory operations which use an immediate offset.
56         */
57        class MemImm : public Mem
58        {
59          protected:
60
61            // Constructor
62            MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
63                Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
64            {}
65
66            std::string generateDisassembly(Addr pc,
67                    const SymbolTable *symtab) const;
68
69            const int32_t imm;
70        };
71}};
72
73output decoder {{
74        std::string Mem::generateDisassembly(Addr pc,
75                const SymbolTable *symtab) const
76        {
77            std::stringstream response;
78            bool load = flags[IsLoad];
79            bool save = flags[IsStore];
80
81            printMnemonic(response, mnemonic);
82            if(save)
83            {
84                printReg(response, _srcRegIdx[0]);
85                ccprintf(response, ", ");
86            }
87            ccprintf(response, "[ ");
88            printReg(response, _srcRegIdx[!save ? 0 : 1]);
89            ccprintf(response, " + ");
90            printReg(response, _srcRegIdx[!save ? 1 : 2]);
91            ccprintf(response, " ]");
92            if(load)
93            {
94                ccprintf(response, ", ");
95                printReg(response, _destRegIdx[0]);
96            }
97
98            return response.str();
99        }
100
101        std::string MemImm::generateDisassembly(Addr pc,
102                const SymbolTable *symtab) const
103        {
104            std::stringstream response;
105            bool load = flags[IsLoad];
106            bool save = flags[IsStore];
107
108            printMnemonic(response, mnemonic);
109            if(save)
110            {
111                printReg(response, _srcRegIdx[0]);
112                ccprintf(response, ", ");
113            }
114            ccprintf(response, "[ ");
115            printReg(response, _srcRegIdx[!save ? 0 : 1]);
116            if(imm >= 0)
117                ccprintf(response, " + 0x%x ]", imm);
118            else
119                ccprintf(response, " + -0x%x ]", -imm);
120            if(load)
121            {
122                ccprintf(response, ", ");
123                printReg(response, _destRegIdx[0]);
124            }
125
126            return response.str();
127        }
128}};
129
130//This template provides the execute functions for a load
131def template LoadExecute {{
132        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
133                Trace::InstRecord *traceData) const
134        {
135            Fault fault = NoFault;
136            Addr EA;
137            %(op_decl)s;
138            %(op_rd)s;
139            %(ea_code)s;
140            DPRINTF(Sparc, "The address is 0x%x\n", EA);
141            %(fault_check)s;
142            if(fault == NoFault)
143            {
144                fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
145            }
146            if(fault == NoFault)
147            {
148                %(code)s;
149            }
150            if(fault == NoFault)
151            {
152                //Write the resulting state to the execution context
153                %(op_wb)s;
154            }
155
156            return fault;
157        }
158
159        Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
160                Trace::InstRecord * traceData) const
161        {
162            Fault fault = NoFault;
163            Addr EA;
164            uint%(mem_acc_size)s_t Mem;
165            %(ea_decl)s;
166            %(ea_rd)s;
167            %(ea_code)s;
168            %(fault_check)s;
169            if(fault == NoFault)
170            {
171                fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
172            }
173            return fault;
174        }
175
176        Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc,
177                Trace::InstRecord * traceData) const
178        {
179            Fault fault = NoFault;
180            %(code_decl)s;
181            %(code_rd)s;
182            Mem = pkt->get<typeof(Mem)>();
183            %(code)s;
184            if(fault == NoFault)
185            {
186                %(code_wb)s;
187            }
188            return fault;
189        }
190}};
191
192//This template provides the execute functions for a store
193def template StoreExecute {{
194        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
195                Trace::InstRecord *traceData) const
196        {
197            Fault fault = NoFault;
198            uint64_t write_result = 0;
199            //This is to support the conditional store in cas instructions.
200            //It should be optomized out in all the others
201            bool storeCond = true;
202            Addr EA;
203            %(op_decl)s;
204            %(op_rd)s;
205            %(ea_code)s;
206            DPRINTF(Sparc, "The address is 0x%x\n", EA);
207            %(fault_check)s;
208            if(fault == NoFault)
209            {
210                %(code)s;
211            }
212            if(storeCond && fault == NoFault)
213            {
214                fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
215            }
216            if(fault == NoFault)
217            {
218                //Write the resulting state to the execution context
219                %(op_wb)s;
220            }
221
222            return fault;
223        }
224
225        Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
226                Trace::InstRecord * traceData) const
227        {
228            Fault fault = NoFault;
229            uint64_t write_result = 0;
230            bool storeCond = true;
231            Addr EA;
232            %(op_decl)s;
233            %(op_rd)s;
234            %(ea_code)s;
235            DPRINTF(Sparc, "The address is 0x%x\n", EA);
236            %(fault_check)s;
237            if(fault == NoFault)
238            {
239                %(code)s;
240            }
241            if(storeCond && fault == NoFault)
242            {
243                fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
244            }
245            if(fault == NoFault)
246            {
247                //Write the resulting state to the execution context
248                %(op_wb)s;
249            }
250            return fault;
251        }
252
253        Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
254                Trace::InstRecord * traceData) const
255        {
256            return NoFault;
257        }
258}};
259
260//This delcares the initiateAcc function in memory operations
261def template InitiateAccDeclare {{
262    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
263}};
264
265//This declares the completeAcc function in memory operations
266def template CompleteAccDeclare {{
267    Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
268}};
269
270//Here are some code snippets which check for various fault conditions
271let {{
272    # The LSB can be zero, since it's really the MSB in doubles and quads
273    # and we're dealing with doubles
274    BlockAlignmentFaultCheck = '''
275        if(RD & 0xe)
276            fault = new IllegalInstruction;
277        else if(EA & 0x3f)
278            fault = new MemAddressNotAligned;
279    '''
280    # XXX Need to take care of pstate.hpriv as well. The lower ASIs
281    # are split into ones that are available in priv and hpriv, and
282    # those that are only available in hpriv
283    AlternateASIPrivFaultCheck = '''
284        if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0)
285            fault = new PrivilegedAction;
286        else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
287            fault = new PrivilegedAction;
288    '''
289
290}};
291
292//A simple function to generate the name of the macro op of a certain
293//instruction at a certain micropc
294let {{
295    def makeMicroName(name, microPc):
296        return name + "::" + name + "_" + str(microPc)
297}};
298
299//This function properly generates the execute functions for one of the
300//templates above. This is needed because in one case, ea computation,
301//fault checks and the actual code all occur in the same function,
302//and in the other they're distributed across two. Also note that for
303//execute functions, the name of the base class doesn't matter.
304let {{
305    def doSplitExecute(code, eaCode, execute,
306            faultCode, name, Name, opt_flags):
307        codeIop = InstObjParams(name, Name, '', code, opt_flags)
308        eaIop = InstObjParams(name, Name, '', eaCode,
309                opt_flags, {"fault_check": faultCode})
310        iop = InstObjParams(name, Name, '', code, opt_flags,
311                {"fault_check": faultCode, "ea_code" : eaCode})
312        (iop.ea_decl,
313         iop.ea_rd,
314         iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb)
315        (iop.code_decl,
316         iop.code_rd,
317         iop.code_wb) = (codeIop.op_decl, codeIop.op_rd, codeIop.op_wb)
318        return execute.subst(iop)
319
320
321    def doDualSplitExecute(code, eaRegCode, eaImmCode, execute,
322            faultCode, nameReg, nameImm, NameReg, NameImm, opt_flags):
323        executeCode = ''
324        for (eaCode, name, Name) in (
325                (eaRegCode, nameReg, NameReg),
326                (eaImmCode, nameImm, NameImm)):
327            executeCode += doSplitExecute(code, eaCode,
328                    execute, faultCode, name, Name, opt_flags)
329        return executeCode
330}};
331