util.isa revision 12106:7784fac1b159 
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28//          Gabe Black
29//          Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// Mem utility templates and functions
34//
35
36output header {{
37        /**
38         * Base class for memory operations.
39         */
40        class Mem : public SparcStaticInst
41        {
42          protected:
43
44            // Constructor
45            Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
46                SparcStaticInst(mnem, _machInst, __opClass)
47            {
48            }
49
50            std::string generateDisassembly(Addr pc,
51                    const SymbolTable *symtab) const;
52        };
53
54        /**
55         * Class for memory operations which use an immediate offset.
56         */
57        class MemImm : public Mem
58        {
59          protected:
60
61            // Constructor
62            MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
63                Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
64            {}
65
66            std::string generateDisassembly(Addr pc,
67                    const SymbolTable *symtab) const;
68
69            const int32_t imm;
70        };
71}};
72
73output decoder {{
74        std::string Mem::generateDisassembly(Addr pc,
75                const SymbolTable *symtab) const
76        {
77            std::stringstream response;
78            bool load = flags[IsLoad];
79            bool store = flags[IsStore];
80
81            printMnemonic(response, mnemonic);
82            if (store) {
83                printReg(response, _srcRegIdx[0]);
84                ccprintf(response, ", ");
85            }
86            ccprintf(response, "[");
87            if (_srcRegIdx[!store ? 0 : 1].index() != 0) {
88                printSrcReg(response, !store ? 0 : 1);
89                ccprintf(response, " + ");
90            }
91            printSrcReg(response, !store ? 1 : 2);
92            ccprintf(response, "]");
93            if (load) {
94                ccprintf(response, ", ");
95                printReg(response, _destRegIdx[0]);
96            }
97
98            return response.str();
99        }
100
101        std::string MemImm::generateDisassembly(Addr pc,
102                const SymbolTable *symtab) const
103        {
104            std::stringstream response;
105            bool load = flags[IsLoad];
106            bool save = flags[IsStore];
107
108            printMnemonic(response, mnemonic);
109            if (save) {
110                printReg(response, _srcRegIdx[0]);
111                ccprintf(response, ", ");
112            }
113            ccprintf(response, "[");
114            if (_srcRegIdx[!save ? 0 : 1].index() != 0) {
115                printReg(response, _srcRegIdx[!save ? 0 : 1]);
116                ccprintf(response, " + ");
117            }
118            if (imm >= 0)
119                ccprintf(response, "0x%x]", imm);
120            else
121                ccprintf(response, "-0x%x]", -imm);
122            if (load) {
123                ccprintf(response, ", ");
124                printReg(response, _destRegIdx[0]);
125            }
126
127            return response.str();
128        }
129}};
130
131// This template provides the execute functions for a load
132def template LoadExecute {{
133        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
134                Trace::InstRecord *traceData) const
135        {
136            Fault fault = NoFault;
137            Addr EA;
138            %(fp_enable_check)s;
139            %(op_decl)s;
140            %(op_rd)s;
141            %(ea_code)s;
142            DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
143            %(fault_check)s;
144            if (fault == NoFault) {
145                %(EA_trunc)s
146                fault = readMemAtomic(xc, traceData, EA, Mem, %(asi_val)s);
147            }
148            if (fault == NoFault) {
149                %(code)s;
150            }
151            if (fault == NoFault) {
152                // Write the resulting state to the execution context
153                %(op_wb)s;
154            }
155
156            return fault;
157        }
158}};
159
160def template LoadInitiateAcc {{
161        Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc,
162                Trace::InstRecord * traceData) const
163        {
164            Fault fault = NoFault;
165            Addr EA;
166            %(fp_enable_check)s;
167            %(op_decl)s;
168            %(op_rd)s;
169            %(ea_code)s;
170            DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
171            %(fault_check)s;
172            if (fault == NoFault) {
173                %(EA_trunc)s
174                fault = initiateMemRead(xc, traceData, EA, Mem, %(asi_val)s);
175            }
176            return fault;
177        }
178}};
179
180def template LoadCompleteAcc {{
181        Fault %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT * xc,
182                Trace::InstRecord * traceData) const
183        {
184            Fault fault = NoFault;
185            %(op_decl)s;
186            %(op_rd)s;
187            getMem(pkt, Mem, traceData);
188            %(code)s;
189            if (fault == NoFault) {
190                %(op_wb)s;
191            }
192            return fault;
193        }
194}};
195
196// This template provides the execute functions for a store
197def template StoreExecute {{
198        Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
199                Trace::InstRecord *traceData) const
200        {
201            Fault fault = NoFault;
202            // This is to support the conditional store in cas instructions.
203            // It should be optomized out in all the others
204            bool storeCond = true;
205            Addr EA;
206            %(fp_enable_check)s;
207            %(op_decl)s;
208            %(op_rd)s;
209            %(ea_code)s;
210            DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
211            %(fault_check)s;
212            if (fault == NoFault) {
213                %(code)s;
214            }
215            if (storeCond && fault == NoFault) {
216                %(EA_trunc)s
217                fault = writeMemAtomic(xc, traceData, Mem, EA, %(asi_val)s, 0);
218            }
219            if (fault == NoFault) {
220                // Write the resulting state to the execution context
221                %(op_wb)s;
222            }
223
224            return fault;
225        }
226}};
227
228def template StoreInitiateAcc {{
229        Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc,
230                Trace::InstRecord * traceData) const
231        {
232            Fault fault = NoFault;
233            bool storeCond = true;
234            Addr EA;
235            %(fp_enable_check)s;
236            %(op_decl)s;
237
238            %(op_rd)s;
239            %(ea_code)s;
240            DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
241            %(fault_check)s;
242            if (fault == NoFault) {
243                %(code)s;
244            }
245            if (storeCond && fault == NoFault) {
246                %(EA_trunc)s
247                fault = writeMemTiming(xc, traceData, Mem, EA, %(asi_val)s, 0);
248            }
249            return fault;
250        }
251}};
252
253def template StoreCompleteAcc {{
254        Fault %(class_name)s::completeAcc(PacketPtr, CPU_EXEC_CONTEXT * xc,
255                Trace::InstRecord * traceData) const
256        {
257            return NoFault;
258        }
259}};
260
261def template EACompExecute {{
262    Fault
263    %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
264                                   Trace::InstRecord *traceData) const
265    {
266        Addr EA;
267        Fault fault = NoFault;
268        %(op_decl)s;
269        %(op_rd)s;
270        %(ea_code)s;
271        %(fault_check)s;
272
273        // NOTE: Trace Data is written using execute or completeAcc templates
274        if (fault == NoFault) {
275            %(EA_trunc)s
276            xc->setEA(EA);
277        }
278
279        return fault;
280    }
281}};
282
283def template EACompDeclare {{
284    Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
285}};
286
287// This delcares the initiateAcc function in memory operations
288def template InitiateAccDeclare {{
289    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
290}};
291
292// This declares the completeAcc function in memory operations
293def template CompleteAccDeclare {{
294    Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
295}};
296
297// Here are some code snippets which check for various fault conditions
298let {{
299    LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc]
300    StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc]
301
302    # The LSB can be zero, since it's really the MSB in doubles and quads
303    # and we're dealing with doubles
304    BlockAlignmentFaultCheck = '''
305        if (RD & 0xe)
306            fault = std::make_shared<IllegalInstruction>();
307        else if (EA & 0x3f)
308            fault = std::make_shared<MemAddressNotAligned>();
309    '''
310    TwinAlignmentFaultCheck = '''
311        if (RD & 0x1)
312            fault = std::make_shared<IllegalInstruction>();
313        else if (EA & 0xf)
314            fault = std::make_shared<MemAddressNotAligned>();
315    '''
316    # XXX Need to take care of pstate.hpriv as well. The lower ASIs
317    # are split into ones that are available in priv and hpriv, and
318    # those that are only available in hpriv
319    AlternateASIPrivFaultCheck = '''
320        if ((!Pstate.priv && !Hpstate.hpriv &&
321             !asiIsUnPriv((ASI)EXT_ASI)) ||
322            (!Hpstate.hpriv && asiIsHPriv((ASI)EXT_ASI)))
323            fault = std::make_shared<PrivilegedAction>();
324        else if (asiIsAsIfUser((ASI)EXT_ASI) && !Pstate.priv)
325            fault = std::make_shared<PrivilegedAction>();
326    '''
327
328    TruncateEA = '''
329        if (!FullSystem) {
330            EA = Pstate.am ? EA<31:0> : EA;
331        }
332    '''
333}};
334
335// A simple function to generate the name of the macro op of a certain
336// instruction at a certain micropc
337let {{
338    def makeMicroName(name, microPc):
339            return name + "::" + name + "_" + str(microPc)
340}};
341
342// This function properly generates the execute functions for one of the
343// templates above. This is needed because in one case, ea computation,
344// fault checks and the actual code all occur in the same function,
345// and in the other they're distributed across two. Also note that for
346// execute functions, the name of the base class doesn't matter.
347let {{
348    def doSplitExecute(execute, name, Name, asi, opt_flags, microParam):
349        microParam["asi_val"] = asi;
350        iop = InstObjParams(name, Name, '', microParam, opt_flags)
351        (execf, initf, compf) = execute
352        return execf.subst(iop) + initf.subst(iop) + compf.subst(iop)
353
354
355    def doDualSplitExecute(code, postacc_code, eaRegCode, eaImmCode, execute,
356            faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags):
357        executeCode = ''
358        for (eaCode, name, Name) in (
359                (eaRegCode, nameReg, NameReg),
360                (eaImmCode, nameImm, NameImm)):
361            microParams = {"code": code, "postacc_code" : postacc_code,
362                "ea_code": eaCode, "fault_check": faultCode,
363                "EA_trunc" : TruncateEA}
364            executeCode += doSplitExecute(execute, name, Name,
365                    asi, opt_flags, microParams)
366        return executeCode
367}};
368