util.isa revision 12106:7784fac1b159
110448Snilay@cs.wisc.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 210448Snilay@cs.wisc.edu// All rights reserved. 310448Snilay@cs.wisc.edu// 410448Snilay@cs.wisc.edu// Redistribution and use in source and binary forms, with or without 510448Snilay@cs.wisc.edu// modification, are permitted provided that the following conditions are 610448Snilay@cs.wisc.edu// met: redistributions of source code must retain the above copyright 710448Snilay@cs.wisc.edu// notice, this list of conditions and the following disclaimer; 810448Snilay@cs.wisc.edu// redistributions in binary form must reproduce the above copyright 910448Snilay@cs.wisc.edu// notice, this list of conditions and the following disclaimer in the 1010448Snilay@cs.wisc.edu// documentation and/or other materials provided with the distribution; 1110448Snilay@cs.wisc.edu// neither the name of the copyright holders nor the names of its 1210448Snilay@cs.wisc.edu// contributors may be used to endorse or promote products derived from 1310448Snilay@cs.wisc.edu// this software without specific prior written permission. 1410448Snilay@cs.wisc.edu// 1510448Snilay@cs.wisc.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1610448Snilay@cs.wisc.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1710448Snilay@cs.wisc.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1810448Snilay@cs.wisc.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1910448Snilay@cs.wisc.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2010448Snilay@cs.wisc.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2110448Snilay@cs.wisc.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2210447Snilay@cs.wisc.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2310447Snilay@cs.wisc.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2410447Snilay@cs.wisc.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2510447Snilay@cs.wisc.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2610447Snilay@cs.wisc.edu// 2710447Snilay@cs.wisc.edu// Authors: Ali Saidi 2810447Snilay@cs.wisc.edu// Gabe Black 2910447Snilay@cs.wisc.edu// Steve Reinhardt 3010447Snilay@cs.wisc.edu 3110447Snilay@cs.wisc.edu//////////////////////////////////////////////////////////////////// 3210447Snilay@cs.wisc.edu// 3310447Snilay@cs.wisc.edu// Mem utility templates and functions 3410447Snilay@cs.wisc.edu// 3510447Snilay@cs.wisc.edu 3610447Snilay@cs.wisc.eduoutput header {{ 3710447Snilay@cs.wisc.edu /** 3810447Snilay@cs.wisc.edu * Base class for memory operations. 3910447Snilay@cs.wisc.edu */ 4010447Snilay@cs.wisc.edu class Mem : public SparcStaticInst 4110447Snilay@cs.wisc.edu { 4210447Snilay@cs.wisc.edu protected: 4310447Snilay@cs.wisc.edu 4410447Snilay@cs.wisc.edu // Constructor 4510447Snilay@cs.wisc.edu Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 4610447Snilay@cs.wisc.edu SparcStaticInst(mnem, _machInst, __opClass) 4710447Snilay@cs.wisc.edu { 4810447Snilay@cs.wisc.edu } 4910447Snilay@cs.wisc.edu 5010447Snilay@cs.wisc.edu std::string generateDisassembly(Addr pc, 5110447Snilay@cs.wisc.edu const SymbolTable *symtab) const; 5210447Snilay@cs.wisc.edu }; 5310447Snilay@cs.wisc.edu 5410447Snilay@cs.wisc.edu /** 5510447Snilay@cs.wisc.edu * Class for memory operations which use an immediate offset. 5610447Snilay@cs.wisc.edu */ 5710447Snilay@cs.wisc.edu class MemImm : public Mem 5810447Snilay@cs.wisc.edu { 5910447Snilay@cs.wisc.edu protected: 6010447Snilay@cs.wisc.edu 6110447Snilay@cs.wisc.edu // Constructor 6210447Snilay@cs.wisc.edu MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 6310447Snilay@cs.wisc.edu Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13)) 6410447Snilay@cs.wisc.edu {} 6510447Snilay@cs.wisc.edu 6610447Snilay@cs.wisc.edu std::string generateDisassembly(Addr pc, 6710447Snilay@cs.wisc.edu const SymbolTable *symtab) const; 6810447Snilay@cs.wisc.edu 6910447Snilay@cs.wisc.edu const int32_t imm; 7010447Snilay@cs.wisc.edu }; 7110447Snilay@cs.wisc.edu}}; 7210447Snilay@cs.wisc.edu 7310447Snilay@cs.wisc.eduoutput decoder {{ 7410447Snilay@cs.wisc.edu std::string Mem::generateDisassembly(Addr pc, 7510447Snilay@cs.wisc.edu const SymbolTable *symtab) const 7610447Snilay@cs.wisc.edu { 7710447Snilay@cs.wisc.edu std::stringstream response; 7810447Snilay@cs.wisc.edu bool load = flags[IsLoad]; 7910447Snilay@cs.wisc.edu bool store = flags[IsStore]; 8010447Snilay@cs.wisc.edu 8110447Snilay@cs.wisc.edu printMnemonic(response, mnemonic); 8210447Snilay@cs.wisc.edu if (store) { 8310447Snilay@cs.wisc.edu printReg(response, _srcRegIdx[0]); 8410447Snilay@cs.wisc.edu ccprintf(response, ", "); 8510447Snilay@cs.wisc.edu } 8610447Snilay@cs.wisc.edu ccprintf(response, "["); 8710447Snilay@cs.wisc.edu if (_srcRegIdx[!store ? 0 : 1].index() != 0) { 8810447Snilay@cs.wisc.edu printSrcReg(response, !store ? 0 : 1); 8910447Snilay@cs.wisc.edu ccprintf(response, " + "); 9010447Snilay@cs.wisc.edu } 9110447Snilay@cs.wisc.edu printSrcReg(response, !store ? 1 : 2); 9210447Snilay@cs.wisc.edu ccprintf(response, "]"); 9310447Snilay@cs.wisc.edu if (load) { 9410447Snilay@cs.wisc.edu ccprintf(response, ", "); 9510447Snilay@cs.wisc.edu printReg(response, _destRegIdx[0]); 9610447Snilay@cs.wisc.edu } 9710447Snilay@cs.wisc.edu 9810447Snilay@cs.wisc.edu return response.str(); 9910447Snilay@cs.wisc.edu } 10010447Snilay@cs.wisc.edu 10110447Snilay@cs.wisc.edu std::string MemImm::generateDisassembly(Addr pc, 10210447Snilay@cs.wisc.edu const SymbolTable *symtab) const 10310447Snilay@cs.wisc.edu { 10410447Snilay@cs.wisc.edu std::stringstream response; 10510447Snilay@cs.wisc.edu bool load = flags[IsLoad]; 10610447Snilay@cs.wisc.edu bool save = flags[IsStore]; 10710447Snilay@cs.wisc.edu 10810447Snilay@cs.wisc.edu printMnemonic(response, mnemonic); 10910447Snilay@cs.wisc.edu if (save) { 11010447Snilay@cs.wisc.edu printReg(response, _srcRegIdx[0]); 11110447Snilay@cs.wisc.edu ccprintf(response, ", "); 11210447Snilay@cs.wisc.edu } 11310447Snilay@cs.wisc.edu ccprintf(response, "["); 11410447Snilay@cs.wisc.edu if (_srcRegIdx[!save ? 0 : 1].index() != 0) { 11510447Snilay@cs.wisc.edu printReg(response, _srcRegIdx[!save ? 0 : 1]); 11610447Snilay@cs.wisc.edu ccprintf(response, " + "); 11710447Snilay@cs.wisc.edu } 11810447Snilay@cs.wisc.edu if (imm >= 0) 11910447Snilay@cs.wisc.edu ccprintf(response, "0x%x]", imm); 12010447Snilay@cs.wisc.edu else 12110447Snilay@cs.wisc.edu ccprintf(response, "-0x%x]", -imm); 12210447Snilay@cs.wisc.edu if (load) { 12310447Snilay@cs.wisc.edu ccprintf(response, ", "); 12410447Snilay@cs.wisc.edu printReg(response, _destRegIdx[0]); 12510447Snilay@cs.wisc.edu } 12610447Snilay@cs.wisc.edu 12710447Snilay@cs.wisc.edu return response.str(); 12810447Snilay@cs.wisc.edu } 12910447Snilay@cs.wisc.edu}}; 13010447Snilay@cs.wisc.edu 13110447Snilay@cs.wisc.edu// This template provides the execute functions for a load 13210447Snilay@cs.wisc.edudef template LoadExecute {{ 13310447Snilay@cs.wisc.edu Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 13410447Snilay@cs.wisc.edu Trace::InstRecord *traceData) const 13510447Snilay@cs.wisc.edu { 13610447Snilay@cs.wisc.edu Fault fault = NoFault; 13710447Snilay@cs.wisc.edu Addr EA; 13810447Snilay@cs.wisc.edu %(fp_enable_check)s; 13910447Snilay@cs.wisc.edu %(op_decl)s; 14010447Snilay@cs.wisc.edu %(op_rd)s; 14110447Snilay@cs.wisc.edu %(ea_code)s; 14210447Snilay@cs.wisc.edu DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 14310447Snilay@cs.wisc.edu %(fault_check)s; 14410447Snilay@cs.wisc.edu if (fault == NoFault) { 14510447Snilay@cs.wisc.edu %(EA_trunc)s 14610447Snilay@cs.wisc.edu fault = readMemAtomic(xc, traceData, EA, Mem, %(asi_val)s); 14710447Snilay@cs.wisc.edu } 14810447Snilay@cs.wisc.edu if (fault == NoFault) { 14910447Snilay@cs.wisc.edu %(code)s; 15010447Snilay@cs.wisc.edu } 15110447Snilay@cs.wisc.edu if (fault == NoFault) { 15210447Snilay@cs.wisc.edu // Write the resulting state to the execution context 15310447Snilay@cs.wisc.edu %(op_wb)s; 15410447Snilay@cs.wisc.edu } 15510447Snilay@cs.wisc.edu 15610447Snilay@cs.wisc.edu return fault; 15710447Snilay@cs.wisc.edu } 15810447Snilay@cs.wisc.edu}}; 15910447Snilay@cs.wisc.edu 16010447Snilay@cs.wisc.edudef template LoadInitiateAcc {{ 16110447Snilay@cs.wisc.edu Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, 16210447Snilay@cs.wisc.edu Trace::InstRecord * traceData) const 16310447Snilay@cs.wisc.edu { 16410447Snilay@cs.wisc.edu Fault fault = NoFault; 16510447Snilay@cs.wisc.edu Addr EA; 16610447Snilay@cs.wisc.edu %(fp_enable_check)s; 16710447Snilay@cs.wisc.edu %(op_decl)s; 16810447Snilay@cs.wisc.edu %(op_rd)s; 16910447Snilay@cs.wisc.edu %(ea_code)s; 17010447Snilay@cs.wisc.edu DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 17110447Snilay@cs.wisc.edu %(fault_check)s; 17210447Snilay@cs.wisc.edu if (fault == NoFault) { 17310447Snilay@cs.wisc.edu %(EA_trunc)s 17410447Snilay@cs.wisc.edu fault = initiateMemRead(xc, traceData, EA, Mem, %(asi_val)s); 17510447Snilay@cs.wisc.edu } 17610447Snilay@cs.wisc.edu return fault; 17710447Snilay@cs.wisc.edu } 17810447Snilay@cs.wisc.edu}}; 17910447Snilay@cs.wisc.edu 18010447Snilay@cs.wisc.edudef template LoadCompleteAcc {{ 18110447Snilay@cs.wisc.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT * xc, 18210447Snilay@cs.wisc.edu Trace::InstRecord * traceData) const 18310447Snilay@cs.wisc.edu { 18410447Snilay@cs.wisc.edu Fault fault = NoFault; 18510447Snilay@cs.wisc.edu %(op_decl)s; 18610447Snilay@cs.wisc.edu %(op_rd)s; 18710447Snilay@cs.wisc.edu getMem(pkt, Mem, traceData); 18810447Snilay@cs.wisc.edu %(code)s; 18910447Snilay@cs.wisc.edu if (fault == NoFault) { 19010447Snilay@cs.wisc.edu %(op_wb)s; 19110447Snilay@cs.wisc.edu } 19210447Snilay@cs.wisc.edu return fault; 19310447Snilay@cs.wisc.edu } 19410447Snilay@cs.wisc.edu}}; 19510447Snilay@cs.wisc.edu 19610447Snilay@cs.wisc.edu// This template provides the execute functions for a store 19710447Snilay@cs.wisc.edudef template StoreExecute {{ 19810447Snilay@cs.wisc.edu Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 19910447Snilay@cs.wisc.edu Trace::InstRecord *traceData) const 20010447Snilay@cs.wisc.edu { 20110447Snilay@cs.wisc.edu Fault fault = NoFault; 20210447Snilay@cs.wisc.edu // This is to support the conditional store in cas instructions. 20310447Snilay@cs.wisc.edu // It should be optomized out in all the others 20410447Snilay@cs.wisc.edu bool storeCond = true; 20510447Snilay@cs.wisc.edu Addr EA; 20610447Snilay@cs.wisc.edu %(fp_enable_check)s; 20710447Snilay@cs.wisc.edu %(op_decl)s; 20810447Snilay@cs.wisc.edu %(op_rd)s; 20910447Snilay@cs.wisc.edu %(ea_code)s; 21010447Snilay@cs.wisc.edu DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 21110447Snilay@cs.wisc.edu %(fault_check)s; 21210447Snilay@cs.wisc.edu if (fault == NoFault) { 21310447Snilay@cs.wisc.edu %(code)s; 21410447Snilay@cs.wisc.edu } 21510447Snilay@cs.wisc.edu if (storeCond && fault == NoFault) { 21610447Snilay@cs.wisc.edu %(EA_trunc)s 21710447Snilay@cs.wisc.edu fault = writeMemAtomic(xc, traceData, Mem, EA, %(asi_val)s, 0); 21810447Snilay@cs.wisc.edu } 21910447Snilay@cs.wisc.edu if (fault == NoFault) { 22010447Snilay@cs.wisc.edu // Write the resulting state to the execution context 22110447Snilay@cs.wisc.edu %(op_wb)s; 22210447Snilay@cs.wisc.edu } 22310447Snilay@cs.wisc.edu 22410447Snilay@cs.wisc.edu return fault; 22510447Snilay@cs.wisc.edu } 22610447Snilay@cs.wisc.edu}}; 22710447Snilay@cs.wisc.edu 22810447Snilay@cs.wisc.edudef template StoreInitiateAcc {{ 22910447Snilay@cs.wisc.edu Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, 23010447Snilay@cs.wisc.edu Trace::InstRecord * traceData) const 23110447Snilay@cs.wisc.edu { 23210447Snilay@cs.wisc.edu Fault fault = NoFault; 23310447Snilay@cs.wisc.edu bool storeCond = true; 23410447Snilay@cs.wisc.edu Addr EA; 23510447Snilay@cs.wisc.edu %(fp_enable_check)s; 23610447Snilay@cs.wisc.edu %(op_decl)s; 23710447Snilay@cs.wisc.edu 23810447Snilay@cs.wisc.edu %(op_rd)s; 23910447Snilay@cs.wisc.edu %(ea_code)s; 240 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 241 %(fault_check)s; 242 if (fault == NoFault) { 243 %(code)s; 244 } 245 if (storeCond && fault == NoFault) { 246 %(EA_trunc)s 247 fault = writeMemTiming(xc, traceData, Mem, EA, %(asi_val)s, 0); 248 } 249 return fault; 250 } 251}}; 252 253def template StoreCompleteAcc {{ 254 Fault %(class_name)s::completeAcc(PacketPtr, CPU_EXEC_CONTEXT * xc, 255 Trace::InstRecord * traceData) const 256 { 257 return NoFault; 258 } 259}}; 260 261def template EACompExecute {{ 262 Fault 263 %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc, 264 Trace::InstRecord *traceData) const 265 { 266 Addr EA; 267 Fault fault = NoFault; 268 %(op_decl)s; 269 %(op_rd)s; 270 %(ea_code)s; 271 %(fault_check)s; 272 273 // NOTE: Trace Data is written using execute or completeAcc templates 274 if (fault == NoFault) { 275 %(EA_trunc)s 276 xc->setEA(EA); 277 } 278 279 return fault; 280 } 281}}; 282 283def template EACompDeclare {{ 284 Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 285}}; 286 287// This delcares the initiateAcc function in memory operations 288def template InitiateAccDeclare {{ 289 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 290}}; 291 292// This declares the completeAcc function in memory operations 293def template CompleteAccDeclare {{ 294 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 295}}; 296 297// Here are some code snippets which check for various fault conditions 298let {{ 299 LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc] 300 StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc] 301 302 # The LSB can be zero, since it's really the MSB in doubles and quads 303 # and we're dealing with doubles 304 BlockAlignmentFaultCheck = ''' 305 if (RD & 0xe) 306 fault = std::make_shared<IllegalInstruction>(); 307 else if (EA & 0x3f) 308 fault = std::make_shared<MemAddressNotAligned>(); 309 ''' 310 TwinAlignmentFaultCheck = ''' 311 if (RD & 0x1) 312 fault = std::make_shared<IllegalInstruction>(); 313 else if (EA & 0xf) 314 fault = std::make_shared<MemAddressNotAligned>(); 315 ''' 316 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 317 # are split into ones that are available in priv and hpriv, and 318 # those that are only available in hpriv 319 AlternateASIPrivFaultCheck = ''' 320 if ((!Pstate.priv && !Hpstate.hpriv && 321 !asiIsUnPriv((ASI)EXT_ASI)) || 322 (!Hpstate.hpriv && asiIsHPriv((ASI)EXT_ASI))) 323 fault = std::make_shared<PrivilegedAction>(); 324 else if (asiIsAsIfUser((ASI)EXT_ASI) && !Pstate.priv) 325 fault = std::make_shared<PrivilegedAction>(); 326 ''' 327 328 TruncateEA = ''' 329 if (!FullSystem) { 330 EA = Pstate.am ? EA<31:0> : EA; 331 } 332 ''' 333}}; 334 335// A simple function to generate the name of the macro op of a certain 336// instruction at a certain micropc 337let {{ 338 def makeMicroName(name, microPc): 339 return name + "::" + name + "_" + str(microPc) 340}}; 341 342// This function properly generates the execute functions for one of the 343// templates above. This is needed because in one case, ea computation, 344// fault checks and the actual code all occur in the same function, 345// and in the other they're distributed across two. Also note that for 346// execute functions, the name of the base class doesn't matter. 347let {{ 348 def doSplitExecute(execute, name, Name, asi, opt_flags, microParam): 349 microParam["asi_val"] = asi; 350 iop = InstObjParams(name, Name, '', microParam, opt_flags) 351 (execf, initf, compf) = execute 352 return execf.subst(iop) + initf.subst(iop) + compf.subst(iop) 353 354 355 def doDualSplitExecute(code, postacc_code, eaRegCode, eaImmCode, execute, 356 faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags): 357 executeCode = '' 358 for (eaCode, name, Name) in ( 359 (eaRegCode, nameReg, NameReg), 360 (eaImmCode, nameImm, NameImm)): 361 microParams = {"code": code, "postacc_code" : postacc_code, 362 "ea_code": eaCode, "fault_check": faultCode, 363 "EA_trunc" : TruncateEA} 364 executeCode += doSplitExecute(execute, name, Name, 365 asi, opt_flags, microParams) 366 return executeCode 367}}; 368