swap.isa revision 4648:173a212f5091
12330SN/A// Copyright (c) 2007 The Regents of The University of Michigan 22330SN/A// All rights reserved. 32330SN/A// 42330SN/A// Redistribution and use in source and binary forms, with or without 52330SN/A// modification, are permitted provided that the following conditions are 62330SN/A// met: redistributions of source code must retain the above copyright 72330SN/A// notice, this list of conditions and the following disclaimer; 82330SN/A// redistributions in binary form must reproduce the above copyright 92330SN/A// notice, this list of conditions and the following disclaimer in the 102330SN/A// documentation and/or other materials provided with the distribution; 112330SN/A// neither the name of the copyright holders nor the names of its 122330SN/A// contributors may be used to endorse or promote products derived from 132330SN/A// this software without specific prior written permission. 142330SN/A// 152330SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162330SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172330SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182330SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192330SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202330SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212330SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222330SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232330SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242330SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252330SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262330SN/A// 272689Sktlim@umich.edu// Authors: Gabe Black 282689Sktlim@umich.edu// Ali Saidi 292330SN/A 302330SN/A//This template provides the execute functions for a swap 312683Sktlim@umich.edudef template SwapExecute {{ 322683Sktlim@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 332315SN/A Trace::InstRecord *traceData) const 342315SN/A { 352683Sktlim@umich.edu Fault fault = NoFault; 362680SN/A //This is to support the conditional store in cas instructions. 372315SN/A //It should be optomized out in all the others 382315SN/A bool storeCond = true; 392330SN/A Addr EA; 402330SN/A %(fp_enable_check)s; 412330SN/A %(op_decl)s; 422315SN/A uint64_t mem_data; 432350SN/A 442680SN/A %(op_rd)s; 452680SN/A %(ea_code)s; 462683Sktlim@umich.edu DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 472683Sktlim@umich.edu %(fault_check)s; 482683Sktlim@umich.edu if(fault == NoFault) 492683Sktlim@umich.edu { 502350SN/A %(code)s; 512680SN/A } 522680SN/A if(storeCond && fault == NoFault) 532315SN/A { 542315SN/A %(EA_trunc)s 552680SN/A fault = xc->write((uint%(mem_acc_size)s_t)Mem, 562683Sktlim@umich.edu EA, %(asi_val)s, &mem_data); 572683Sktlim@umich.edu } 582330SN/A if(fault == NoFault) 592315SN/A { 602315SN/A //Handle the swapping 612315SN/A %(postacc_code)s; 622683Sktlim@umich.edu } 632683Sktlim@umich.edu if(fault == NoFault) 642680SN/A { 652683Sktlim@umich.edu //Write the resulting state to the execution context 662683Sktlim@umich.edu %(op_wb)s; 672683Sktlim@umich.edu } 682683Sktlim@umich.edu 692683Sktlim@umich.edu return fault; 702315SN/A } 712315SN/A}}; 722315SN/A 732315SN/A 742680SN/Adef template SwapInitiateAcc {{ 752315SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 762315SN/A Trace::InstRecord * traceData) const 772315SN/A { 782680SN/A Fault fault = NoFault; 792680SN/A Addr EA; 802315SN/A %(fp_enable_check)s; 812315SN/A uint64_t mem_data = 0; 822680SN/A %(op_decl)s; 832315SN/A %(op_rd)s; 842315SN/A %(ea_code)s; 852680SN/A 862315SN/A DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); 872680SN/A %(fault_check)s; 882315SN/A 892680SN/A if(fault == NoFault) 902315SN/A { 912680SN/A %(code)s; 922330SN/A } 932680SN/A if(fault == NoFault) 942690Sktlim@umich.edu { 952690Sktlim@umich.edu %(EA_trunc)s 962690Sktlim@umich.edu fault = xc->write((uint%(mem_acc_size)s_t)Mem, 972690Sktlim@umich.edu EA, %(asi_val)s, &mem_data); 982690Sktlim@umich.edu } 992690Sktlim@umich.edu return fault; 1002690Sktlim@umich.edu } 1012315SN/A}}; 1022690Sktlim@umich.edu 1032690Sktlim@umich.edu 1042680SN/A 1052315SN/Adef template SwapCompleteAcc {{ 1062315SN/A Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc, 1072680SN/A Trace::InstRecord * traceData) const 1082315SN/A { 1092315SN/A Fault fault = NoFault; 1102330SN/A %(op_decl)s; 1112680SN/A 1122680SN/A uint64_t mem_data = pkt->get<uint%(mem_acc_size)s_t>(); 1132330SN/A 1142315SN/A if(fault == NoFault) 1152315SN/A { 1162315SN/A //Handle the swapping 1172680SN/A %(postacc_code)s; 1182315SN/A } 1192315SN/A if(fault == NoFault) 1202680SN/A { 1212315SN/A //Write the resulting state to the execution context 1222315SN/A %(op_wb)s; 1232887Sktlim@umich.edu } 1242315SN/A 1252315SN/A return fault; 1262680SN/A } 1272315SN/A}}; 1282315SN/A 1292680SN/Alet {{ 1302315SN/A SwapFuncs = [SwapExecute, SwapInitiateAcc, SwapCompleteAcc] 1312315SN/A}}; 1322680SN/A 1332315SN/A 1342680SN/Adef format Swap(code, postacc_code, mem_flags, *opt_flags) {{ 1352680SN/A mem_flags = makeList(mem_flags) 1362315SN/A flags = string.join(mem_flags, '|') 1372315SN/A 1382680SN/A (header_output, 1392315SN/A decoder_output, 1402680SN/A exec_output, 1412315SN/A decode_block) = doMemFormat(code, SwapFuncs, '', name, Name, flags, 1422680SN/A ["IsStoreConditional"], postacc_code) 1432315SN/A}}; 1442315SN/A 1452680SN/Adef format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{ 1462315SN/A mem_flags = makeList(mem_flags) 1472680SN/A mem_flags.append(asi) 1482680SN/A flags = string.join(mem_flags, '|') 1492315SN/A (header_output, 1502680SN/A decoder_output, 1512680SN/A exec_output, 1522315SN/A decode_block) = doMemFormat(code, SwapFuncs, AlternateASIPrivFaultCheck, 1532315SN/A name, Name, flags, ["IsStoreConditional"], postacc_code) 1542680SN/A}}; 1552315SN/A 1562315SN/A 1572680SN/Alet {{ 1582315SN/A def doCasFormat(code, execute, faultCode, name, Name, asi, opt_flags, postacc_code = ''): 1592315SN/A addrCalcReg = 'EA = Rs1;' 1602680SN/A iop = InstObjParams(name, Name, 'Mem', 1612315SN/A {"code": code, "postacc_code" : postacc_code, 1622680SN/A "fault_check": faultCode, "ea_code": addrCalcReg, 1632680SN/A "EA_trunc" : TruncateEA}, opt_flags) 1642315SN/A header_output = MemDeclare.subst(iop) 1652315SN/A decoder_output = BasicConstructor.subst(iop) 1662315SN/A decode_block = BasicDecode.subst(iop) 1672315SN/A microParams = {"code": code, "postacc_code" : postacc_code, 1682680SN/A "ea_code" : addrCalcReg, "fault_check" : faultCode, 1692680SN/A "EA_trunc" : TruncateEA} 1702315SN/A exec_output = doSplitExecute(execute, name, Name, asi, 1712315SN/A ["IsStoreConditional"], microParams); 1722315SN/A return (header_output, decoder_output, exec_output, decode_block) 1732315SN/A}}; 1742315SN/A 1752315SN/A 1762680SN/Adef format CasAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{ 1772315SN/A mem_flags = makeList(mem_flags) 1782669SN/A mem_flags.append(asi) 1792680SN/A flags = string.join(mem_flags, '|') 1802315SN/A (header_output, 1812669SN/A decoder_output, 1822680SN/A exec_output, 1832315SN/A decode_block) = doCasFormat(code, SwapFuncs, AlternateASIPrivFaultCheck, 1842669SN/A name, Name, flags, ["IsStoreConditional"], postacc_code) 1852680SN/A}}; 1862669SN/A 1872669SN/A 1882680SN/A