mem.isa revision 2516 
1////////////////////////////////////////////////////////////////////
2//
3// Mem instructions
4//
5
6output header {{
7        /**
8         * Base class for memory operations.
9         */
10        class Mem : public SparcStaticInst
11        {
12          protected:
13
14            // Constructor
15            Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
16                SparcStaticInst(mnem, _machInst, __opClass)
17            {
18            }
19
20            std::string generateDisassembly(Addr pc,
21                    const SymbolTable *symtab) const;
22        };
23
24        /**
25         * Class for memory operations which use an immediate offset.
26         */
27        class MemImm : public Mem
28        {
29          protected:
30
31            // Constructor
32            MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
33                Mem(mnem, _machInst, __opClass), imm(SIMM13)
34            {
35            }
36
37            std::string generateDisassembly(Addr pc,
38                    const SymbolTable *symtab) const;
39
40            int imm;
41        };
42}};
43
44output decoder {{
45        std::string Mem::generateDisassembly(Addr pc,
46                const SymbolTable *symtab) const
47        {
48            std::stringstream response;
49            bool load = (_numDestRegs == 1);
50
51            printMnemonic(response, mnemonic);
52            if(!load)
53            {
54                printReg(response, _srcRegIdx[0]);
55                ccprintf(response, ", ");
56            }
57            ccprintf(response, "[ ");
58            printReg(response, _srcRegIdx[load ? 0 : 1]);
59            ccprintf(response, " + ");
60            printReg(response, _srcRegIdx[load ? 1 : 2]);
61            ccprintf(response, " ]");
62            if(load)
63            {
64                ccprintf(response, ", ");
65                printReg(response, _destRegIdx[0]);
66            }
67
68            return response.str();
69        }
70
71        std::string MemImm::generateDisassembly(Addr pc,
72                const SymbolTable *symtab) const
73        {
74            std::stringstream response;
75            bool load = (_numDestRegs == 1);
76
77            printMnemonic(response, mnemonic);
78            if(!load)
79            {
80                printReg(response, _srcRegIdx[0]);
81                ccprintf(response, ", ");
82            }
83            ccprintf(response, "[ ");
84            printReg(response, _srcRegIdx[load ? 0 : 1]);
85            ccprintf(response, " + 0x%x ]", imm);
86            if(load)
87            {
88                ccprintf(response, ", ");
89                printReg(response, _destRegIdx[0]);
90            }
91
92            return response.str();
93        }
94}};
95
96def template MemExecute {{
97        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
98                Trace::InstRecord *traceData) const
99        {
100            Fault fault = NoFault;
101            Addr EA;
102            %(op_decl)s;
103            %(op_rd)s;
104            %(ea_code)s;
105            %(code)s;
106
107            if(fault == NoFault)
108            {
109                //Write the resulting state to the execution context
110                %(op_wb)s;
111            }
112
113            return fault;
114        }
115}};
116
117// Primary format for memory instructions:
118def format Mem(code, *opt_flags) {{
119        addrCalcReg = 'EA = Rs1 + Rs2;'
120        addrCalcImm = 'EA = Rs1 + SIMM13;'
121        iop = genCompositeIop(code, name, Name, 'Mem',
122                opt_flags, ea_code=addrCalcReg)
123        iop_imm = genCompositeIop(code, name, Name + 'Imm', 'MemImm',
124                opt_flags, ea_code=addrCalcImm)
125        header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
126        decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
127        decode_block = ROrImmDecode.subst(iop)
128        exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
129}};
130