blockmem.isa revision 3388:1c6ebfc4c20e 
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28//          Gabe Black
29
30////////////////////////////////////////////////////////////////////
31//
32// Block Memory instructions
33//
34
35output header {{
36
37        class BlockMem : public SparcMacroInst
38        {
39          protected:
40
41            // Constructor
42            // We make the assumption that all block memory operations
43            // Will take 8 instructions to execute
44            BlockMem(const char *mnem, ExtMachInst _machInst) :
45                SparcMacroInst(mnem, _machInst, No_OpClass, 8)
46            {}
47        };
48
49        class BlockMemImm : public BlockMem
50        {
51          protected:
52
53            // Constructor
54            BlockMemImm(const char *mnem, ExtMachInst _machInst) :
55                BlockMem(mnem, _machInst)
56            {}
57        };
58
59        class BlockMemMicro : public SparcDelayedMicroInst
60        {
61          protected:
62
63            // Constructor
64            BlockMemMicro(const char *mnem, ExtMachInst _machInst,
65                    OpClass __opClass, int8_t _offset) :
66                SparcDelayedMicroInst(mnem, _machInst, __opClass),
67                offset(_offset)
68            {}
69
70            std::string generateDisassembly(Addr pc,
71                const SymbolTable *symtab) const;
72
73            const int8_t offset;
74        };
75
76        class BlockMemImmMicro : public BlockMemMicro
77        {
78          protected:
79
80            // Constructor
81            BlockMemImmMicro(const char *mnem, ExtMachInst _machInst,
82                    OpClass __opClass, int8_t _offset) :
83                BlockMemMicro(mnem, _machInst, __opClass, _offset),
84                imm(sext<13>(SIMM13))
85            {}
86
87            std::string generateDisassembly(Addr pc,
88                const SymbolTable *symtab) const;
89
90            const int32_t imm;
91        };
92}};
93
94output decoder {{
95        std::string BlockMemMicro::generateDisassembly(Addr pc,
96                const SymbolTable *symtab) const
97        {
98            std::stringstream response;
99            bool load = flags[IsLoad];
100            bool save = flags[IsStore];
101
102            printMnemonic(response, mnemonic);
103            if(save)
104            {
105                printReg(response, _srcRegIdx[0]);
106                ccprintf(response, ", ");
107            }
108            ccprintf(response, "[ ");
109            printReg(response, _srcRegIdx[!save ? 0 : 1]);
110            ccprintf(response, " + ");
111            printReg(response, _srcRegIdx[!save ? 1 : 2]);
112            ccprintf(response, " ]");
113            if(load)
114            {
115                ccprintf(response, ", ");
116                printReg(response, _destRegIdx[0]);
117            }
118
119            return response.str();
120        }
121
122        std::string BlockMemImmMicro::generateDisassembly(Addr pc,
123                const SymbolTable *symtab) const
124        {
125            std::stringstream response;
126            bool load = flags[IsLoad];
127            bool save = flags[IsStore];
128
129            printMnemonic(response, mnemonic);
130            if(save)
131            {
132                printReg(response, _srcRegIdx[1]);
133                ccprintf(response, ", ");
134            }
135            ccprintf(response, "[ ");
136            printReg(response, _srcRegIdx[0]);
137            if(imm >= 0)
138                ccprintf(response, " + 0x%x ]", imm);
139            else
140                ccprintf(response, " + -0x%x ]", -imm);
141            if(load)
142            {
143                ccprintf(response, ", ");
144                printReg(response, _destRegIdx[0]);
145            }
146
147            return response.str();
148        }
149
150}};
151
152def template BlockMemDeclare {{
153        /**
154         * Static instruction class for a block memory operation
155         */
156        class %(class_name)s : public %(base_class)s
157        {
158          public:
159            //Constructor
160            %(class_name)s(ExtMachInst machInst);
161
162          protected:
163            class %(class_name)s_0 : public %(base_class)sMicro
164            {
165              public:
166                //Constructor
167                %(class_name)s_0(ExtMachInst machInst);
168                %(BasicExecDeclare)s
169            };
170
171            class %(class_name)s_1 : public %(base_class)sMicro
172            {
173              public:
174                //Constructor
175                %(class_name)s_1(ExtMachInst machInst);
176                %(BasicExecDeclare)s
177            };
178
179            class %(class_name)s_2 : public %(base_class)sMicro
180            {
181              public:
182                //Constructor
183                %(class_name)s_2(ExtMachInst machInst);
184                %(BasicExecDeclare)s
185            };
186
187            class %(class_name)s_3 : public %(base_class)sMicro
188            {
189              public:
190                //Constructor
191                %(class_name)s_3(ExtMachInst machInst);
192                %(BasicExecDeclare)s
193            };
194
195            class %(class_name)s_4 : public %(base_class)sMicro
196            {
197              public:
198                //Constructor
199                %(class_name)s_4(ExtMachInst machInst);
200                %(BasicExecDeclare)s
201            };
202
203            class %(class_name)s_5 : public %(base_class)sMicro
204            {
205              public:
206                //Constructor
207                %(class_name)s_5(ExtMachInst machInst);
208                %(BasicExecDeclare)s
209            };
210
211            class %(class_name)s_6 : public %(base_class)sMicro
212            {
213              public:
214                //Constructor
215                %(class_name)s_6(ExtMachInst machInst);
216                %(BasicExecDeclare)s
217            };
218
219            class %(class_name)s_7 : public %(base_class)sMicro
220            {
221              public:
222                //Constructor
223                %(class_name)s_7(ExtMachInst machInst);
224                %(BasicExecDeclare)s
225            };
226        };
227}};
228
229// Basic instruction class constructor template.
230def template BlockMemConstructor {{
231        inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
232            : %(base_class)s("%(mnemonic)s", machInst)
233        {
234            %(constructor)s;
235            microOps[0] = new %(class_name)s_0(machInst);
236            microOps[1] = new %(class_name)s_1(machInst);
237            microOps[2] = new %(class_name)s_2(machInst);
238            microOps[3] = new %(class_name)s_3(machInst);
239            microOps[4] = new %(class_name)s_4(machInst);
240            microOps[5] = new %(class_name)s_5(machInst);
241            microOps[6] = new %(class_name)s_6(machInst);
242            microOps[7] = new %(class_name)s_7(machInst);
243        }
244}};
245
246def template BlockMemMicroConstructor {{
247        inline %(class_name)s::
248            %(class_name)s_%(micro_pc)s::
249            %(class_name)s_%(micro_pc)s(ExtMachInst machInst) :
250                %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]",
251                        machInst, %(op_class)s, %(micro_pc)s * 8)
252    {
253        %(constructor)s;
254        %(set_flags)s;
255    }
256}};
257
258def template MicroLoadExecute {{
259        Fault %(class_name)s::%(class_name)s_%(micro_pc)s::execute(
260                %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
261        {
262            Fault fault = NoFault;
263            Addr EA;
264            %(op_decl)s;
265            %(op_rd)s;
266            %(ea_code)s;
267            %(fault_check)s;
268            DPRINTF(Sparc, "The address is 0x%x\n", EA);
269            xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
270            %(code)s;
271
272            if(fault == NoFault)
273            {
274                //Write the resulting state to the execution context
275                %(op_wb)s;
276            }
277
278            return fault;
279        }
280}};
281
282def template MicroStoreExecute {{
283        Fault %(class_name)s::%(class_name)s_%(micro_pc)s::execute(
284                %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
285        {
286            Fault fault = NoFault;
287            uint64_t write_result = 0;
288            Addr EA;
289            %(op_decl)s;
290            %(op_rd)s;
291            %(ea_code)s;
292            %(fault_check)s;
293            DPRINTF(Sparc, "The address is 0x%x\n", EA);
294            %(code)s;
295
296            if(fault == NoFault)
297            {
298                xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
299                //Write the resulting state to the execution context
300                %(op_wb)s;
301            }
302
303            return fault;
304        }
305}};
306
307let {{
308
309    def doBlockMemFormat(code, execute, name, Name, opt_flags):
310        # XXX Need to take care of pstate.hpriv as well. The lower ASIs
311        # are split into ones that are available in priv and hpriv, and
312        # those that are only available in hpriv
313        faultCheck = '''if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0)
314                    return new PrivilegedAction;
315                if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
316                    return new PrivilegedAction;
317                //The LSB can be zero, since it's really the MSB in doubles
318                //and quads
319                if(RD & 0xe)
320                    return new IllegalInstruction;
321                if(EA & 0x3f)
322                    return new MemAddressNotAligned;
323                '''
324        addrCalcReg = 'EA = Rs1 + Rs2 + offset;'
325        addrCalcImm = 'EA = Rs1 + imm + offset;'
326        iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags)
327        iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags)
328        header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm)
329        decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm)
330        decode_block = ROrImmDecode.subst(iop)
331        matcher = re.compile(r'Frd_N')
332        exec_output = ''
333        for microPC in range(8):
334            flag_code = ''
335            if (microPC == 7):
336                flag_code = "flags[IsLastMicroOp] = true;"
337            pcedCode = matcher.sub("Frd_%d" % microPC, code)
338            iop = InstObjParams(name, Name, 'BlockMem', pcedCode,
339                    opt_flags, {"ea_code": addrCalcReg,
340                    "fault_check": faultCheck, "micro_pc": microPC,
341                    "set_flags": flag_code})
342            iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', pcedCode,
343                    opt_flags, {"ea_code": addrCalcImm,
344                    "fault_check": faultCheck, "micro_pc": microPC,
345                    "set_flags": flag_code})
346            exec_output += execute.subst(iop)
347            exec_output += execute.subst(iop_imm)
348            decoder_output += BlockMemMicroConstructor.subst(iop)
349            decoder_output += BlockMemMicroConstructor.subst(iop_imm)
350            faultCheck = ''
351        return (header_output, decoder_output, exec_output, decode_block)
352}};
353
354def format BlockLoad(code, *opt_flags) {{
355        (header_output,
356         decoder_output,
357         exec_output,
358         decode_block) = doBlockMemFormat(code, MicroLoadExecute,
359             name, Name, opt_flags)
360}};
361
362def format BlockStore(code, *opt_flags) {{
363        (header_output,
364         decoder_output,
365         exec_output,
366         decode_block) = doBlockMemFormat(code, MicroStoreExecute,
367            name, Name, opt_flags)
368}};
369