blockmem.isa revision 12236:126ac9da6050
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29 30//////////////////////////////////////////////////////////////////// 31// 32// Block Memory instructions 33// 34 35output header {{ 36 37 class BlockMem : public SparcMacroInst 38 { 39 protected: 40 41 // Constructor 42 // We make the assumption that all block memory operations 43 // Will take 8 instructions to execute 44 BlockMem(const char *mnem, ExtMachInst _machInst) : 45 SparcMacroInst(mnem, _machInst, No_OpClass, 8) 46 {} 47 }; 48 49 class BlockMemImm : public BlockMem 50 { 51 protected: 52 53 // Constructor 54 BlockMemImm(const char *mnem, ExtMachInst _machInst) : 55 BlockMem(mnem, _machInst) 56 {} 57 }; 58 59 class BlockMemMicro : public SparcMicroInst 60 { 61 protected: 62 63 // Constructor 64 BlockMemMicro(const char *mnem, ExtMachInst _machInst, 65 OpClass __opClass, int8_t _offset) : 66 SparcMicroInst(mnem, _machInst, __opClass), 67 offset(_offset) 68 {} 69 70 std::string generateDisassembly(Addr pc, 71 const SymbolTable *symtab) const; 72 73 const int8_t offset; 74 }; 75 76 class BlockMemImmMicro : public BlockMemMicro 77 { 78 protected: 79 80 // Constructor 81 BlockMemImmMicro(const char *mnem, ExtMachInst _machInst, 82 OpClass __opClass, int8_t _offset) : 83 BlockMemMicro(mnem, _machInst, __opClass, _offset), 84 imm(sext<13>(SIMM13)) 85 {} 86 87 std::string generateDisassembly(Addr pc, 88 const SymbolTable *symtab) const; 89 90 const int32_t imm; 91 }; 92}}; 93 94output decoder {{ 95 std::string BlockMemMicro::generateDisassembly(Addr pc, 96 const SymbolTable *symtab) const 97 { 98 std::stringstream response; 99 bool load = flags[IsLoad]; 100 bool save = flags[IsStore]; 101 102 printMnemonic(response, mnemonic); 103 if (save) { 104 printReg(response, _srcRegIdx[0]); 105 ccprintf(response, ", "); 106 } 107 ccprintf(response, "[ "); 108 printReg(response, _srcRegIdx[!save ? 0 : 1]); 109 ccprintf(response, " + "); 110 printReg(response, _srcRegIdx[!save ? 1 : 2]); 111 ccprintf(response, " ]"); 112 if (load) { 113 ccprintf(response, ", "); 114 printReg(response, _destRegIdx[0]); 115 } 116 117 return response.str(); 118 } 119 120 std::string BlockMemImmMicro::generateDisassembly(Addr pc, 121 const SymbolTable *symtab) const 122 { 123 std::stringstream response; 124 bool load = flags[IsLoad]; 125 bool save = flags[IsStore]; 126 127 printMnemonic(response, mnemonic); 128 if (save) { 129 printReg(response, _srcRegIdx[1]); 130 ccprintf(response, ", "); 131 } 132 ccprintf(response, "[ "); 133 printReg(response, _srcRegIdx[0]); 134 if (imm >= 0) 135 ccprintf(response, " + 0x%x ]", imm); 136 else 137 ccprintf(response, " + -0x%x ]", -imm); 138 if (load) { 139 ccprintf(response, ", "); 140 printReg(response, _destRegIdx[0]); 141 } 142 143 return response.str(); 144 } 145 146}}; 147 148def template BlockMemDeclare {{ 149 /** 150 * Static instruction class for a block memory operation 151 */ 152 class %(class_name)s : public %(base_class)s 153 { 154 public: 155 // Constructor 156 %(class_name)s(ExtMachInst machInst); 157 158 protected: 159 class %(class_name)s_0 : public %(base_class)sMicro 160 { 161 public: 162 // Constructor 163 %(class_name)s_0(ExtMachInst machInst); 164 Fault execute(ExecContext *, Trace::InstRecord *) const; 165 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 166 Fault completeAcc(PacketPtr, ExecContext *, 167 Trace::InstRecord *) const; 168 }; 169 170 class %(class_name)s_1 : public %(base_class)sMicro 171 { 172 public: 173 // Constructor 174 %(class_name)s_1(ExtMachInst machInst); 175 Fault execute(ExecContext *, Trace::InstRecord *) const; 176 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 177 Fault completeAcc(PacketPtr, ExecContext *, 178 Trace::InstRecord *) const; 179 }; 180 181 class %(class_name)s_2 : public %(base_class)sMicro 182 { 183 public: 184 // Constructor 185 %(class_name)s_2(ExtMachInst machInst); 186 Fault execute(ExecContext *, Trace::InstRecord *) const; 187 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 188 Fault completeAcc(PacketPtr, ExecContext *, 189 Trace::InstRecord *) const; 190 }; 191 192 class %(class_name)s_3 : public %(base_class)sMicro 193 { 194 public: 195 // Constructor 196 %(class_name)s_3(ExtMachInst machInst); 197 Fault execute(ExecContext *, Trace::InstRecord *) const; 198 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 199 Fault completeAcc(PacketPtr, ExecContext *, 200 Trace::InstRecord *) const; 201 }; 202 203 class %(class_name)s_4 : public %(base_class)sMicro 204 { 205 public: 206 // Constructor 207 %(class_name)s_4(ExtMachInst machInst); 208 Fault execute(ExecContext *, Trace::InstRecord *) const; 209 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 210 Fault completeAcc(PacketPtr, ExecContext *, 211 Trace::InstRecord *) const; 212 }; 213 214 class %(class_name)s_5 : public %(base_class)sMicro 215 { 216 public: 217 // Constructor 218 %(class_name)s_5(ExtMachInst machInst); 219 Fault execute(ExecContext *, Trace::InstRecord *) const; 220 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 221 Fault completeAcc(PacketPtr, ExecContext *, 222 Trace::InstRecord *) const; 223 }; 224 225 class %(class_name)s_6 : public %(base_class)sMicro 226 { 227 public: 228 // Constructor 229 %(class_name)s_6(ExtMachInst machInst); 230 Fault execute(ExecContext *, Trace::InstRecord *) const; 231 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 232 Fault completeAcc(PacketPtr, ExecContext *, 233 Trace::InstRecord *) const; 234 }; 235 236 class %(class_name)s_7 : public %(base_class)sMicro 237 { 238 public: 239 // Constructor 240 %(class_name)s_7(ExtMachInst machInst); 241 Fault execute(ExecContext *, Trace::InstRecord *) const; 242 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 243 Fault completeAcc(PacketPtr, ExecContext *, 244 Trace::InstRecord *) const; 245 }; 246 }; 247}}; 248 249// Basic instruction class constructor template. 250def template BlockMemConstructor {{ 251 %(class_name)s::%(class_name)s(ExtMachInst machInst) 252 : %(base_class)s("%(mnemonic)s", machInst) 253 { 254 %(constructor)s; 255 microops[0] = new %(class_name)s_0(machInst); 256 microops[1] = new %(class_name)s_1(machInst); 257 microops[2] = new %(class_name)s_2(machInst); 258 microops[3] = new %(class_name)s_3(machInst); 259 microops[4] = new %(class_name)s_4(machInst); 260 microops[5] = new %(class_name)s_5(machInst); 261 microops[6] = new %(class_name)s_6(machInst); 262 microops[7] = new %(class_name)s_7(machInst); 263 } 264}}; 265 266def template BlockMemMicroConstructor {{ 267 %(class_name)s:: 268 %(class_name)s_%(micro_pc)s:: 269 %(class_name)s_%(micro_pc)s(ExtMachInst machInst) : 270 %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]", 271 machInst, %(op_class)s, %(micro_pc)s * 8) 272 { 273 %(constructor)s; 274 %(set_flags)s; 275 } 276}}; 277 278let {{ 279 280 def doBlockMemFormat(code, faultCode, execute, name, Name, opt_flags): 281 # XXX Need to take care of pstate.hpriv as well. The lower ASIs 282 # are split into ones that are available in priv and hpriv, and 283 # those that are only available in hpriv 284 addrCalcReg = 'EA = Rs1 + Rs2 + offset;' 285 addrCalcImm = 'EA = Rs1 + imm + offset;' 286 iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags) 287 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags) 288 header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm) 289 decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm) 290 decode_block = ROrImmDecode.subst(iop) 291 matcher = re.compile(r'Frd_N') 292 exec_output = '' 293 for microPc in range(8): 294 flag_code = '' 295 if (microPc == 7): 296 flag_code = "flags[IsLastMicroop] = true;" 297 elif (microPc == 0): 298 flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroop] = true;" 299 else: 300 flag_code = "flags[IsDelayedCommit] = true;" 301 pcedCode = matcher.sub("Frd_%d" % microPc, code) 302 iop = InstObjParams(name, Name, 'BlockMem', 303 {"code": pcedCode, "ea_code": addrCalcReg, 304 "fault_check": faultCode, "micro_pc": microPc, 305 "set_flags": flag_code, "EA_trunc" : TruncateEA}, 306 opt_flags) 307 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', 308 {"code": pcedCode, "ea_code": addrCalcImm, 309 "fault_check": faultCode, "micro_pc": microPc, 310 "set_flags": flag_code, "EA_trunc" : TruncateEA}, 311 opt_flags) 312 decoder_output += BlockMemMicroConstructor.subst(iop) 313 decoder_output += BlockMemMicroConstructor.subst(iop_imm) 314 exec_output += doDualSplitExecute( 315 pcedCode, '', addrCalcReg, addrCalcImm, execute, faultCode, 316 makeMicroName(name, microPc), 317 makeMicroName(name + "Imm", microPc), 318 makeMicroName(Name, microPc), 319 makeMicroName(Name + "Imm", microPc), 320 "EXT_ASI", opt_flags); 321 faultCode = '' 322 return (header_output, decoder_output, exec_output, decode_block) 323}}; 324 325def format BlockLoad(code, *opt_flags) {{ 326 code = filterDoubles(code) 327 # We need to make sure to check the highest priority fault last. 328 # That way, if other faults have been detected, they'll be overwritten 329 # rather than the other way around. 330 faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck 331 (header_output, 332 decoder_output, 333 exec_output, 334 decode_block) = doBlockMemFormat(code, faultCode, 335 LoadFuncs, name, Name, opt_flags) 336}}; 337 338def format BlockStore(code, *opt_flags) {{ 339 code = filterDoubles(code) 340 # We need to make sure to check the highest priority fault last. 341 # That way, if other faults have been detected, they'll be overwritten 342 # rather than the other way around. 343 faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck 344 (header_output, 345 decoder_output, 346 exec_output, 347 decode_block) = doBlockMemFormat(code, faultCode, 348 StoreFuncs, name, Name, opt_flags) 349}}; 350