decoder.isa revision 4828:768d4cf6b0dc
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 //Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 format BranchN 43 { 44 //bpcc 45 0x1: decode COND2 46 { 47 //Branch Always 48 0x8: decode A 49 { 50 0x0: bpa(19, {{ 51 NNPC = xc->readPC() + disp; 52 }}); 53 0x1: bpa(19, {{ 54 NPC = xc->readPC() + disp; 55 NNPC = NPC + 4; 56 }}, ',a'); 57 } 58 //Branch Never 59 0x0: decode A 60 { 61 0x0: bpn(19, {{ 62 NNPC = NNPC;//Don't do anything 63 }}); 64 0x1: bpn(19, {{ 65 NNPC = NPC + 8; 66 NPC = NPC + 4; 67 }}, ',a'); 68 } 69 default: decode BPCC 70 { 71 0x0: bpcci(19, {{ 72 if(passesCondition(Ccr<3:0>, COND2)) 73 NNPC = xc->readPC() + disp; 74 else 75 handle_annul 76 }}); 77 0x2: bpccx(19, {{ 78 if(passesCondition(Ccr<7:4>, COND2)) 79 NNPC = xc->readPC() + disp; 80 else 81 handle_annul 82 }}); 83 } 84 } 85 //bicc 86 0x2: decode COND2 87 { 88 //Branch Always 89 0x8: decode A 90 { 91 0x0: ba(22, {{ 92 NNPC = xc->readPC() + disp; 93 }}); 94 0x1: ba(22, {{ 95 NPC = xc->readPC() + disp; 96 NNPC = NPC + 4; 97 }}, ',a'); 98 } 99 //Branch Never 100 0x0: decode A 101 { 102 0x0: bn(22, {{ 103 NNPC = NNPC;//Don't do anything 104 }}); 105 0x1: bn(22, {{ 106 NNPC = NPC + 8; 107 NPC = NPC + 4; 108 }}, ',a'); 109 } 110 default: bicc(22, {{ 111 if(passesCondition(Ccr<3:0>, COND2)) 112 NNPC = xc->readPC() + disp; 113 else 114 handle_annul 115 }}); 116 } 117 } 118 0x3: decode RCOND2 119 { 120 format BranchSplit 121 { 122 0x1: bpreq({{ 123 if(Rs1.sdw == 0) 124 NNPC = xc->readPC() + disp; 125 else 126 handle_annul 127 }}); 128 0x2: bprle({{ 129 if(Rs1.sdw <= 0) 130 NNPC = xc->readPC() + disp; 131 else 132 handle_annul 133 }}); 134 0x3: bprl({{ 135 if(Rs1.sdw < 0) 136 NNPC = xc->readPC() + disp; 137 else 138 handle_annul 139 }}); 140 0x5: bprne({{ 141 if(Rs1.sdw != 0) 142 NNPC = xc->readPC() + disp; 143 else 144 handle_annul 145 }}); 146 0x6: bprg({{ 147 if(Rs1.sdw > 0) 148 NNPC = xc->readPC() + disp; 149 else 150 handle_annul 151 }}); 152 0x7: bprge({{ 153 if(Rs1.sdw >= 0) 154 NNPC = xc->readPC() + disp; 155 else 156 handle_annul 157 }}); 158 } 159 } 160 //SETHI (or NOP if rd == 0 and imm == 0) 161 0x4: SetHi::sethi({{Rd.udw = imm;}}); 162 //fbpfcc 163 0x5: decode COND2 { 164 format BranchN { 165 //Branch Always 166 0x8: decode A 167 { 168 0x0: fbpa(22, {{ 169 NNPC = xc->readPC() + disp; 170 }}); 171 0x1: fbpa(22, {{ 172 NPC = xc->readPC() + disp; 173 NNPC = NPC + 4; 174 }}, ',a'); 175 } 176 //Branch Never 177 0x0: decode A 178 { 179 0x0: fbpn(22, {{ 180 NNPC = NNPC;//Don't do anything 181 }}); 182 0x1: fbpn(22, {{ 183 NNPC = NPC + 8; 184 NPC = NPC + 4; 185 }}, ',a'); 186 } 187 default: decode BPCC { 188 0x0: fbpfcc0(19, {{ 189 if(passesFpCondition(Fsr<11:10>, COND2)) 190 NNPC = xc->readPC() + disp; 191 else 192 handle_annul 193 }}); 194 0x1: fbpfcc1(19, {{ 195 if(passesFpCondition(Fsr<33:32>, COND2)) 196 NNPC = xc->readPC() + disp; 197 else 198 handle_annul 199 }}); 200 0x2: fbpfcc2(19, {{ 201 if(passesFpCondition(Fsr<35:34>, COND2)) 202 NNPC = xc->readPC() + disp; 203 else 204 handle_annul 205 }}); 206 0x3: fbpfcc3(19, {{ 207 if(passesFpCondition(Fsr<37:36>, COND2)) 208 NNPC = xc->readPC() + disp; 209 else 210 handle_annul 211 }}); 212 } 213 } 214 } 215 //fbfcc 216 0x6: decode COND2 { 217 format BranchN { 218 //Branch Always 219 0x8: decode A 220 { 221 0x0: fba(22, {{ 222 NNPC = xc->readPC() + disp; 223 }}); 224 0x1: fba(22, {{ 225 NPC = xc->readPC() + disp; 226 NNPC = NPC + 4; 227 }}, ',a'); 228 } 229 //Branch Never 230 0x0: decode A 231 { 232 0x0: fbn(22, {{ 233 NNPC = NNPC;//Don't do anything 234 }}); 235 0x1: fbn(22, {{ 236 NNPC = NPC + 8; 237 NPC = NPC + 4; 238 }}, ',a'); 239 } 240 default: fbfcc(22, {{ 241 if(passesFpCondition(Fsr<11:10>, COND2)) 242 NNPC = xc->readPC() + disp; 243 else 244 handle_annul 245 }}); 246 } 247 } 248 } 249 0x1: BranchN::call(30, {{ 250 if (Pstate<3:>) 251 R15 = (xc->readPC())<31:0>; 252 else 253 R15 = xc->readPC(); 254 NNPC = R15 + disp; 255 }}); 256 0x2: decode OP3 { 257 format IntOp { 258 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 259 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 260 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 261 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 262 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 263 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 264 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 265 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 266 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 267 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 268 0x0A: umul({{ 269 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 270 Y = Rd<63:32>; 271 }}); 272 0x0B: smul({{ 273 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 274 Y = Rd.sdw<63:32>; 275 }}); 276 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 277 0x0D: udivx({{ 278 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 279 else Rd.udw = Rs1.udw / Rs2_or_imm13; 280 }}); 281 0x0E: udiv({{ 282 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 283 else 284 { 285 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 286 if(Rd.udw >> 32 != 0) 287 Rd.udw = 0xFFFFFFFF; 288 } 289 }}); 290 0x0F: sdiv({{ 291 if(Rs2_or_imm13.sdw == 0) 292 fault = new DivisionByZero; 293 else 294 { 295 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 296 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) 297 Rd.udw = 0x7FFFFFFF; 298 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 299 Rd.udw = ULL(0xFFFFFFFF80000000); 300 } 301 }}); 302 } 303 format IntOpCc { 304 0x10: addcc({{ 305 int64_t resTemp, val2 = Rs2_or_imm13; 306 Rd = resTemp = Rs1 + val2;}}, 307 {{(Rs1<31:0> + val2<31:0>)<32:>}}, 308 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 309 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 310 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 311 ); 312 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 313 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 314 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 315 0x14: subcc({{ 316 int64_t val2 = Rs2_or_imm13; 317 Rd = Rs1 - val2;}}, 318 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 319 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 320 {{(~(Rs1<63:1> + (~val2)<63:1> + 321 (Rs1 | ~val2)<0:>))<63:>}}, 322 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 323 ); 324 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 325 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 326 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 327 0x18: addccc({{ 328 int64_t resTemp, val2 = Rs2_or_imm13; 329 int64_t carryin = Ccr<0:0>; 330 Rd = resTemp = Rs1 + val2 + carryin;}}, 331 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 332 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 333 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}}, 334 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 335 ); 336 0x1A: IntOpCcRes::umulcc({{ 337 uint64_t resTemp; 338 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 339 Y = resTemp<63:32>;}}); 340 0x1B: IntOpCcRes::smulcc({{ 341 int64_t resTemp; 342 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 343 Y = resTemp<63:32>;}}); 344 0x1C: subccc({{ 345 int64_t resTemp, val2 = Rs2_or_imm13; 346 int64_t carryin = Ccr<0:0>; 347 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 348 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}}, 349 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 350 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}}, 351 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 352 ); 353 0x1D: IntOpCcRes::udivxcc({{ 354 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 355 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 356 0x1E: udivcc({{ 357 uint32_t resTemp, val2 = Rs2_or_imm13.udw; 358 int32_t overflow = 0; 359 if(val2 == 0) fault = new DivisionByZero; 360 else 361 { 362 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 363 overflow = (resTemp<63:32> != 0); 364 if(overflow) Rd = resTemp = 0xFFFFFFFF; 365 else Rd = resTemp; 366 } }}, 367 {{0}}, 368 {{overflow}}, 369 {{0}}, 370 {{0}} 371 ); 372 0x1F: sdivcc({{ 373 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 374 bool overflow = false, underflow = false; 375 if(val2 == 0) fault = new DivisionByZero; 376 else 377 { 378 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 379 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 380 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 381 if(overflow) Rd = 0x7FFFFFFF; 382 else if(underflow) Rd = ULL(0xFFFFFFFF80000000); 383 } }}, 384 {{0}}, 385 {{overflow || underflow}}, 386 {{0}}, 387 {{0}} 388 ); 389 0x20: taddcc({{ 390 int64_t resTemp, val2 = Rs2_or_imm13; 391 Rd = resTemp = Rs1 + val2; 392 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 393 {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 394 {{overflow}}, 395 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 396 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 397 ); 398 0x21: tsubcc({{ 399 int64_t resTemp, val2 = Rs2_or_imm13; 400 Rd = resTemp = Rs1 + val2; 401 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 402 {{(Rs1<31:0> + val2<31:0>)<32:0>}}, 403 {{overflow}}, 404 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 405 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 406 ); 407 0x22: taddcctv({{ 408 int64_t val2 = Rs2_or_imm13; 409 Rd = Rs1 + val2; 410 int32_t overflow = Rs1<1:0> || val2<1:0> || 411 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 412 if(overflow) fault = new TagOverflow;}}, 413 {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 414 {{overflow}}, 415 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 416 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} 417 ); 418 0x23: tsubcctv({{ 419 int64_t resTemp, val2 = Rs2_or_imm13; 420 Rd = resTemp = Rs1 + val2; 421 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 422 if(overflow) fault = new TagOverflow;}}, 423 {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 424 {{overflow}}, 425 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 426 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 427 ); 428 0x24: mulscc({{ 429 int32_t savedLSB = Rs1<0:>; 430 431 //Step 1 432 int64_t multiplicand = Rs2_or_imm13; 433 //Step 2 434 int32_t partialP = Rs1<31:1> | 435 ((Ccr<3:3> ^ Ccr<1:1>) << 31); 436 //Step 3 437 int32_t added = Y<0:> ? multiplicand : 0; 438 Rd = partialP + added; 439 //Steps 4 & 5 440 Y = Y<31:1> | (savedLSB << 31);}}, 441 {{((partialP<31:0> + added<31:0>)<32:0>)}}, 442 {{partialP<31:> == added<31:> && added<31:> != Rd<31:>}}, 443 {{((partialP >> 1) + (added >> 1) + (partialP & added & 0x1))<63:>}}, 444 {{partialP<63:> == added<63:> && partialP<63:> != Rd<63:>}} 445 ); 446 } 447 format IntOp 448 { 449 0x25: decode X { 450 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 451 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 452 } 453 0x26: decode X { 454 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 455 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 456 } 457 0x27: decode X { 458 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 459 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 460 } 461 0x28: decode RS1 { 462 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 463 //1 should cause an illegal instruction exception 464 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 465 0x03: NoPriv::rdasi({{Rd = Asi;}}); 466 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 467 0x05: NoPriv::rdpc({{ 468 if(Pstate<3:>) 469 Rd = (xc->readPC())<31:0>; 470 else 471 Rd = xc->readPC();}}); 472 0x06: NoPriv::rdfprs({{ 473 //Wait for all fpops to finish. 474 Rd = Fprs; 475 }}); 476 //7-14 should cause an illegal instruction exception 477 0x0F: decode I { 478 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 479 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 480 } 481 0x10: Priv::rdpcr({{Rd = Pcr;}}); 482 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 483 //0x12 should cause an illegal instruction exception 484 0x13: NoPriv::rdgsr({{ 485 fault = checkFpEnableFault(xc); 486 if (fault) 487 return fault; 488 Rd = Gsr; 489 }}); 490 //0x14-0x15 should cause an illegal instruction exception 491 0x16: Priv::rdsoftint({{Rd = Softint;}}); 492 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 493 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 494 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 495 0x1A: Priv::rdstrand_sts_reg({{ 496 if(Pstate<2:> && !Hpstate<2:>) 497 Rd = StrandStsReg<0:>; 498 else 499 Rd = StrandStsReg; 500 }}); 501 //0x1A is supposed to be reserved, but it reads the strand 502 //status register. 503 //0x1B-0x1F should cause an illegal instruction exception 504 } 505 0x29: decode RS1 { 506 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 507 0x01: HPriv::rdhprhtstate({{ 508 if(Tl == 0) 509 return new IllegalInstruction; 510 Rd = Htstate; 511 }}); 512 //0x02 should cause an illegal instruction exception 513 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 514 //0x04 should cause an illegal instruction exception 515 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 516 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 517 //0x07-0x1E should cause an illegal instruction exception 518 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 519 } 520 0x2A: decode RS1 { 521 0x00: Priv::rdprtpc({{ 522 if(Tl == 0) 523 return new IllegalInstruction; 524 Rd = Tpc; 525 }}); 526 0x01: Priv::rdprtnpc({{ 527 if(Tl == 0) 528 return new IllegalInstruction; 529 Rd = Tnpc; 530 }}); 531 0x02: Priv::rdprtstate({{ 532 if(Tl == 0) 533 return new IllegalInstruction; 534 Rd = Tstate; 535 }}); 536 0x03: Priv::rdprtt({{ 537 if(Tl == 0) 538 return new IllegalInstruction; 539 Rd = Tt; 540 }}); 541 0x04: Priv::rdprtick({{Rd = Tick;}}); 542 0x05: Priv::rdprtba({{Rd = Tba;}}); 543 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 544 0x07: Priv::rdprtl({{Rd = Tl;}}); 545 0x08: Priv::rdprpil({{Rd = Pil;}}); 546 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 547 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 548 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 549 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 550 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 551 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 552 //0x0F should cause an illegal instruction exception 553 0x10: Priv::rdprgl({{Rd = Gl;}}); 554 //0x11-0x1F should cause an illegal instruction exception 555 } 556 0x2B: BasicOperate::flushw({{ 557 if(NWindows - 2 - Cansave != 0) 558 { 559 if(Otherwin) 560 fault = new SpillNOther(4*Wstate<5:3>); 561 else 562 fault = new SpillNNormal(4*Wstate<2:0>); 563 } 564 }}); 565 0x2C: decode MOVCC3 566 { 567 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 568 0x1: decode CC 569 { 570 0x0: movcci({{ 571 if(passesCondition(Ccr<3:0>, COND4)) 572 Rd = Rs2_or_imm11; 573 else 574 Rd = Rd; 575 }}); 576 0x2: movccx({{ 577 if(passesCondition(Ccr<7:4>, COND4)) 578 Rd = Rs2_or_imm11; 579 else 580 Rd = Rd; 581 }}); 582 } 583 } 584 0x2D: sdivx({{ 585 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 586 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 587 }}); 588 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 589 0x2F: decode RCOND3 590 { 591 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 592 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 593 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 594 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 595 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 596 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 597 } 598 0x30: decode RD { 599 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 600 //0x01 should cause an illegal instruction exception 601 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 602 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 603 //0x04-0x05 should cause an illegal instruction exception 604 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 605 //0x07-0x0E should cause an illegal instruction exception 606 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 607 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 608 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 609 //0x12 should cause an illegal instruction exception 610 0x13: NoPriv::wrgsr({{ 611 if(Fprs<2:> == 0 || Pstate<4:> == 0) 612 return new FpDisabled; 613 Gsr = Rs1 ^ Rs2_or_imm13; 614 }}); 615 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 616 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 617 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 618 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 619 0x18: NoPriv::wrstick({{ 620 if(!Hpstate<2:>) 621 return new IllegalInstruction; 622 Stick = Rs1 ^ Rs2_or_imm13; 623 }}); 624 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 625 0x1A: Priv::wrstrand_sts_reg({{ 626 StrandStsReg = Rs1 ^ Rs2_or_imm13; 627 }}); 628 //0x1A is supposed to be reserved, but it writes the strand 629 //status register. 630 //0x1B-0x1F should cause an illegal instruction exception 631 } 632 0x31: decode FCN { 633 0x0: Priv::saved({{ 634 assert(Cansave < NWindows - 2); 635 assert(Otherwin || Canrestore); 636 Cansave = Cansave + 1; 637 if(Otherwin == 0) 638 Canrestore = Canrestore - 1; 639 else 640 Otherwin = Otherwin - 1; 641 }}); 642 0x1: Priv::restored({{ 643 assert(Cansave || Otherwin); 644 assert(Canrestore < NWindows - 2); 645 Canrestore = Canrestore + 1; 646 if(Otherwin == 0) 647 Cansave = Cansave - 1; 648 else 649 Otherwin = Otherwin - 1; 650 651 if(Cleanwin < NWindows - 1) 652 Cleanwin = Cleanwin + 1; 653 }}); 654 } 655 0x32: decode RD { 656 0x00: Priv::wrprtpc({{ 657 if(Tl == 0) 658 return new IllegalInstruction; 659 else 660 Tpc = Rs1 ^ Rs2_or_imm13; 661 }}); 662 0x01: Priv::wrprtnpc({{ 663 if(Tl == 0) 664 return new IllegalInstruction; 665 else 666 Tnpc = Rs1 ^ Rs2_or_imm13; 667 }}); 668 0x02: Priv::wrprtstate({{ 669 if(Tl == 0) 670 return new IllegalInstruction; 671 else 672 Tstate = Rs1 ^ Rs2_or_imm13; 673 }}); 674 0x03: Priv::wrprtt({{ 675 if(Tl == 0) 676 return new IllegalInstruction; 677 else 678 Tt = Rs1 ^ Rs2_or_imm13; 679 }}); 680 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 681 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 682 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 683 0x07: Priv::wrprtl({{ 684 if(Pstate<2:> && !Hpstate<2:>) 685 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 686 else 687 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 688 }}); 689 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 690 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 691 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 692 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 693 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 694 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 695 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 696 //0x0F should cause an illegal instruction exception 697 0x10: Priv::wrprgl({{ 698 if(Pstate<2:> && !Hpstate<2:>) 699 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 700 else 701 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 702 }}); 703 //0x11-0x1F should cause an illegal instruction exception 704 } 705 0x33: decode RD { 706 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 707 0x01: HPriv::wrhprhtstate({{ 708 if(Tl == 0) 709 return new IllegalInstruction; 710 Htstate = Rs1 ^ Rs2_or_imm13; 711 }}); 712 //0x02 should cause an illegal instruction exception 713 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 714 //0x04 should cause an illegal instruction exception 715 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 716 //0x06-0x01D should cause an illegal instruction exception 717 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 718 } 719 0x34: decode OPF{ 720 format FpBasic{ 721 0x01: fmovs({{ 722 Frds.uw = Frs2s.uw; 723 //fsr.ftt = fsr.cexc = 0 724 Fsr &= ~(7 << 14); 725 Fsr &= ~(0x1F); 726 }}); 727 0x02: fmovd({{ 728 Frd.udw = Frs2.udw; 729 //fsr.ftt = fsr.cexc = 0 730 Fsr &= ~(7 << 14); 731 Fsr &= ~(0x1F); 732 }}); 733 0x03: FpUnimpl::fmovq(); 734 0x05: fnegs({{ 735 Frds.uw = Frs2s.uw ^ (1UL << 31); 736 //fsr.ftt = fsr.cexc = 0 737 Fsr &= ~(7 << 14); 738 Fsr &= ~(0x1F); 739 }}); 740 0x06: fnegd({{ 741 Frd.udw = Frs2.udw ^ (1ULL << 63); 742 //fsr.ftt = fsr.cexc = 0 743 Fsr &= ~(7 << 14); 744 Fsr &= ~(0x1F); 745 }}); 746 0x07: FpUnimpl::fnegq(); 747 0x09: fabss({{ 748 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; 749 //fsr.ftt = fsr.cexc = 0 750 Fsr &= ~(7 << 14); 751 Fsr &= ~(0x1F); 752 }}); 753 0x0A: fabsd({{ 754 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 755 //fsr.ftt = fsr.cexc = 0 756 Fsr &= ~(7 << 14); 757 Fsr &= ~(0x1F); 758 }}); 759 0x0B: FpUnimpl::fabsq(); 760 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 761 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 762 0x2B: FpUnimpl::fsqrtq(); 763 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 764 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 765 0x43: FpUnimpl::faddq(); 766 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 767 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 768 0x47: FpUnimpl::fsubq(); 769 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 770 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 771 0x4B: FpUnimpl::fmulq(); 772 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 773 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 774 0x4F: FpUnimpl::fdivq(); 775 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 776 0x6E: FpUnimpl::fdmulq(); 777 0x81: fstox({{ 778 Frd.sdw = static_cast<int64_t>(Frs2s.sf); 779 }}); 780 0x82: fdtox({{ 781 Frd.sdw = static_cast<int64_t>(Frs2.df); 782 }}); 783 0x83: FpUnimpl::fqtox(); 784 0x84: fxtos({{ 785 Frds.sf = static_cast<float>(Frs2.sdw); 786 }}); 787 0x88: fxtod({{ 788 Frd.df = static_cast<double>(Frs2.sdw); 789 }}); 790 0x8C: FpUnimpl::fxtoq(); 791 0xC4: fitos({{ 792 Frds.sf = static_cast<float>(Frs2s.sw); 793 }}); 794 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 795 0xC7: FpUnimpl::fqtos(); 796 0xC8: fitod({{ 797 Frd.df = static_cast<double>(Frs2s.sw); 798 }}); 799 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 800 0xCB: FpUnimpl::fqtod(); 801 0xCC: FpUnimpl::fitoq(); 802 0xCD: FpUnimpl::fstoq(); 803 0xCE: FpUnimpl::fdtoq(); 804 0xD1: fstoi({{ 805 Frds.sw = static_cast<int32_t>(Frs2s.sf); 806 float t = Frds.sw; 807 if (t != Frs2s.sf) 808 Fsr = insertBits(Fsr, 4,0, 0x01); 809 }}); 810 0xD2: fdtoi({{ 811 Frds.sw = static_cast<int32_t>(Frs2.df); 812 double t = Frds.sw; 813 if (t != Frs2.df) 814 Fsr = insertBits(Fsr, 4,0, 0x01); 815 }}); 816 0xD3: FpUnimpl::fqtoi(); 817 default: FailUnimpl::fpop1(); 818 } 819 } 820 0x35: decode OPF{ 821 format FpBasic{ 822 0x01: fmovs_fcc0({{ 823 if(passesFpCondition(Fsr<11:10>, COND4)) 824 Frds = Frs2s; 825 else 826 Frds = Frds; 827 }}); 828 0x02: fmovd_fcc0({{ 829 if(passesFpCondition(Fsr<11:10>, COND4)) 830 Frd = Frs2; 831 else 832 Frd = Frd; 833 }}); 834 0x03: FpUnimpl::fmovq_fcc0(); 835 0x25: fmovrsz({{ 836 if(Rs1 == 0) 837 Frds = Frs2s; 838 else 839 Frds = Frds; 840 }}); 841 0x26: fmovrdz({{ 842 if(Rs1 == 0) 843 Frd = Frs2; 844 else 845 Frd = Frd; 846 }}); 847 0x27: FpUnimpl::fmovrqz(); 848 0x41: fmovs_fcc1({{ 849 if(passesFpCondition(Fsr<33:32>, COND4)) 850 Frds = Frs2s; 851 else 852 Frds = Frds; 853 }}); 854 0x42: fmovd_fcc1({{ 855 if(passesFpCondition(Fsr<33:32>, COND4)) 856 Frd = Frs2; 857 else 858 Frd = Frd; 859 }}); 860 0x43: FpUnimpl::fmovq_fcc1(); 861 0x45: fmovrslez({{ 862 if(Rs1 <= 0) 863 Frds = Frs2s; 864 else 865 Frds = Frds; 866 }}); 867 0x46: fmovrdlez({{ 868 if(Rs1 <= 0) 869 Frd = Frs2; 870 else 871 Frd = Frd; 872 }}); 873 0x47: FpUnimpl::fmovrqlez(); 874 0x51: fcmps({{ 875 uint8_t fcc; 876 if(isnan(Frs1s) || isnan(Frs2s)) 877 fcc = 3; 878 else if(Frs1s < Frs2s) 879 fcc = 1; 880 else if(Frs1s > Frs2s) 881 fcc = 2; 882 else 883 fcc = 0; 884 uint8_t firstbit = 10; 885 if(FCMPCC) 886 firstbit = FCMPCC * 2 + 30; 887 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 888 }}); 889 0x52: fcmpd({{ 890 uint8_t fcc; 891 if(isnan(Frs1) || isnan(Frs2)) 892 fcc = 3; 893 else if(Frs1 < Frs2) 894 fcc = 1; 895 else if(Frs1 > Frs2) 896 fcc = 2; 897 else 898 fcc = 0; 899 uint8_t firstbit = 10; 900 if(FCMPCC) 901 firstbit = FCMPCC * 2 + 30; 902 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 903 }}); 904 0x53: FpUnimpl::fcmpq(); 905 0x55: fcmpes({{ 906 uint8_t fcc = 0; 907 if(isnan(Frs1s) || isnan(Frs2s)) 908 fault = new FpExceptionIEEE754; 909 if(Frs1s < Frs2s) 910 fcc = 1; 911 else if(Frs1s > Frs2s) 912 fcc = 2; 913 uint8_t firstbit = 10; 914 if(FCMPCC) 915 firstbit = FCMPCC * 2 + 30; 916 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 917 }}); 918 0x56: fcmped({{ 919 uint8_t fcc = 0; 920 if(isnan(Frs1) || isnan(Frs2)) 921 fault = new FpExceptionIEEE754; 922 if(Frs1 < Frs2) 923 fcc = 1; 924 else if(Frs1 > Frs2) 925 fcc = 2; 926 uint8_t firstbit = 10; 927 if(FCMPCC) 928 firstbit = FCMPCC * 2 + 30; 929 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 930 }}); 931 0x57: FpUnimpl::fcmpeq(); 932 0x65: fmovrslz({{ 933 if(Rs1 < 0) 934 Frds = Frs2s; 935 else 936 Frds = Frds; 937 }}); 938 0x66: fmovrdlz({{ 939 if(Rs1 < 0) 940 Frd = Frs2; 941 else 942 Frd = Frd; 943 }}); 944 0x67: FpUnimpl::fmovrqlz(); 945 0x81: fmovs_fcc2({{ 946 if(passesFpCondition(Fsr<35:34>, COND4)) 947 Frds = Frs2s; 948 else 949 Frds = Frds; 950 }}); 951 0x82: fmovd_fcc2({{ 952 if(passesFpCondition(Fsr<35:34>, COND4)) 953 Frd = Frs2; 954 else 955 Frd = Frd; 956 }}); 957 0x83: FpUnimpl::fmovq_fcc2(); 958 0xA5: fmovrsnz({{ 959 if(Rs1 != 0) 960 Frds = Frs2s; 961 else 962 Frds = Frds; 963 }}); 964 0xA6: fmovrdnz({{ 965 if(Rs1 != 0) 966 Frd = Frs2; 967 else 968 Frd = Frd; 969 }}); 970 0xA7: FpUnimpl::fmovrqnz(); 971 0xC1: fmovs_fcc3({{ 972 if(passesFpCondition(Fsr<37:36>, COND4)) 973 Frds = Frs2s; 974 else 975 Frds = Frds; 976 }}); 977 0xC2: fmovd_fcc3({{ 978 if(passesFpCondition(Fsr<37:36>, COND4)) 979 Frd = Frs2; 980 else 981 Frd = Frd; 982 }}); 983 0xC3: FpUnimpl::fmovq_fcc3(); 984 0xC5: fmovrsgz({{ 985 if(Rs1 > 0) 986 Frds = Frs2s; 987 else 988 Frds = Frds; 989 }}); 990 0xC6: fmovrdgz({{ 991 if(Rs1 > 0) 992 Frd = Frs2; 993 else 994 Frd = Frd; 995 }}); 996 0xC7: FpUnimpl::fmovrqgz(); 997 0xE5: fmovrsgez({{ 998 if(Rs1 >= 0) 999 Frds = Frs2s; 1000 else 1001 Frds = Frds; 1002 }}); 1003 0xE6: fmovrdgez({{ 1004 if(Rs1 >= 0) 1005 Frd = Frs2; 1006 else 1007 Frd = Frd; 1008 }}); 1009 0xE7: FpUnimpl::fmovrqgez(); 1010 0x101: fmovs_icc({{ 1011 if(passesCondition(Ccr<3:0>, COND4)) 1012 Frds = Frs2s; 1013 else 1014 Frds = Frds; 1015 }}); 1016 0x102: fmovd_icc({{ 1017 if(passesCondition(Ccr<3:0>, COND4)) 1018 Frd = Frs2; 1019 else 1020 Frd = Frd; 1021 }}); 1022 0x103: FpUnimpl::fmovq_icc(); 1023 0x181: fmovs_xcc({{ 1024 if(passesCondition(Ccr<7:4>, COND4)) 1025 Frds = Frs2s; 1026 else 1027 Frds = Frds; 1028 }}); 1029 0x182: fmovd_xcc({{ 1030 if(passesCondition(Ccr<7:4>, COND4)) 1031 Frd = Frs2; 1032 else 1033 Frd = Frd; 1034 }}); 1035 0x183: FpUnimpl::fmovq_xcc(); 1036 default: FailUnimpl::fpop2(); 1037 } 1038 } 1039 //This used to be just impdep1, but now it's a whole bunch 1040 //of instructions 1041 0x36: decode OPF{ 1042 0x00: FailUnimpl::edge8(); 1043 0x01: FailUnimpl::edge8n(); 1044 0x02: FailUnimpl::edge8l(); 1045 0x03: FailUnimpl::edge8ln(); 1046 0x04: FailUnimpl::edge16(); 1047 0x05: FailUnimpl::edge16n(); 1048 0x06: FailUnimpl::edge16l(); 1049 0x07: FailUnimpl::edge16ln(); 1050 0x08: FailUnimpl::edge32(); 1051 0x09: FailUnimpl::edge32n(); 1052 0x0A: FailUnimpl::edge32l(); 1053 0x0B: FailUnimpl::edge32ln(); 1054 0x10: FailUnimpl::array8(); 1055 0x12: FailUnimpl::array16(); 1056 0x14: FailUnimpl::array32(); 1057 0x18: BasicOperate::alignaddr({{ 1058 uint64_t sum = Rs1 + Rs2; 1059 Rd = sum & ~7; 1060 Gsr = (Gsr & ~7) | (sum & 7); 1061 }}); 1062 0x19: FailUnimpl::bmask(); 1063 0x1A: BasicOperate::alignaddresslittle({{ 1064 uint64_t sum = Rs1 + Rs2; 1065 Rd = sum & ~7; 1066 Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 1067 }}); 1068 0x20: FailUnimpl::fcmple16(); 1069 0x22: FailUnimpl::fcmpne16(); 1070 0x24: FailUnimpl::fcmple32(); 1071 0x26: FailUnimpl::fcmpne32(); 1072 0x28: FailUnimpl::fcmpgt16(); 1073 0x2A: FailUnimpl::fcmpeq16(); 1074 0x2C: FailUnimpl::fcmpgt32(); 1075 0x2E: FailUnimpl::fcmpeq32(); 1076 0x31: FailUnimpl::fmul8x16(); 1077 0x33: FailUnimpl::fmul8x16au(); 1078 0x35: FailUnimpl::fmul8x16al(); 1079 0x36: FailUnimpl::fmul8sux16(); 1080 0x37: FailUnimpl::fmul8ulx16(); 1081 0x38: FailUnimpl::fmuld8sux16(); 1082 0x39: FailUnimpl::fmuld8ulx16(); 1083 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 1084 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 1085 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 1086 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 1087 0x48: BasicOperate::faligndata({{ 1088 uint64_t msbX = Frs1.udw; 1089 uint64_t lsbX = Frs2.udw; 1090 //Some special cases need to be split out, first 1091 //because they're the most likely to be used, and 1092 //second because otherwise, we end up shifting by 1093 //greater than the width of the type being shifted, 1094 //namely 64, which produces undefined results according 1095 //to the C standard. 1096 switch(Gsr<2:0>) 1097 { 1098 case 0: 1099 Frd.udw = msbX; 1100 break; 1101 case 8: 1102 Frd.udw = lsbX; 1103 break; 1104 default: 1105 uint64_t msbShift = Gsr<2:0> * 8; 1106 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 1107 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 1108 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 1109 Frd.udw = ((msbX & msbMask) << msbShift) | 1110 ((lsbX & lsbMask) >> lsbShift); 1111 } 1112 }}); 1113 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 1114 0x4C: FailUnimpl::bshuffle(); 1115 0x4D: FailUnimpl::fexpand(); 1116 0x50: FailUnimpl::fpadd16(); 1117 0x51: FailUnimpl::fpadd16s(); 1118 0x52: FailUnimpl::fpadd32(); 1119 0x53: FailUnimpl::fpadd32s(); 1120 0x54: FailUnimpl::fpsub16(); 1121 0x55: FailUnimpl::fpsub16s(); 1122 0x56: FailUnimpl::fpsub32(); 1123 0x57: FailUnimpl::fpsub32s(); 1124 0x60: FpBasic::fzero({{Frd.df = 0;}}); 1125 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 1126 0x62: FailUnimpl::fnor(); 1127 0x63: FailUnimpl::fnors(); 1128 0x64: FailUnimpl::fandnot2(); 1129 0x65: FailUnimpl::fandnot2s(); 1130 0x66: FpBasic::fnot2({{ 1131 Frd.df = (double)(~((uint64_t)Frs2.df)); 1132 }}); 1133 0x67: FpBasic::fnot2s({{ 1134 Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 1135 }}); 1136 0x68: FailUnimpl::fandnot1(); 1137 0x69: FailUnimpl::fandnot1s(); 1138 0x6A: FpBasic::fnot1({{ 1139 Frd.df = (double)(~((uint64_t)Frs1.df)); 1140 }}); 1141 0x6B: FpBasic::fnot1s({{ 1142 Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 1143 }}); 1144 0x6C: FailUnimpl::fxor(); 1145 0x6D: FailUnimpl::fxors(); 1146 0x6E: FailUnimpl::fnand(); 1147 0x6F: FailUnimpl::fnands(); 1148 0x70: FailUnimpl::fand(); 1149 0x71: FailUnimpl::fands(); 1150 0x72: FailUnimpl::fxnor(); 1151 0x73: FailUnimpl::fxnors(); 1152 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 1153 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 1154 0x76: FailUnimpl::fornot2(); 1155 0x77: FailUnimpl::fornot2s(); 1156 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 1157 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 1158 0x7A: FailUnimpl::fornot1(); 1159 0x7B: FailUnimpl::fornot1s(); 1160 0x7C: FailUnimpl::for(); 1161 0x7D: FailUnimpl::fors(); 1162 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 1163 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 1164 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 1165 0x81: FailUnimpl::siam(); 1166 } 1167 // M5 special opcodes use the reserved IMPDEP2A opcode space 1168 0x37: decode M5FUNC { 1169#if FULL_SYSTEM 1170 format BasicOperate { 1171 // we have 7 bits of space here to play with... 1172 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 1173 }}, No_OpClass, IsNonSpeculative); 1174 0x50: m5readfile({{ 1175 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 1176 }}, IsNonSpeculative); 1177 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 1178 }}, IsNonSpeculative); 1179 0x54: m5panic({{ 1180 panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 1181 }}, No_OpClass, IsNonSpeculative); 1182 } 1183#endif 1184 default: Trap::impdep2({{fault = new IllegalInstruction;}}); 1185 } 1186 0x38: Branch::jmpl({{ 1187 Addr target = Rs1 + Rs2_or_imm13; 1188 if(target & 0x3) 1189 fault = new MemAddressNotAligned; 1190 else 1191 { 1192 if (Pstate<3:>) 1193 Rd = (xc->readPC())<31:0>; 1194 else 1195 Rd = xc->readPC(); 1196 NNPC = target; 1197 } 1198 }}); 1199 0x39: Branch::return({{ 1200 Addr target = Rs1 + Rs2_or_imm13; 1201 if(fault == NoFault) 1202 { 1203 //Check for fills which are higher priority than alignment 1204 //faults. 1205 if(Canrestore == 0) 1206 { 1207 if(Otherwin) 1208 fault = new FillNOther(4*Wstate<5:3>); 1209 else 1210 fault = new FillNNormal(4*Wstate<2:0>); 1211 } 1212 //Check for alignment faults 1213 else if(target & 0x3) 1214 fault = new MemAddressNotAligned; 1215 else 1216 { 1217 NNPC = target; 1218 Cwp = (Cwp - 1 + NWindows) % NWindows; 1219 Cansave = Cansave + 1; 1220 Canrestore = Canrestore - 1; 1221 } 1222 } 1223 }}); 1224 0x3A: decode CC 1225 { 1226 0x0: Trap::tcci({{ 1227 if(passesCondition(Ccr<3:0>, COND2)) 1228 { 1229 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1230 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1231 fault = new TrapInstruction(lTrapNum); 1232 } 1233 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 1234 0x2: Trap::tccx({{ 1235 if(passesCondition(Ccr<7:4>, COND2)) 1236 { 1237 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1238 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1239 fault = new TrapInstruction(lTrapNum); 1240 } 1241 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 1242 } 1243 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 1244 MemWriteOp); 1245 0x3C: save({{ 1246 if(Cansave == 0) 1247 { 1248 if(Otherwin) 1249 fault = new SpillNOther(4*Wstate<5:3>); 1250 else 1251 fault = new SpillNNormal(4*Wstate<2:0>); 1252 } 1253 else if(Cleanwin - Canrestore == 0) 1254 { 1255 fault = new CleanWindow; 1256 } 1257 else 1258 { 1259 Cwp = (Cwp + 1) % NWindows; 1260 Rd_next = Rs1 + Rs2_or_imm13; 1261 Cansave = Cansave - 1; 1262 Canrestore = Canrestore + 1; 1263 } 1264 }}); 1265 0x3D: restore({{ 1266 if(Canrestore == 0) 1267 { 1268 if(Otherwin) 1269 fault = new FillNOther(4*Wstate<5:3>); 1270 else 1271 fault = new FillNNormal(4*Wstate<2:0>); 1272 } 1273 else 1274 { 1275 Cwp = (Cwp - 1 + NWindows) % NWindows; 1276 Rd_prev = Rs1 + Rs2_or_imm13; 1277 Cansave = Cansave + 1; 1278 Canrestore = Canrestore - 1; 1279 } 1280 }}); 1281 0x3E: decode FCN { 1282 0x0: Priv::done({{ 1283 if(Tl == 0) 1284 return new IllegalInstruction; 1285 1286 Cwp = Tstate<4:0>; 1287 Pstate = Tstate<20:8>; 1288 Asi = Tstate<31:24>; 1289 Ccr = Tstate<39:32>; 1290 Gl = Tstate<42:40>; 1291 Hpstate = Htstate; 1292 NPC = Tnpc; 1293 NNPC = Tnpc + 4; 1294 Tl = Tl - 1; 1295 }}); 1296 0x1: Priv::retry({{ 1297 if(Tl == 0) 1298 return new IllegalInstruction; 1299 Cwp = Tstate<4:0>; 1300 Pstate = Tstate<20:8>; 1301 Asi = Tstate<31:24>; 1302 Ccr = Tstate<39:32>; 1303 Gl = Tstate<42:40>; 1304 Hpstate = Htstate; 1305 NPC = Tpc; 1306 NNPC = Tnpc; 1307 Tl = Tl - 1; 1308 }}); 1309 } 1310 } 1311 } 1312 0x3: decode OP3 { 1313 format Load { 1314 0x00: lduw({{Rd = Mem.uw;}}); 1315 0x01: ldub({{Rd = Mem.ub;}}); 1316 0x02: lduh({{Rd = Mem.uhw;}}); 1317 0x03: ldtw({{ 1318 RdLow = (Mem.tuw).a; 1319 RdHigh = (Mem.tuw).b; 1320 }}); 1321 } 1322 format Store { 1323 0x04: stw({{Mem.uw = Rd.sw;}}); 1324 0x05: stb({{Mem.ub = Rd.sb;}}); 1325 0x06: sth({{Mem.uhw = Rd.shw;}}); 1326 0x07: sttw({{ 1327 //This temporary needs to be here so that the parser 1328 //will correctly identify this instruction as a store. 1329 //It's probably either the parenthesis or referencing 1330 //the member variable that throws confuses it. 1331 Twin32_t temp; 1332 temp.a = RdLow<31:0>; 1333 temp.b = RdHigh<31:0>; 1334 Mem.tuw = temp; 1335 }}); 1336 } 1337 format Load { 1338 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 1339 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 1340 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 1341 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 1342 } 1343 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 1344 {{ 1345 uint8_t tmp = mem_data; 1346 Rd.ub = tmp; 1347 }}, MEM_SWAP); 1348 0x0E: Store::stx({{Mem.udw = Rd}}); 1349 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 1350 {{ 1351 uint32_t tmp = mem_data; 1352 Rd.uw = tmp; 1353 }}, MEM_SWAP); 1354 format LoadAlt { 1355 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 1356 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 1357 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 1358 0x13: decode EXT_ASI { 1359 //ASI_LDTD_AIUP 1360 0x22: TwinLoad::ldtx_aiup( 1361 {{RdLow.udw = (Mem.tudw).a; 1362 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1363 //ASI_LDTD_AIUS 1364 0x23: TwinLoad::ldtx_aius( 1365 {{RdLow.udw = (Mem.tudw).a; 1366 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1367 //ASI_QUAD_LDD 1368 0x24: TwinLoad::ldtx_quad_ldd( 1369 {{RdLow.udw = (Mem.tudw).a; 1370 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1371 //ASI_LDTX_REAL 1372 0x26: TwinLoad::ldtx_real( 1373 {{RdLow.udw = (Mem.tudw).a; 1374 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1375 //ASI_LDTX_N 1376 0x27: TwinLoad::ldtx_n( 1377 {{RdLow.udw = (Mem.tudw).a; 1378 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1379 //ASI_LDTX_AIUP_L 1380 0x2A: TwinLoad::ldtx_aiup_l( 1381 {{RdLow.udw = (Mem.tudw).a; 1382 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1383 //ASI_LDTX_AIUS_L 1384 0x2B: TwinLoad::ldtx_aius_l( 1385 {{RdLow.udw = (Mem.tudw).a; 1386 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1387 //ASI_LDTX_L 1388 0x2C: TwinLoad::ldtx_l( 1389 {{RdLow.udw = (Mem.tudw).a; 1390 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1391 //ASI_LDTX_REAL_L 1392 0x2E: TwinLoad::ldtx_real_l( 1393 {{RdLow.udw = (Mem.tudw).a; 1394 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1395 //ASI_LDTX_N_L 1396 0x2F: TwinLoad::ldtx_n_l( 1397 {{RdLow.udw = (Mem.tudw).a; 1398 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1399 //ASI_LDTX_P 1400 0xE2: TwinLoad::ldtx_p( 1401 {{RdLow.udw = (Mem.tudw).a; 1402 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1403 //ASI_LDTX_S 1404 0xE3: TwinLoad::ldtx_s( 1405 {{RdLow.udw = (Mem.tudw).a; 1406 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1407 //ASI_LDTX_PL 1408 0xEA: TwinLoad::ldtx_pl( 1409 {{RdLow.udw = (Mem.tudw).a; 1410 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1411 //ASI_LDTX_SL 1412 0xEB: TwinLoad::ldtx_sl( 1413 {{RdLow.udw = (Mem.tudw).a; 1414 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1415 default: ldtwa({{ 1416 RdLow = (Mem.tuw).a; 1417 RdHigh = (Mem.tuw).b; 1418 }}, {{EXT_ASI}}); 1419 } 1420 } 1421 format StoreAlt { 1422 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 1423 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 1424 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 1425 0x17: sttwa({{ 1426 //This temporary needs to be here so that the parser 1427 //will correctly identify this instruction as a store. 1428 //It's probably either the parenthesis or referencing 1429 //the member variable that throws confuses it. 1430 Twin32_t temp; 1431 temp.a = RdLow<31:0>; 1432 temp.b = RdHigh<31:0>; 1433 Mem.tuw = temp; 1434 }}, {{EXT_ASI}}); 1435 } 1436 format LoadAlt { 1437 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 1438 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 1439 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 1440 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); 1441 } 1442 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 1443 {{ 1444 uint8_t tmp = mem_data; 1445 Rd.ub = tmp; 1446 }}, {{EXT_ASI}}, MEM_SWAP); 1447 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 1448 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 1449 {{ 1450 uint32_t tmp = mem_data; 1451 Rd.uw = tmp; 1452 }}, {{EXT_ASI}}, MEM_SWAP); 1453 1454 format Trap { 1455 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 1456 0x21: decode RD { 1457 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 1458 if (fault) 1459 return fault; 1460 Fsr = Mem.uw | Fsr<63:32>;}}); 1461 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 1462 if (fault) 1463 return fault; 1464 Fsr = Mem.udw;}}); 1465 default: FailUnimpl::ldfsrOther(); 1466 } 1467 0x22: ldqf({{fault = new FpDisabled;}}); 1468 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1469 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 1470 0x25: decode RD { 1471 0x0: Store::stfsr({{fault = checkFpEnableFault(xc); 1472 if (fault) 1473 return fault; 1474 Mem.uw = Fsr<31:0>; 1475 Fsr = insertBits(Fsr,16,14,0);}}); 1476 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc); 1477 if (fault) 1478 return fault; 1479 Mem.udw = Fsr; 1480 Fsr = insertBits(Fsr,16,14,0);}}); 1481 default: FailUnimpl::stfsrOther(); 1482 } 1483 0x26: stqf({{fault = new FpDisabled;}}); 1484 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1485 0x2D: Nop::prefetch({{ }}); 1486 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); 1487 0x32: ldqfa({{fault = new FpDisabled;}}); 1488 format LoadAlt { 1489 0x33: decode EXT_ASI { 1490 //ASI_NUCLEUS 1491 0x04: FailUnimpl::lddfa_n(); 1492 //ASI_NUCLEUS_LITTLE 1493 0x0C: FailUnimpl::lddfa_nl(); 1494 //ASI_AS_IF_USER_PRIMARY 1495 0x10: FailUnimpl::lddfa_aiup(); 1496 //ASI_AS_IF_USER_PRIMARY_LITTLE 1497 0x18: FailUnimpl::lddfa_aiupl(); 1498 //ASI_AS_IF_USER_SECONDARY 1499 0x11: FailUnimpl::lddfa_aius(); 1500 //ASI_AS_IF_USER_SECONDARY_LITTLE 1501 0x19: FailUnimpl::lddfa_aiusl(); 1502 //ASI_REAL 1503 0x14: FailUnimpl::lddfa_real(); 1504 //ASI_REAL_LITTLE 1505 0x1C: FailUnimpl::lddfa_real_l(); 1506 //ASI_REAL_IO 1507 0x15: FailUnimpl::lddfa_real_io(); 1508 //ASI_REAL_IO_LITTLE 1509 0x1D: FailUnimpl::lddfa_real_io_l(); 1510 //ASI_PRIMARY 1511 0x80: FailUnimpl::lddfa_p(); 1512 //ASI_PRIMARY_LITTLE 1513 0x88: FailUnimpl::lddfa_pl(); 1514 //ASI_SECONDARY 1515 0x81: FailUnimpl::lddfa_s(); 1516 //ASI_SECONDARY_LITTLE 1517 0x89: FailUnimpl::lddfa_sl(); 1518 //ASI_PRIMARY_NO_FAULT 1519 0x82: FailUnimpl::lddfa_pnf(); 1520 //ASI_PRIMARY_NO_FAULT_LITTLE 1521 0x8A: FailUnimpl::lddfa_pnfl(); 1522 //ASI_SECONDARY_NO_FAULT 1523 0x83: FailUnimpl::lddfa_snf(); 1524 //ASI_SECONDARY_NO_FAULT_LITTLE 1525 0x8B: FailUnimpl::lddfa_snfl(); 1526 1527 format BlockLoad { 1528 // LDBLOCKF 1529 //ASI_BLOCK_AS_IF_USER_PRIMARY 1530 0x16: FailUnimpl::ldblockf_aiup(); 1531 //ASI_BLOCK_AS_IF_USER_SECONDARY 1532 0x17: FailUnimpl::ldblockf_aius(); 1533 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1534 0x1E: FailUnimpl::ldblockf_aiupl(); 1535 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1536 0x1F: FailUnimpl::ldblockf_aiusl(); 1537 //ASI_BLOCK_PRIMARY 1538 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); 1539 //ASI_BLOCK_SECONDARY 1540 0xF1: FailUnimpl::ldblockf_s(); 1541 //ASI_BLOCK_PRIMARY_LITTLE 1542 0xF8: FailUnimpl::ldblockf_pl(); 1543 //ASI_BLOCK_SECONDARY_LITTLE 1544 0xF9: FailUnimpl::ldblockf_sl(); 1545 } 1546 1547 //LDSHORTF 1548 //ASI_FL8_PRIMARY 1549 0xD0: FailUnimpl::ldshortf_8p(); 1550 //ASI_FL8_SECONDARY 1551 0xD1: FailUnimpl::ldshortf_8s(); 1552 //ASI_FL8_PRIMARY_LITTLE 1553 0xD8: FailUnimpl::ldshortf_8pl(); 1554 //ASI_FL8_SECONDARY_LITTLE 1555 0xD9: FailUnimpl::ldshortf_8sl(); 1556 //ASI_FL16_PRIMARY 1557 0xD2: FailUnimpl::ldshortf_16p(); 1558 //ASI_FL16_SECONDARY 1559 0xD3: FailUnimpl::ldshortf_16s(); 1560 //ASI_FL16_PRIMARY_LITTLE 1561 0xDA: FailUnimpl::ldshortf_16pl(); 1562 //ASI_FL16_SECONDARY_LITTLE 1563 0xDB: FailUnimpl::ldshortf_16sl(); 1564 //Not an ASI which is legal with lddfa 1565 default: Trap::lddfa_bad_asi( 1566 {{fault = new DataAccessException;}}); 1567 } 1568 } 1569 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 1570 0x36: stqfa({{fault = new FpDisabled;}}); 1571 format StoreAlt { 1572 0x37: decode EXT_ASI { 1573 //ASI_NUCLEUS 1574 0x04: FailUnimpl::stdfa_n(); 1575 //ASI_NUCLEUS_LITTLE 1576 0x0C: FailUnimpl::stdfa_nl(); 1577 //ASI_AS_IF_USER_PRIMARY 1578 0x10: FailUnimpl::stdfa_aiup(); 1579 //ASI_AS_IF_USER_PRIMARY_LITTLE 1580 0x18: FailUnimpl::stdfa_aiupl(); 1581 //ASI_AS_IF_USER_SECONDARY 1582 0x11: FailUnimpl::stdfa_aius(); 1583 //ASI_AS_IF_USER_SECONDARY_LITTLE 1584 0x19: FailUnimpl::stdfa_aiusl(); 1585 //ASI_REAL 1586 0x14: FailUnimpl::stdfa_real(); 1587 //ASI_REAL_LITTLE 1588 0x1C: FailUnimpl::stdfa_real_l(); 1589 //ASI_REAL_IO 1590 0x15: FailUnimpl::stdfa_real_io(); 1591 //ASI_REAL_IO_LITTLE 1592 0x1D: FailUnimpl::stdfa_real_io_l(); 1593 //ASI_PRIMARY 1594 0x80: FailUnimpl::stdfa_p(); 1595 //ASI_PRIMARY_LITTLE 1596 0x88: FailUnimpl::stdfa_pl(); 1597 //ASI_SECONDARY 1598 0x81: FailUnimpl::stdfa_s(); 1599 //ASI_SECONDARY_LITTLE 1600 0x89: FailUnimpl::stdfa_sl(); 1601 //ASI_PRIMARY_NO_FAULT 1602 0x82: FailUnimpl::stdfa_pnf(); 1603 //ASI_PRIMARY_NO_FAULT_LITTLE 1604 0x8A: FailUnimpl::stdfa_pnfl(); 1605 //ASI_SECONDARY_NO_FAULT 1606 0x83: FailUnimpl::stdfa_snf(); 1607 //ASI_SECONDARY_NO_FAULT_LITTLE 1608 0x8B: FailUnimpl::stdfa_snfl(); 1609 1610 format BlockStore { 1611 // STBLOCKF 1612 //ASI_BLOCK_AS_IF_USER_PRIMARY 1613 0x16: FailUnimpl::stblockf_aiup(); 1614 //ASI_BLOCK_AS_IF_USER_SECONDARY 1615 0x17: FailUnimpl::stblockf_aius(); 1616 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1617 0x1E: FailUnimpl::stblockf_aiupl(); 1618 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1619 0x1F: FailUnimpl::stblockf_aiusl(); 1620 //ASI_BLOCK_PRIMARY 1621 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); 1622 //ASI_BLOCK_SECONDARY 1623 0xF1: FailUnimpl::stblockf_s(); 1624 //ASI_BLOCK_PRIMARY_LITTLE 1625 0xF8: FailUnimpl::stblockf_pl(); 1626 //ASI_BLOCK_SECONDARY_LITTLE 1627 0xF9: FailUnimpl::stblockf_sl(); 1628 } 1629 1630 //STSHORTF 1631 //ASI_FL8_PRIMARY 1632 0xD0: FailUnimpl::stshortf_8p(); 1633 //ASI_FL8_SECONDARY 1634 0xD1: FailUnimpl::stshortf_8s(); 1635 //ASI_FL8_PRIMARY_LITTLE 1636 0xD8: FailUnimpl::stshortf_8pl(); 1637 //ASI_FL8_SECONDARY_LITTLE 1638 0xD9: FailUnimpl::stshortf_8sl(); 1639 //ASI_FL16_PRIMARY 1640 0xD2: FailUnimpl::stshortf_16p(); 1641 //ASI_FL16_SECONDARY 1642 0xD3: FailUnimpl::stshortf_16s(); 1643 //ASI_FL16_PRIMARY_LITTLE 1644 0xDA: FailUnimpl::stshortf_16pl(); 1645 //ASI_FL16_SECONDARY_LITTLE 1646 0xDB: FailUnimpl::stshortf_16sl(); 1647 //Not an ASI which is legal with lddfa 1648 default: Trap::stdfa_bad_asi( 1649 {{fault = new DataAccessException;}}); 1650 } 1651 } 1652 0x3C: CasAlt::casa({{ 1653 mem_data = htog(Rs2.uw); 1654 Mem.uw = Rd.uw;}}, 1655 {{ 1656 uint32_t tmp = mem_data; 1657 Rd.uw = tmp; 1658 }}, {{EXT_ASI}}, MEM_SWAP_COND); 1659 0x3D: Nop::prefetcha({{ }}); 1660 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 1661 Mem.udw = Rd.udw; }}, 1662 {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND); 1663 } 1664 } 1665} 1666