decoder.isa revision 4005:c31dee26d855
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 //Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 format BranchN 43 { 44 //bpcc 45 0x1: decode COND2 46 { 47 //Branch Always 48 0x8: decode A 49 { 50 0x0: bpa(19, {{ 51 NNPC = xc->readPC() + disp; 52 }}); 53 0x1: bpa(19, {{ 54 NPC = xc->readPC() + disp; 55 NNPC = NPC + 4; 56 }}, ',a'); 57 } 58 //Branch Never 59 0x0: decode A 60 { 61 0x0: bpn(19, {{ 62 NNPC = NNPC;//Don't do anything 63 }}); 64 0x1: bpn(19, {{ 65 NNPC = NPC + 8; 66 NPC = NPC + 4; 67 }}, ',a'); 68 } 69 default: decode BPCC 70 { 71 0x0: bpcci(19, {{ 72 if(passesCondition(Ccr<3:0>, COND2)) 73 NNPC = xc->readPC() + disp; 74 else 75 handle_annul 76 }}); 77 0x2: bpccx(19, {{ 78 if(passesCondition(Ccr<7:4>, COND2)) 79 NNPC = xc->readPC() + disp; 80 else 81 handle_annul 82 }}); 83 } 84 } 85 //bicc 86 0x2: decode COND2 87 { 88 //Branch Always 89 0x8: decode A 90 { 91 0x0: ba(22, {{ 92 NNPC = xc->readPC() + disp; 93 }}); 94 0x1: ba(22, {{ 95 NPC = xc->readPC() + disp; 96 NNPC = NPC + 4; 97 }}, ',a'); 98 } 99 //Branch Never 100 0x0: decode A 101 { 102 0x0: bn(22, {{ 103 NNPC = NNPC;//Don't do anything 104 }}); 105 0x1: bn(22, {{ 106 NNPC = NPC + 8; 107 NPC = NPC + 4; 108 }}, ',a'); 109 } 110 default: bicc(22, {{ 111 if(passesCondition(Ccr<3:0>, COND2)) 112 NNPC = xc->readPC() + disp; 113 else 114 handle_annul 115 }}); 116 } 117 } 118 0x3: decode RCOND2 119 { 120 format BranchSplit 121 { 122 0x1: bpreq({{ 123 if(Rs1.sdw == 0) 124 NNPC = xc->readPC() + disp; 125 else 126 handle_annul 127 }}); 128 0x2: bprle({{ 129 if(Rs1.sdw <= 0) 130 NNPC = xc->readPC() + disp; 131 else 132 handle_annul 133 }}); 134 0x3: bprl({{ 135 if(Rs1.sdw < 0) 136 NNPC = xc->readPC() + disp; 137 else 138 handle_annul 139 }}); 140 0x5: bprne({{ 141 if(Rs1.sdw != 0) 142 NNPC = xc->readPC() + disp; 143 else 144 handle_annul 145 }}); 146 0x6: bprg({{ 147 if(Rs1.sdw > 0) 148 NNPC = xc->readPC() + disp; 149 else 150 handle_annul 151 }}); 152 0x7: bprge({{ 153 if(Rs1.sdw >= 0) 154 NNPC = xc->readPC() + disp; 155 else 156 handle_annul 157 }}); 158 } 159 } 160 //SETHI (or NOP if rd == 0 and imm == 0) 161 0x4: SetHi::sethi({{Rd.udw = imm;}}); 162 //fbpfcc 163 0x5: decode COND2 { 164 format BranchN { 165 //Branch Always 166 0x8: decode A 167 { 168 0x0: fbpa(22, {{ 169 NNPC = xc->readPC() + disp; 170 }}); 171 0x1: fbpa(22, {{ 172 NPC = xc->readPC() + disp; 173 NNPC = NPC + 4; 174 }}, ',a'); 175 } 176 //Branch Never 177 0x0: decode A 178 { 179 0x0: fbpn(22, {{ 180 NNPC = NNPC;//Don't do anything 181 }}); 182 0x1: fbpn(22, {{ 183 NNPC = NPC + 8; 184 NPC = NPC + 4; 185 }}, ',a'); 186 } 187 default: decode BPCC { 188 0x0: fbpcc0(22, {{ 189 if(passesFpCondition(Fsr<11:10>, COND2)) 190 NNPC = xc->readPC() + disp; 191 else 192 handle_annul 193 }}); 194 0x1: fbpcc1(22, {{ 195 if(passesFpCondition(Fsr<33:32>, COND2)) 196 NNPC = xc->readPC() + disp; 197 else 198 handle_annul 199 }}); 200 0x2: fbpcc2(22, {{ 201 if(passesFpCondition(Fsr<35:34>, COND2)) 202 NNPC = xc->readPC() + disp; 203 else 204 handle_annul 205 }}); 206 0x3: fbpcc3(22, {{ 207 if(passesFpCondition(Fsr<37:36>, COND2)) 208 NNPC = xc->readPC() + disp; 209 else 210 handle_annul 211 }}); 212 } 213 } 214 } 215 //fbfcc 216 0x6: decode COND2 { 217 format BranchN { 218 //Branch Always 219 0x8: decode A 220 { 221 0x0: fba(22, {{ 222 NNPC = xc->readPC() + disp; 223 }}); 224 0x1: fba(22, {{ 225 NPC = xc->readPC() + disp; 226 NNPC = NPC + 4; 227 }}, ',a'); 228 } 229 //Branch Never 230 0x0: decode A 231 { 232 0x0: fbn(22, {{ 233 NNPC = NNPC;//Don't do anything 234 }}); 235 0x1: fbn(22, {{ 236 NNPC = NPC + 8; 237 NPC = NPC + 4; 238 }}, ',a'); 239 } 240 default: fbfcc(22, {{ 241 if(passesFpCondition(Fsr<11:10>, COND2)) 242 NNPC = xc->readPC() + disp; 243 else 244 handle_annul 245 }}); 246 } 247 } 248 } 249 0x1: BranchN::call(30, {{ 250 if (Pstate<3:>) 251 R15 = (xc->readPC())<31:0>; 252 else 253 R15 = xc->readPC(); 254 NNPC = R15 + disp; 255 }}); 256 0x2: decode OP3 { 257 format IntOp { 258 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 259 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 260 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 261 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 262 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 263 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 264 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 265 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 266 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 267 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 268 0x0A: umul({{ 269 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 270 Y = Rd<63:32>; 271 }}); 272 0x0B: smul({{ 273 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 274 Y = Rd.sdw<63:32>; 275 }}); 276 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 277 0x0D: udivx({{ 278 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 279 else Rd.udw = Rs1.udw / Rs2_or_imm13; 280 }}); 281 0x0E: udiv({{ 282 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 283 else 284 { 285 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 286 if(Rd.udw >> 32 != 0) 287 Rd.udw = 0xFFFFFFFF; 288 } 289 }}); 290 0x0F: sdiv({{ 291 if(Rs2_or_imm13.sdw == 0) 292 fault = new DivisionByZero; 293 else 294 { 295 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 296 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) 297 Rd.udw = 0x7FFFFFFF; 298 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 299 Rd.udw = ULL(0xFFFFFFFF80000000); 300 } 301 }}); 302 } 303 format IntOpCc { 304 0x10: addcc({{ 305 int64_t resTemp, val2 = Rs2_or_imm13; 306 Rd = resTemp = Rs1 + val2;}}, 307 {{(Rs1<31:0> + val2<31:0>)<32:>}}, 308 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 309 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 310 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 311 ); 312 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 313 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 314 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 315 0x14: subcc({{ 316 int64_t val2 = Rs2_or_imm13; 317 Rd = Rs1 - val2;}}, 318 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 319 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 320 {{(~(Rs1<63:1> + (~val2)<63:1> + 321 (Rs1 | ~val2)<0:>))<63:>}}, 322 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 323 ); 324 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 325 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 326 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 327 0x18: addccc({{ 328 int64_t resTemp, val2 = Rs2_or_imm13; 329 int64_t carryin = Ccr<0:0>; 330 Rd = resTemp = Rs1 + val2 + carryin;}}, 331 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 332 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 333 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}}, 334 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 335 ); 336 0x1A: IntOpCcRes::umulcc({{ 337 uint64_t resTemp; 338 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 339 Y = resTemp<63:32>;}}); 340 0x1B: IntOpCcRes::smulcc({{ 341 int64_t resTemp; 342 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 343 Y = resTemp<63:32>;}}); 344 0x1C: subccc({{ 345 int64_t resTemp, val2 = Rs2_or_imm13; 346 int64_t carryin = Ccr<0:0>; 347 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 348 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}}, 349 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 350 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}}, 351 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 352 ); 353 0x1D: IntOpCcRes::udivxcc({{ 354 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 355 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 356 0x1E: udivcc({{ 357 uint32_t resTemp, val2 = Rs2_or_imm13.udw; 358 int32_t overflow = 0; 359 if(val2 == 0) fault = new DivisionByZero; 360 else 361 { 362 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 363 overflow = (resTemp<63:32> != 0); 364 if(overflow) Rd = resTemp = 0xFFFFFFFF; 365 else Rd = resTemp; 366 } }}, 367 {{0}}, 368 {{overflow}}, 369 {{0}}, 370 {{0}} 371 ); 372 0x1F: sdivcc({{ 373 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 374 bool overflow = false, underflow = false; 375 if(val2 == 0) fault = new DivisionByZero; 376 else 377 { 378 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 379 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 380 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 381 if(overflow) Rd = 0x7FFFFFFF; 382 else if(underflow) Rd = ULL(0xFFFFFFFF80000000); 383 } }}, 384 {{0}}, 385 {{overflow || underflow}}, 386 {{0}}, 387 {{0}} 388 ); 389 0x20: taddcc({{ 390 int64_t resTemp, val2 = Rs2_or_imm13; 391 Rd = resTemp = Rs1 + val2; 392 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 393 {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 394 {{overflow}}, 395 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 396 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 397 ); 398 0x21: tsubcc({{ 399 int64_t resTemp, val2 = Rs2_or_imm13; 400 Rd = resTemp = Rs1 + val2; 401 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 402 {{(Rs1<31:0> + val2<31:0>)<32:0>}}, 403 {{overflow}}, 404 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 405 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 406 ); 407 0x22: taddcctv({{ 408 int64_t val2 = Rs2_or_imm13; 409 Rd = Rs1 + val2; 410 int32_t overflow = Rs1<1:0> || val2<1:0> || 411 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 412 if(overflow) fault = new TagOverflow;}}, 413 {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 414 {{overflow}}, 415 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 416 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} 417 ); 418 0x23: tsubcctv({{ 419 int64_t resTemp, val2 = Rs2_or_imm13; 420 Rd = resTemp = Rs1 + val2; 421 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 422 if(overflow) fault = new TagOverflow;}}, 423 {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 424 {{overflow}}, 425 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 426 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 427 ); 428 0x24: mulscc({{ 429 int64_t resTemp, multiplicand = Rs2_or_imm13; 430 int32_t multiplier = Rs1<31:0>; 431 int32_t savedLSB = Rs1<0:>; 432 multiplier = multiplier<31:1> | 433 ((Ccr<3:3> ^ Ccr<1:1>) << 32); 434 if(!Y<0:>) 435 multiplicand = 0; 436 Rd = resTemp = multiplicand + multiplier; 437 Y = Y<31:1> | (savedLSB << 31);}}, 438 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}}, 439 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 440 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 441 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 442 ); 443 } 444 format IntOp 445 { 446 0x25: decode X { 447 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 448 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 449 } 450 0x26: decode X { 451 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 452 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 453 } 454 0x27: decode X { 455 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 456 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 457 } 458 0x28: decode RS1 { 459 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 460 //1 should cause an illegal instruction exception 461 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 462 0x03: NoPriv::rdasi({{Rd = Asi;}}); 463 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 464 0x05: NoPriv::rdpc({{ 465 if(Pstate<3:>) 466 Rd = (xc->readPC())<31:0>; 467 else 468 Rd = xc->readPC();}}); 469 0x06: NoPriv::rdfprs({{ 470 //Wait for all fpops to finish. 471 Rd = Fprs; 472 }}); 473 //7-14 should cause an illegal instruction exception 474 0x0F: decode I { 475 0x0: Nop::stbar({{/*stuff*/}}); 476 0x1: Nop::membar({{/*stuff*/}}); 477 } 478 0x10: Priv::rdpcr({{Rd = Pcr;}}); 479 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 480 //0x12 should cause an illegal instruction exception 481 0x13: NoPriv::rdgsr({{ 482 if(Fprs<2:> == 0 || Pstate<4:> == 0) 483 Rd = Gsr; 484 else 485 fault = new FpDisabled; 486 }}); 487 //0x14-0x15 should cause an illegal instruction exception 488 0x16: Priv::rdsoftint({{Rd = Softint;}}); 489 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 490 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 491 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 492 0x1A: Priv::rdstrand_sts_reg({{ 493 if(Pstate<2:> && !Hpstate<2:>) 494 Rd = StrandStsReg<0:>; 495 else 496 Rd = StrandStsReg; 497 }}); 498 //0x1A is supposed to be reserved, but it reads the strand 499 //status register. 500 //0x1B-0x1F should cause an illegal instruction exception 501 } 502 0x29: decode RS1 { 503 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 504 0x01: HPriv::rdhprhtstate({{ 505 if(Tl == 0) 506 return new IllegalInstruction; 507 Rd = Htstate; 508 }}); 509 //0x02 should cause an illegal instruction exception 510 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 511 //0x04 should cause an illegal instruction exception 512 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 513 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 514 //0x07-0x1E should cause an illegal instruction exception 515 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 516 } 517 0x2A: decode RS1 { 518 0x00: Priv::rdprtpc({{ 519 if(Tl == 0) 520 return new IllegalInstruction; 521 Rd = Tpc; 522 }}); 523 0x01: Priv::rdprtnpc({{ 524 if(Tl == 0) 525 return new IllegalInstruction; 526 Rd = Tnpc; 527 }}); 528 0x02: Priv::rdprtstate({{ 529 if(Tl == 0) 530 return new IllegalInstruction; 531 Rd = Tstate; 532 }}); 533 0x03: Priv::rdprtt({{ 534 if(Tl == 0) 535 return new IllegalInstruction; 536 Rd = Tt; 537 }}); 538 0x04: Priv::rdprtick({{Rd = Tick;}}); 539 0x05: Priv::rdprtba({{Rd = Tba;}}); 540 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 541 0x07: Priv::rdprtl({{Rd = Tl;}}); 542 0x08: Priv::rdprpil({{Rd = Pil;}}); 543 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 544 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 545 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 546 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 547 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 548 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 549 //0x0F should cause an illegal instruction exception 550 0x10: Priv::rdprgl({{Rd = Gl;}}); 551 //0x11-0x1F should cause an illegal instruction exception 552 } 553 0x2B: BasicOperate::flushw({{ 554 if(NWindows - 2 - Cansave != 0) 555 { 556 if(Otherwin) 557 fault = new SpillNOther(4*Wstate<5:3>); 558 else 559 fault = new SpillNNormal(4*Wstate<2:0>); 560 } 561 }}); 562 0x2C: decode MOVCC3 563 { 564 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 565 0x1: decode CC 566 { 567 0x0: movcci({{ 568 if(passesCondition(Ccr<3:0>, COND4)) 569 Rd = Rs2_or_imm11; 570 else 571 Rd = Rd; 572 }}); 573 0x2: movccx({{ 574 if(passesCondition(Ccr<7:4>, COND4)) 575 Rd = Rs2_or_imm11; 576 else 577 Rd = Rd; 578 }}); 579 } 580 } 581 0x2D: sdivx({{ 582 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 583 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 584 }}); 585 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 586 0x2F: decode RCOND3 587 { 588 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 589 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 590 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 591 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 592 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 593 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 594 } 595 0x30: decode RD { 596 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 597 //0x01 should cause an illegal instruction exception 598 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 599 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 600 //0x04-0x05 should cause an illegal instruction exception 601 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 602 //0x07-0x0E should cause an illegal instruction exception 603 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 604 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 605 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 606 //0x12 should cause an illegal instruction exception 607 0x13: NoPriv::wrgsr({{ 608 if(Fprs<2:> == 0 || Pstate<4:> == 0) 609 return new FpDisabled; 610 Gsr = Rs1 ^ Rs2_or_imm13; 611 }}); 612 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 613 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 614 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 615 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 616 0x18: NoPriv::wrstick({{ 617 if(!Hpstate<2:>) 618 return new IllegalInstruction; 619 Stick = Rs1 ^ Rs2_or_imm13; 620 }}); 621 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 622 0x1A: Priv::wrstrand_sts_reg({{ 623 if(Pstate<2:> && !Hpstate<2:>) 624 StrandStsReg = StrandStsReg<63:1> | 625 (Rs1 ^ Rs2_or_imm13)<0:>; 626 else 627 StrandStsReg = Rs1 ^ Rs2_or_imm13; 628 }}); 629 //0x1A is supposed to be reserved, but it writes the strand 630 //status register. 631 //0x1B-0x1F should cause an illegal instruction exception 632 } 633 0x31: decode FCN { 634 0x0: Priv::saved({{ 635 assert(Cansave < NWindows - 2); 636 assert(Otherwin || Canrestore); 637 Cansave = Cansave + 1; 638 if(Otherwin == 0) 639 Canrestore = Canrestore - 1; 640 else 641 Otherwin = Otherwin - 1; 642 }}); 643 0x1: Priv::restored({{ 644 assert(Cansave || Otherwin); 645 assert(Canrestore < NWindows - 2); 646 Canrestore = Canrestore + 1; 647 if(Otherwin == 0) 648 Cansave = Cansave - 1; 649 else 650 Otherwin = Otherwin - 1; 651 652 if(Cleanwin < NWindows - 1) 653 Cleanwin = Cleanwin + 1; 654 }}); 655 } 656 0x32: decode RD { 657 0x00: Priv::wrprtpc({{ 658 if(Tl == 0) 659 return new IllegalInstruction; 660 else 661 Tpc = Rs1 ^ Rs2_or_imm13; 662 }}); 663 0x01: Priv::wrprtnpc({{ 664 if(Tl == 0) 665 return new IllegalInstruction; 666 else 667 Tnpc = Rs1 ^ Rs2_or_imm13; 668 }}); 669 0x02: Priv::wrprtstate({{ 670 if(Tl == 0) 671 return new IllegalInstruction; 672 else 673 Tstate = Rs1 ^ Rs2_or_imm13; 674 }}); 675 0x03: Priv::wrprtt({{ 676 if(Tl == 0) 677 return new IllegalInstruction; 678 else 679 Tt = Rs1 ^ Rs2_or_imm13; 680 }}); 681 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 682 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 683 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 684 0x07: Priv::wrprtl({{ 685 if(Pstate<2:> && !Hpstate<2:>) 686 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 687 else 688 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 689 }}); 690 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 691 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 692 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 693 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 694 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 695 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 696 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 697 //0x0F should cause an illegal instruction exception 698 0x10: Priv::wrprgl({{ 699 if(Pstate<2:> && !Hpstate<2:>) 700 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 701 else 702 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 703 }}); 704 //0x11-0x1F should cause an illegal instruction exception 705 } 706 0x33: decode RD { 707 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 708 0x01: HPriv::wrhprhtstate({{ 709 if(Tl == 0) 710 return new IllegalInstruction; 711 Htstate = Rs1 ^ Rs2_or_imm13; 712 }}); 713 //0x02 should cause an illegal instruction exception 714 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 715 //0x04 should cause an illegal instruction exception 716 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 717 //0x06-0x01D should cause an illegal instruction exception 718 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 719 } 720 0x34: decode OPF{ 721 format BasicOperate{ 722 0x01: fmovs({{ 723 Frds.uw = Frs2s.uw; 724 //fsr.ftt = fsr.cexc = 0 725 Fsr &= ~(7 << 14); 726 Fsr &= ~(0x1F); 727 }}); 728 0x02: fmovd({{ 729 Frd.udw = Frs2.udw; 730 //fsr.ftt = fsr.cexc = 0 731 Fsr &= ~(7 << 14); 732 Fsr &= ~(0x1F); 733 }}); 734 0x03: FpUnimpl::fmovq(); 735 0x05: fnegs({{ 736 Frds.uw = Frs2s.uw ^ (1UL << 31); 737 //fsr.ftt = fsr.cexc = 0 738 Fsr &= ~(7 << 14); 739 Fsr &= ~(0x1F); 740 }}); 741 0x06: fnegd({{ 742 Frd.udw = Frs2.udw ^ (1ULL << 63); 743 //fsr.ftt = fsr.cexc = 0 744 Fsr &= ~(7 << 14); 745 Fsr &= ~(0x1F); 746 }}); 747 0x07: FpUnimpl::fnegq(); 748 0x09: fabss({{ 749 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; 750 //fsr.ftt = fsr.cexc = 0 751 Fsr &= ~(7 << 14); 752 Fsr &= ~(0x1F); 753 }}); 754 0x0A: fabsd({{ 755 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 756 //fsr.ftt = fsr.cexc = 0 757 Fsr &= ~(7 << 14); 758 Fsr &= ~(0x1F); 759 }}); 760 0x0B: FpUnimpl::fabsq(); 761 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 762 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 763 0x2B: FpUnimpl::fsqrtq(); 764 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 765 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 766 0x43: FpUnimpl::faddq(); 767 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 768 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}}); 769 0x47: FpUnimpl::fsubq(); 770 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 771 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 772 0x4B: FpUnimpl::fmulq(); 773 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 774 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 775 0x4F: FpUnimpl::fdivq(); 776 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 777 0x6E: FpUnimpl::fdmulq(); 778 0x81: fstox({{ 779 Frd.df = (double)static_cast<int64_t>(Frs2s.sf); 780 }}); 781 0x82: fdtox({{ 782 Frd.df = (double)static_cast<int64_t>(Frs2.df); 783 }}); 784 0x83: FpUnimpl::fqtox(); 785 0x84: fxtos({{ 786 Frds.sf = static_cast<float>((int64_t)Frs2.df); 787 }}); 788 0x88: fxtod({{ 789 Frd.df = static_cast<double>((int64_t)Frs2.df); 790 }}); 791 0x8C: FpUnimpl::fxtoq(); 792 0xC4: fitos({{ 793 Frds.sf = static_cast<float>((int32_t)Frs2s.sf); 794 }}); 795 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 796 0xC7: FpUnimpl::fqtos(); 797 0xC8: fitod({{ 798 Frd.df = static_cast<double>((int32_t)Frs2s.sf); 799 }}); 800 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 801 0xCB: FpUnimpl::fqtod(); 802 0xCC: FpUnimpl::fitoq(); 803 0xCD: FpUnimpl::fstoq(); 804 0xCE: FpUnimpl::fdtoq(); 805 0xD1: fstoi({{ 806 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf); 807 }}); 808 0xD2: fdtoi({{ 809 Frds.sf = (float)static_cast<int32_t>(Frs2.df); 810 }}); 811 0xD3: FpUnimpl::fqtoi(); 812 default: FailUnimpl::fpop1(); 813 } 814 } 815 0x35: decode OPF{ 816 format BasicOperate{ 817 0x51: fcmps({{ 818 uint8_t fcc; 819 if(isnan(Frs1s) || isnan(Frs2s)) 820 fcc = 3; 821 else if(Frs1s < Frs2s) 822 fcc = 1; 823 else if(Frs1s > Frs2s) 824 fcc = 2; 825 else 826 fcc = 0; 827 uint8_t firstbit = 10; 828 if(FCMPCC) 829 firstbit = FCMPCC * 2 + 30; 830 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 831 }}); 832 0x52: fcmpd({{ 833 uint8_t fcc; 834 if(isnan(Frs1s) || isnan(Frs2s)) 835 fcc = 3; 836 else if(Frs1s < Frs2s) 837 fcc = 1; 838 else if(Frs1s > Frs2s) 839 fcc = 2; 840 else 841 fcc = 0; 842 uint8_t firstbit = 10; 843 if(FCMPCC) 844 firstbit = FCMPCC * 2 + 30; 845 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 846 }}); 847 0x53: FpUnimpl::fcmpq(); 848 0x55: fcmpes({{ 849 uint8_t fcc = 0; 850 if(isnan(Frs1s) || isnan(Frs2s)) 851 fault = new FpExceptionIEEE754; 852 if(Frs1s < Frs2s) 853 fcc = 1; 854 else if(Frs1s > Frs2s) 855 fcc = 2; 856 uint8_t firstbit = 10; 857 if(FCMPCC) 858 firstbit = FCMPCC * 2 + 30; 859 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 860 }}); 861 0x56: fcmped({{ 862 uint8_t fcc = 0; 863 if(isnan(Frs1s) || isnan(Frs2s)) 864 fault = new FpExceptionIEEE754; 865 if(Frs1s < Frs2s) 866 fcc = 1; 867 else if(Frs1s > Frs2s) 868 fcc = 2; 869 uint8_t firstbit = 10; 870 if(FCMPCC) 871 firstbit = FCMPCC * 2 + 30; 872 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 873 }}); 874 0x57: FpUnimpl::fcmpeq(); 875 default: FailUnimpl::fpop2(); 876 } 877 } 878 //This used to be just impdep1, but now it's a whole bunch 879 //of instructions 880 0x36: decode OPF{ 881 0x00: FailUnimpl::edge8(); 882 0x01: FailUnimpl::edge8n(); 883 0x02: FailUnimpl::edge8l(); 884 0x03: FailUnimpl::edge8ln(); 885 0x04: FailUnimpl::edge16(); 886 0x05: FailUnimpl::edge16n(); 887 0x06: FailUnimpl::edge16l(); 888 0x07: FailUnimpl::edge16ln(); 889 0x08: FailUnimpl::edge32(); 890 0x09: FailUnimpl::edge32n(); 891 0x0A: FailUnimpl::edge32l(); 892 0x0B: FailUnimpl::edge32ln(); 893 0x10: FailUnimpl::array8(); 894 0x12: FailUnimpl::array16(); 895 0x14: FailUnimpl::array32(); 896 0x18: BasicOperate::alignaddr({{ 897 uint64_t sum = Rs1 + Rs2; 898 Rd = sum & ~7; 899 Gsr = (Gsr & ~7) | (sum & 7); 900 }}); 901 0x19: FailUnimpl::bmask(); 902 0x1A: BasicOperate::alignaddresslittle({{ 903 uint64_t sum = Rs1 + Rs2; 904 Rd = sum & ~7; 905 Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 906 }}); 907 0x20: FailUnimpl::fcmple16(); 908 0x22: FailUnimpl::fcmpne16(); 909 0x24: FailUnimpl::fcmple32(); 910 0x26: FailUnimpl::fcmpne32(); 911 0x28: FailUnimpl::fcmpgt16(); 912 0x2A: FailUnimpl::fcmpeq16(); 913 0x2C: FailUnimpl::fcmpgt32(); 914 0x2E: FailUnimpl::fcmpeq32(); 915 0x31: FailUnimpl::fmul8x16(); 916 0x33: FailUnimpl::fmul8x16au(); 917 0x35: FailUnimpl::fmul8x16al(); 918 0x36: FailUnimpl::fmul8sux16(); 919 0x37: FailUnimpl::fmul8ulx16(); 920 0x38: FailUnimpl::fmuld8sux16(); 921 0x39: FailUnimpl::fmuld8ulx16(); 922 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 923 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 924 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 925 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 926 0x48: BasicOperate::faligndata({{ 927 uint64_t msbX = Frs1.udw; 928 uint64_t lsbX = Frs2.udw; 929 //Some special cases need to be split out, first 930 //because they're the most likely to be used, and 931 //second because otherwise, we end up shifting by 932 //greater than the width of the type being shifted, 933 //namely 64, which produces undefined results according 934 //to the C standard. 935 switch(Gsr<2:0>) 936 { 937 case 0: 938 Frd.udw = msbX; 939 break; 940 case 8: 941 Frd.udw = lsbX; 942 break; 943 default: 944 uint64_t msbShift = Gsr<2:0> * 8; 945 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 946 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 947 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 948 Frd.udw = ((msbX & msbMask) << msbShift) | 949 ((lsbX & lsbMask) >> lsbShift); 950 } 951 }}); 952 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 953 0x4C: FailUnimpl::bshuffle(); 954 0x4D: FailUnimpl::fexpand(); 955 0x50: FailUnimpl::fpadd16(); 956 0x51: FailUnimpl::fpadd16s(); 957 0x52: FailUnimpl::fpadd32(); 958 0x53: FailUnimpl::fpadd32s(); 959 0x54: FailUnimpl::fpsub16(); 960 0x55: FailUnimpl::fpsub16s(); 961 0x56: FailUnimpl::fpsub32(); 962 0x57: FailUnimpl::fpsub32s(); 963 0x60: BasicOperate::fzero({{Frd.df = 0;}}); 964 0x61: BasicOperate::fzeros({{Frds.sf = 0;}}); 965 0x62: FailUnimpl::fnor(); 966 0x63: FailUnimpl::fnors(); 967 0x64: FailUnimpl::fandnot2(); 968 0x65: FailUnimpl::fandnot2s(); 969 0x66: BasicOperate::fnot2({{ 970 Frd.df = (double)(~((uint64_t)Frs2.df)); 971 }}); 972 0x67: BasicOperate::fnot2s({{ 973 Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 974 }}); 975 0x68: FailUnimpl::fandnot1(); 976 0x69: FailUnimpl::fandnot1s(); 977 0x6A: BasicOperate::fnot1({{ 978 Frd.df = (double)(~((uint64_t)Frs1.df)); 979 }}); 980 0x6B: BasicOperate::fnot1s({{ 981 Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 982 }}); 983 0x6C: FailUnimpl::fxor(); 984 0x6D: FailUnimpl::fxors(); 985 0x6E: FailUnimpl::fnand(); 986 0x6F: FailUnimpl::fnands(); 987 0x70: FailUnimpl::fand(); 988 0x71: FailUnimpl::fands(); 989 0x72: FailUnimpl::fxnor(); 990 0x73: FailUnimpl::fxnors(); 991 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}}); 992 0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}}); 993 0x76: FailUnimpl::fornot2(); 994 0x77: FailUnimpl::fornot2s(); 995 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}}); 996 0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}}); 997 0x7A: FailUnimpl::fornot1(); 998 0x7B: FailUnimpl::fornot1s(); 999 0x7C: FailUnimpl::for(); 1000 0x7D: FailUnimpl::fors(); 1001 0x7E: BasicOperate::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 1002 0x7F: BasicOperate::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 1003 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 1004 0x81: FailUnimpl::siam(); 1005 } 1006 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 1007 0x38: Branch::jmpl({{ 1008 Addr target = Rs1 + Rs2_or_imm13; 1009 if(target & 0x3) 1010 fault = new MemAddressNotAligned; 1011 else 1012 { 1013 if (Pstate<3:>) 1014 Rd = (xc->readPC())<31:0>; 1015 else 1016 Rd = xc->readPC(); 1017 NNPC = target; 1018 } 1019 }}); 1020 0x39: Branch::return({{ 1021 Addr target = Rs1 + Rs2_or_imm13; 1022 if(fault == NoFault) 1023 { 1024 //Check for fills which are higher priority than alignment 1025 //faults. 1026 if(Canrestore == 0) 1027 { 1028 if(Otherwin) 1029 fault = new FillNOther(4*Wstate<5:3>); 1030 else 1031 fault = new FillNNormal(4*Wstate<2:0>); 1032 } 1033 //Check for alignment faults 1034 else if(target & 0x3) 1035 fault = new MemAddressNotAligned; 1036 else 1037 { 1038 NNPC = target; 1039 Cwp = (Cwp - 1 + NWindows) % NWindows; 1040 Cansave = Cansave + 1; 1041 Canrestore = Canrestore - 1; 1042 } 1043 } 1044 }}); 1045 0x3A: decode CC 1046 { 1047 0x0: Trap::tcci({{ 1048 if(passesCondition(Ccr<3:0>, COND2)) 1049 { 1050#if FULL_SYSTEM 1051 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1052 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1053 fault = new TrapInstruction(lTrapNum); 1054#else 1055 DPRINTF(Sparc, "The syscall number is %d\n", R1); 1056 xc->syscall(R1); 1057#endif 1058 } 1059 }}, IsSerializeAfter, IsNonSpeculative); 1060 0x2: Trap::tccx({{ 1061 if(passesCondition(Ccr<7:4>, COND2)) 1062 { 1063#if FULL_SYSTEM 1064 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1065 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1066 fault = new TrapInstruction(lTrapNum); 1067#else 1068 DPRINTF(Sparc, "The syscall number is %d\n", R1); 1069 xc->syscall(R1); 1070#endif 1071 } 1072 }}, IsSerializeAfter, IsNonSpeculative); 1073 } 1074 0x3B: Nop::flush({{/*Instruction memory flush*/}}); 1075 0x3C: save({{ 1076 if(Cansave == 0) 1077 { 1078 if(Otherwin) 1079 fault = new SpillNOther(4*Wstate<5:3>); 1080 else 1081 fault = new SpillNNormal(4*Wstate<2:0>); 1082 } 1083 else if(Cleanwin - Canrestore == 0) 1084 { 1085 fault = new CleanWindow; 1086 } 1087 else 1088 { 1089 Cwp = (Cwp + 1) % NWindows; 1090 Rd_next = Rs1 + Rs2_or_imm13; 1091 Cansave = Cansave - 1; 1092 Canrestore = Canrestore + 1; 1093 } 1094 }}); 1095 0x3D: restore({{ 1096 if(Canrestore == 0) 1097 { 1098 if(Otherwin) 1099 fault = new FillNOther(4*Wstate<5:3>); 1100 else 1101 fault = new FillNNormal(4*Wstate<2:0>); 1102 } 1103 else 1104 { 1105 Cwp = (Cwp - 1 + NWindows) % NWindows; 1106 Rd_prev = Rs1 + Rs2_or_imm13; 1107 Cansave = Cansave + 1; 1108 Canrestore = Canrestore - 1; 1109 } 1110 }}); 1111 0x3E: decode FCN { 1112 0x0: Priv::done({{ 1113 if(Tl == 0) 1114 return new IllegalInstruction; 1115 1116 Cwp = Tstate<4:0>; 1117 Pstate = Tstate<20:8>; 1118 Asi = Tstate<31:24>; 1119 Ccr = Tstate<39:32>; 1120 Gl = Tstate<42:40>; 1121 Hpstate = Htstate; 1122 NPC = Tnpc; 1123 NNPC = Tnpc + 4; 1124 Tl = Tl - 1; 1125 }}); 1126 0x1: Priv::retry({{ 1127 if(Tl == 0) 1128 return new IllegalInstruction; 1129 Cwp = Tstate<4:0>; 1130 Pstate = Tstate<20:8>; 1131 Asi = Tstate<31:24>; 1132 Ccr = Tstate<39:32>; 1133 Gl = Tstate<42:40>; 1134 Hpstate = Htstate; 1135 NPC = Tpc; 1136 NNPC = Tnpc; 1137 Tl = Tl - 1; 1138 }}); 1139 } 1140 } 1141 } 1142 0x3: decode OP3 { 1143 format Load { 1144 0x00: lduw({{Rd = Mem.uw;}}); 1145 0x01: ldub({{Rd = Mem.ub;}}); 1146 0x02: lduh({{Rd = Mem.uhw;}}); 1147 0x03: ldtw({{ 1148 uint64_t val = Mem.udw; 1149 RdLow = val<31:0>; 1150 RdHigh = val<63:32>; 1151 }}); 1152 } 1153 format Store { 1154 0x04: stw({{Mem.uw = Rd.sw;}}); 1155 0x05: stb({{Mem.ub = Rd.sb;}}); 1156 0x06: sth({{Mem.uhw = Rd.shw;}}); 1157 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}}); 1158 } 1159 format Load { 1160 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 1161 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 1162 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 1163 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 1164 } 1165 0x0D: LoadStore::ldstub( 1166 {{uReg0 = Mem.ub;}}, 1167 {{Rd.ub = uReg0; 1168 Mem.ub = 0xFF;}}); 1169 0x0E: Store::stx({{Mem.udw = Rd}}); 1170 0x0F: LoadStore::swap( 1171 {{ uReg0 = Mem.uw}}, 1172 {{ Mem.uw = Rd.uw; 1173 Rd.uw = uReg0;}}); 1174 format LoadAlt { 1175 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 1176 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 1177 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 1178 0x13: decode EXT_ASI { 1179 //ASI_LDTD_AIUP 1180 0x22: TwinLoad::ldtx_aiup( 1181 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); 1182 //ASI_LDTD_AIUS 1183 0x23: TwinLoad::ldtx_aius( 1184 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); 1185 //ASI_QUAD_LDD 1186 0x24: TwinLoad::ldtx_quad_ldd( 1187 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); 1188 //ASI_LDTX_REAL 1189 0x26: TwinLoad::ldtx_real( 1190 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); 1191 //ASI_LDTX_N 1192 0x27: TwinLoad::ldtx_n( 1193 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); 1194 //ASI_LDTX_L 1195 0x2C: TwinLoad::ldtx_l( 1196 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); 1197 //ASI_LDTX_REAL_L 1198 0x2E: TwinLoad::ldtx_real_l( 1199 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); 1200 //ASI_LDTX_N_L 1201 0x2F: TwinLoad::ldtx_n_l( 1202 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); 1203 //ASI_LDTX_P 1204 0xE2: TwinLoad::ldtx_p( 1205 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); 1206 //ASI_LDTX_S 1207 0xE3: TwinLoad::ldtx_s( 1208 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); 1209 default: ldtwa({{ 1210 uint64_t val = Mem.udw; 1211 RdLow = val<31:0>; 1212 RdHigh = val<63:32>; 1213 }}, {{EXT_ASI}}); 1214 } 1215 } 1216 format StoreAlt { 1217 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 1218 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 1219 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 1220 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}}); 1221 } 1222 format LoadAlt { 1223 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 1224 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 1225 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 1226 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); 1227 } 1228 0x1D: LoadStoreAlt::ldstuba( 1229 {{uReg0 = Mem.ub;}}, 1230 {{Rd.ub = uReg0; 1231 Mem.ub = 0xFF;}}, {{EXT_ASI}}); 1232 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 1233 0x1F: LoadStoreAlt::swapa( 1234 {{ uReg0 = Mem.uw}}, 1235 {{ Mem.uw = Rd.uw; 1236 Rd.uw = uReg0;}}, {{EXT_ASI}}); 1237 format Trap { 1238 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 1239 0x21: decode X { 1240 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 1241 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); 1242 } 1243 0x22: ldqf({{fault = new FpDisabled;}}); 1244 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1245 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 1246 0x25: decode X { 1247 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 1248 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); 1249 } 1250 0x26: stqf({{fault = new FpDisabled;}}); 1251 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1252 0x2D: Nop::prefetch({{ }}); 1253 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); 1254 0x32: ldqfa({{fault = new FpDisabled;}}); 1255 format LoadAlt { 1256 0x33: decode EXT_ASI { 1257 //ASI_NUCLEUS 1258 0x04: FailUnimpl::lddfa_n(); 1259 //ASI_NUCLEUS_LITTLE 1260 0x0C: FailUnimpl::lddfa_nl(); 1261 //ASI_AS_IF_USER_PRIMARY 1262 0x10: FailUnimpl::lddfa_aiup(); 1263 //ASI_AS_IF_USER_PRIMARY_LITTLE 1264 0x18: FailUnimpl::lddfa_aiupl(); 1265 //ASI_AS_IF_USER_SECONDARY 1266 0x11: FailUnimpl::lddfa_aius(); 1267 //ASI_AS_IF_USER_SECONDARY_LITTLE 1268 0x19: FailUnimpl::lddfa_aiusl(); 1269 //ASI_REAL 1270 0x14: FailUnimpl::lddfa_real(); 1271 //ASI_REAL_LITTLE 1272 0x1C: FailUnimpl::lddfa_real_l(); 1273 //ASI_REAL_IO 1274 0x15: FailUnimpl::lddfa_real_io(); 1275 //ASI_REAL_IO_LITTLE 1276 0x1D: FailUnimpl::lddfa_real_io_l(); 1277 //ASI_PRIMARY 1278 0x80: FailUnimpl::lddfa_p(); 1279 //ASI_PRIMARY_LITTLE 1280 0x88: FailUnimpl::lddfa_pl(); 1281 //ASI_SECONDARY 1282 0x81: FailUnimpl::lddfa_s(); 1283 //ASI_SECONDARY_LITTLE 1284 0x89: FailUnimpl::lddfa_sl(); 1285 //ASI_PRIMARY_NO_FAULT 1286 0x82: FailUnimpl::lddfa_pnf(); 1287 //ASI_PRIMARY_NO_FAULT_LITTLE 1288 0x8A: FailUnimpl::lddfa_pnfl(); 1289 //ASI_SECONDARY_NO_FAULT 1290 0x83: FailUnimpl::lddfa_snf(); 1291 //ASI_SECONDARY_NO_FAULT_LITTLE 1292 0x8B: FailUnimpl::lddfa_snfl(); 1293 1294 format BlockLoad { 1295 // LDBLOCKF 1296 //ASI_BLOCK_AS_IF_USER_PRIMARY 1297 0x16: FailUnimpl::ldblockf_aiup(); 1298 //ASI_BLOCK_AS_IF_USER_SECONDARY 1299 0x17: FailUnimpl::ldblockf_aius(); 1300 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1301 0x1E: FailUnimpl::ldblockf_aiupl(); 1302 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1303 0x1F: FailUnimpl::ldblockf_aiusl(); 1304 //ASI_BLOCK_PRIMARY 1305 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); 1306 //ASI_BLOCK_SECONDARY 1307 0xF1: FailUnimpl::ldblockf_s(); 1308 //ASI_BLOCK_PRIMARY_LITTLE 1309 0xF8: FailUnimpl::ldblockf_pl(); 1310 //ASI_BLOCK_SECONDARY_LITTLE 1311 0xF9: FailUnimpl::ldblockf_sl(); 1312 } 1313 1314 //LDSHORTF 1315 //ASI_FL8_PRIMARY 1316 0xD0: FailUnimpl::ldshortf_8p(); 1317 //ASI_FL8_SECONDARY 1318 0xD1: FailUnimpl::ldshortf_8s(); 1319 //ASI_FL8_PRIMARY_LITTLE 1320 0xD8: FailUnimpl::ldshortf_8pl(); 1321 //ASI_FL8_SECONDARY_LITTLE 1322 0xD9: FailUnimpl::ldshortf_8sl(); 1323 //ASI_FL16_PRIMARY 1324 0xD2: FailUnimpl::ldshortf_16p(); 1325 //ASI_FL16_SECONDARY 1326 0xD3: FailUnimpl::ldshortf_16s(); 1327 //ASI_FL16_PRIMARY_LITTLE 1328 0xDA: FailUnimpl::ldshortf_16pl(); 1329 //ASI_FL16_SECONDARY_LITTLE 1330 0xDB: FailUnimpl::ldshortf_16sl(); 1331 //Not an ASI which is legal with lddfa 1332 default: Trap::lddfa_bad_asi( 1333 {{fault = new DataAccessException;}}); 1334 } 1335 } 1336 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 1337 0x36: stqfa({{fault = new FpDisabled;}}); 1338 format StoreAlt { 1339 0x37: decode EXT_ASI { 1340 //ASI_NUCLEUS 1341 0x04: FailUnimpl::stdfa_n(); 1342 //ASI_NUCLEUS_LITTLE 1343 0x0C: FailUnimpl::stdfa_nl(); 1344 //ASI_AS_IF_USER_PRIMARY 1345 0x10: FailUnimpl::stdfa_aiup(); 1346 //ASI_AS_IF_USER_PRIMARY_LITTLE 1347 0x18: FailUnimpl::stdfa_aiupl(); 1348 //ASI_AS_IF_USER_SECONDARY 1349 0x11: FailUnimpl::stdfa_aius(); 1350 //ASI_AS_IF_USER_SECONDARY_LITTLE 1351 0x19: FailUnimpl::stdfa_aiusl(); 1352 //ASI_REAL 1353 0x14: FailUnimpl::stdfa_real(); 1354 //ASI_REAL_LITTLE 1355 0x1C: FailUnimpl::stdfa_real_l(); 1356 //ASI_REAL_IO 1357 0x15: FailUnimpl::stdfa_real_io(); 1358 //ASI_REAL_IO_LITTLE 1359 0x1D: FailUnimpl::stdfa_real_io_l(); 1360 //ASI_PRIMARY 1361 0x80: FailUnimpl::stdfa_p(); 1362 //ASI_PRIMARY_LITTLE 1363 0x88: FailUnimpl::stdfa_pl(); 1364 //ASI_SECONDARY 1365 0x81: FailUnimpl::stdfa_s(); 1366 //ASI_SECONDARY_LITTLE 1367 0x89: FailUnimpl::stdfa_sl(); 1368 //ASI_PRIMARY_NO_FAULT 1369 0x82: FailUnimpl::stdfa_pnf(); 1370 //ASI_PRIMARY_NO_FAULT_LITTLE 1371 0x8A: FailUnimpl::stdfa_pnfl(); 1372 //ASI_SECONDARY_NO_FAULT 1373 0x83: FailUnimpl::stdfa_snf(); 1374 //ASI_SECONDARY_NO_FAULT_LITTLE 1375 0x8B: FailUnimpl::stdfa_snfl(); 1376 1377 format BlockStore { 1378 // STBLOCKF 1379 //ASI_BLOCK_AS_IF_USER_PRIMARY 1380 0x16: FailUnimpl::stblockf_aiup(); 1381 //ASI_BLOCK_AS_IF_USER_SECONDARY 1382 0x17: FailUnimpl::stblockf_aius(); 1383 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1384 0x1E: FailUnimpl::stblockf_aiupl(); 1385 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1386 0x1F: FailUnimpl::stblockf_aiusl(); 1387 //ASI_BLOCK_PRIMARY 1388 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); 1389 //ASI_BLOCK_SECONDARY 1390 0xF1: FailUnimpl::stblockf_s(); 1391 //ASI_BLOCK_PRIMARY_LITTLE 1392 0xF8: FailUnimpl::stblockf_pl(); 1393 //ASI_BLOCK_SECONDARY_LITTLE 1394 0xF9: FailUnimpl::stblockf_sl(); 1395 } 1396 1397 //STSHORTF 1398 //ASI_FL8_PRIMARY 1399 0xD0: FailUnimpl::stshortf_8p(); 1400 //ASI_FL8_SECONDARY 1401 0xD1: FailUnimpl::stshortf_8s(); 1402 //ASI_FL8_PRIMARY_LITTLE 1403 0xD8: FailUnimpl::stshortf_8pl(); 1404 //ASI_FL8_SECONDARY_LITTLE 1405 0xD9: FailUnimpl::stshortf_8sl(); 1406 //ASI_FL16_PRIMARY 1407 0xD2: FailUnimpl::stshortf_16p(); 1408 //ASI_FL16_SECONDARY 1409 0xD3: FailUnimpl::stshortf_16s(); 1410 //ASI_FL16_PRIMARY_LITTLE 1411 0xDA: FailUnimpl::stshortf_16pl(); 1412 //ASI_FL16_SECONDARY_LITTLE 1413 0xDB: FailUnimpl::stshortf_16sl(); 1414 //Not an ASI which is legal with lddfa 1415 default: Trap::stdfa_bad_asi( 1416 {{fault = new DataAccessException;}}); 1417 } 1418 } 1419 0x3C: Cas::casa( 1420 {{uReg0 = Mem.uw;}}, 1421 {{if(Rs2.uw == uReg0) 1422 Mem.uw = Rd.uw; 1423 else 1424 storeCond = false; 1425 Rd.uw = uReg0;}}, {{EXT_ASI}}); 1426 0x3D: Nop::prefetcha({{ }}); 1427 0x3E: Cas::casxa( 1428 {{uReg0 = Mem.udw;}}, 1429 {{if(Rs2 == uReg0) 1430 Mem.udw = Rd; 1431 else 1432 storeCond = false; 1433 Rd = uReg0;}}, {{EXT_ASI}}); 1434 } 1435 } 1436} 1437