decoder.isa revision 2974:cc78d60b5698
1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 //Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 format BranchN 43 { 44 0x1: decode BPCC 45 { 46 0x0: bpcci(19, {{ 47 if(passesCondition(Ccr<3:0>, COND2)) 48 NNPC = xc->readPC() + disp; 49 else 50 handle_annul 51 }}); 52 0x2: bpccx(19, {{ 53 if(passesCondition(Ccr<7:4>, COND2)) 54 NNPC = xc->readPC() + disp; 55 else 56 handle_annul 57 }}); 58 } 59 0x2: bicc(22, {{ 60 if(passesCondition(Ccr<3:0>, COND2)) 61 NNPC = xc->readPC() + disp; 62 else 63 handle_annul 64 }}); 65 } 66 0x3: decode RCOND2 67 { 68 format BranchSplit 69 { 70 0x1: bpreq({{ 71 if(Rs1.sdw == 0) 72 NNPC = xc->readPC() + disp; 73 else 74 handle_annul 75 }}); 76 0x2: bprle({{ 77 if(Rs1.sdw <= 0) 78 NNPC = xc->readPC() + disp; 79 else 80 handle_annul 81 }}); 82 0x3: bprl({{ 83 if(Rs1.sdw < 0) 84 NNPC = xc->readPC() + disp; 85 else 86 handle_annul 87 }}); 88 0x5: bprne({{ 89 if(Rs1.sdw != 0) 90 NNPC = xc->readPC() + disp; 91 else 92 handle_annul 93 }}); 94 0x6: bprg({{ 95 if(Rs1.sdw > 0) 96 NNPC = xc->readPC() + disp; 97 else 98 handle_annul 99 }}); 100 0x7: bprge({{ 101 if(Rs1.sdw >= 0) 102 NNPC = xc->readPC() + disp; 103 else 104 handle_annul 105 }}); 106 } 107 } 108 //SETHI (or NOP if rd == 0 and imm == 0) 109 0x4: SetHi::sethi({{Rd = imm;}}); 110 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 111 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 112 } 113 0x1: BranchN::call(30, {{ 114 R15 = xc->readPC(); 115 NNPC = R15 + disp; 116 }}); 117 0x2: decode OP3 { 118 format IntOp { 119 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 120 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 121 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 122 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 123 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 124 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 125 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 126 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 127 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 128 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 129 0x0A: umul({{ 130 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 131 Y = Rd<63:32>; 132 }}); 133 0x0B: smul({{ 134 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; 135 Y = Rd.sdw; 136 }}); 137 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 138 0x0D: udivx({{ 139 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 140 else Rd.udw = Rs1.udw / Rs2_or_imm13; 141 }}); 142 0x0E: udiv({{ 143 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 144 else 145 { 146 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 147 if(Rd.udw >> 32 != 0) 148 Rd.udw = 0xFFFFFFFF; 149 } 150 }}); 151 0x0F: sdiv({{ 152 if(Rs2_or_imm13.sdw == 0) 153 fault = new DivisionByZero; 154 else 155 { 156 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 157 if(Rd.udw<63:31> != 0) 158 Rd.udw = 0x7FFFFFFF; 159 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 160 Rd.udw = 0xFFFFFFFF80000000ULL; 161 } 162 }}); 163 } 164 format IntOpCc { 165 0x10: addcc({{ 166 int64_t resTemp, val2 = Rs2_or_imm13; 167 Rd = resTemp = Rs1 + val2;}}, 168 {{(Rs1<31:0> + val2<31:0>)<32:>}}, 169 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 170 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 171 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 172 ); 173 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 174 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 175 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 176 0x14: subcc({{ 177 int64_t val2 = Rs2_or_imm13; 178 Rd = Rs1 - val2;}}, 179 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 180 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 181 {{(~(Rs1<63:1> + (~val2)<63:1> + 182 (Rs1 | ~val2)<0:>))<63:>}}, 183 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 184 ); 185 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 186 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 187 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 188 0x18: addccc({{ 189 int64_t resTemp, val2 = Rs2_or_imm13; 190 int64_t carryin = Ccr<0:0>; 191 Rd = resTemp = Rs1 + val2 + carryin;}}, 192 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 193 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 194 {{(Rs1<63:1> + val2<63:1> + 195 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, 196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 197 ); 198 0x1A: umulcc({{ 199 uint64_t resTemp; 200 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 201 Y = resTemp<63:32>;}}, 202 {{0}},{{0}},{{0}},{{0}}); 203 0x1B: smulcc({{ 204 int64_t resTemp; 205 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; 206 Y = resTemp<63:32>;}}, 207 {{0}},{{0}},{{0}},{{0}}); 208 0x1C: subccc({{ 209 int64_t resTemp, val2 = Rs2_or_imm13; 210 int64_t carryin = Ccr<0:0>; 211 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 212 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, 213 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 214 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, 215 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 216 ); 217 0x1D: udivxcc({{ 218 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 219 else Rd = Rs1.udw / Rs2_or_imm13.udw;}} 220 ,{{0}},{{0}},{{0}},{{0}}); 221 0x1E: udivcc({{ 222 uint32_t resTemp, val2 = Rs2_or_imm13.udw; 223 int32_t overflow; 224 if(val2 == 0) fault = new DivisionByZero; 225 else 226 { 227 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 228 overflow = (resTemp<63:32> != 0); 229 if(overflow) Rd = resTemp = 0xFFFFFFFF; 230 else Rd = resTemp; 231 } }}, 232 {{0}}, 233 {{overflow}}, 234 {{0}}, 235 {{0}} 236 ); 237 0x1F: sdivcc({{ 238 int32_t resTemp, val2 = Rs2_or_imm13.sdw; 239 int32_t overflow, underflow; 240 if(val2 == 0) fault = new DivisionByZero; 241 else 242 { 243 Rd = resTemp = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 244 overflow = (resTemp<63:31> != 0); 245 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 246 if(overflow) Rd = resTemp = 0x7FFFFFFF; 247 else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000ULL; 248 else Rd = resTemp; 249 } }}, 250 {{0}}, 251 {{overflow || underflow}}, 252 {{0}}, 253 {{0}} 254 ); 255 0x20: taddcc({{ 256 int64_t resTemp, val2 = Rs2_or_imm13; 257 Rd = resTemp = Rs1 + val2; 258 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 259 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 260 {{overflow}}, 261 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 262 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 263 ); 264 0x21: tsubcc({{ 265 int64_t resTemp, val2 = Rs2_or_imm13; 266 Rd = resTemp = Rs1 + val2; 267 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 268 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, 269 {{overflow}}, 270 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 271 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 272 ); 273 0x22: taddcctv({{ 274 int64_t resTemp, val2 = Rs2_or_imm13; 275 Rd = Rs1 + val2; 276 int32_t overflow = Rs1<1:0> || val2<1:0> || 277 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 278 if(overflow) fault = new TagOverflow;}}, 279 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 280 {{overflow}}, 281 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 282 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 283 ); 284 0x23: tsubcctv({{ 285 int64_t resTemp, val2 = Rs2_or_imm13; 286 Rd = resTemp = Rs1 + val2; 287 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 288 if(overflow) fault = new TagOverflow;}}, 289 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 290 {{overflow}}, 291 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 292 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 293 ); 294 0x24: mulscc({{ 295 int64_t resTemp, multiplicand = Rs2_or_imm13; 296 int32_t multiplier = Rs1<31:0>; 297 int32_t savedLSB = Rs1<0:>; 298 multiplier = multiplier<31:1> | 299 ((Ccr<3:3> 300 ^ Ccr<1:1>) << 32); 301 if(!Y<0:>) 302 multiplicand = 0; 303 Rd = resTemp = multiplicand + multiplier; 304 Y = Y<31:1> | (savedLSB << 31);}}, 305 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 306 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 307 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 308 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 309 ); 310 } 311 format IntOp 312 { 313 0x25: decode X { 314 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 315 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 316 } 317 0x26: decode X { 318 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 319 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 320 } 321 0x27: decode X { 322 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 323 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 324 } 325 // XXX might want a format rdipr thing here 326 0x28: decode RS1 { 327 0xF: decode I { 328 0x0: Nop::stbar({{/*stuff*/}}); 329 0x1: Nop::membar({{/*stuff*/}}); 330 } 331 default: rdasr({{ 332 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault); 333 }}); 334 } 335 0x29: HPriv::rdhpr({{ 336 // XXX Need to protect with format that traps non-priv/priv 337 // access 338 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); 339 }}); 340 0x2A: Priv::rdpr({{ 341 // XXX Need to protect with format that traps non-priv 342 // access 343 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); 344 }}); 345 0x2B: BasicOperate::flushw({{ 346 if(NWindows - 2 - Cansave == 0) 347 { 348 if(Otherwin) 349 fault = new SpillNOther(Wstate<5:3>); 350 else 351 fault = new SpillNNormal(Wstate<2:0>); 352 } 353 }}); 354 0x2C: decode MOVCC3 355 { 356 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 357 0x1: decode CC 358 { 359 0x0: movcci({{ 360 if(passesCondition(Ccr<3:0>, COND4)) 361 Rd = Rs2_or_imm11; 362 else 363 Rd = Rd; 364 }}); 365 0x2: movccx({{ 366 if(passesCondition(Ccr<7:4>, COND4)) 367 Rd = Rs2_or_imm11; 368 else 369 Rd = Rd; 370 }}); 371 } 372 } 373 0x2D: sdivx({{ 374 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 375 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 376 }}); 377 0x2E: decode RS1 { 378 0x0: IntOp::popc({{ 379 int64_t count = 0; 380 uint64_t temp = Rs2_or_imm13; 381 //Count the 1s in the front 4bits until none are left 382 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 383 while(temp) 384 { 385 count += oneBits[temp & 0xF]; 386 temp = temp >> 4; 387 } 388 Rd = count; 389 }}); 390 } 391 0x2F: decode RCOND3 392 { 393 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 394 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 395 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 396 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 397 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 398 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 399 } 400 0x30: wrasr({{ 401 xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13); 402 }}); 403 0x31: decode FCN { 404 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 405 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); 406 } 407 0x32: Priv::wrpr({{ 408 // XXX Need to protect with format that traps non-priv 409 // access 410 fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); 411 }}); 412 0x33: HPriv::wrhpr({{ 413 // XXX Need to protect with format that traps non-priv/priv 414 // access 415 fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); 416 }}); 417 0x34: decode OPF{ 418 format BasicOperate{ 419 0x01: fmovs({{ 420 Frd.sf = Frs2.sf; 421 //fsr.ftt = fsr.cexc = 0 422 Fsr &= ~(7 << 14); 423 Fsr &= ~(0x1F); 424 }}); 425 0x02: fmovd({{ 426 Frd.df = Frs2.df; 427 //fsr.ftt = fsr.cexc = 0 428 Fsr &= ~(7 << 14); 429 Fsr &= ~(0x1F); 430 }}); 431 0x03: Trap::fmovq({{fault = new FpDisabled;}}); 432 0x05: fnegs({{ 433 //XXX might want to explicitly flip the sign bit 434 //So cases with Nan and +/-0 don't do weird things 435 Frd.sf = -Frs2.sf; 436 //fsr.ftt = fsr.cexc = 0 437 Fsr &= ~(7 << 14); 438 Fsr &= ~(0x1F); 439 }}); 440 0x06: fnegd({{ 441 //XXX might want to explicitly flip the sign bit 442 //So cases with Nan and +/-0 don't do weird things 443 Frd.df = -Frs2.df; 444 //fsr.ftt = fsr.cexc = 0 445 Fsr &= ~(7 << 14); 446 Fsr &= ~(0x1F); 447 }}); 448 0x07: Trap::fnegq({{fault = new FpDisabled;}}); 449 0x09: fabss({{ 450 //XXX this instruction should be tested individually 451 //Clear the sign bit 452 Frd.sf = (float)(~(1 << 31) & ((uint32_t)Frs2.sf)); 453 //fsr.ftt = fsr.cexc = 0 454 Fsr &= ~(7 << 14); 455 Fsr &= ~(0x1F); 456 }}); 457 0x0A: fabsd({{ 458 //XXX this instruction should be tested individually 459 //Clear the sign bit 460 Frd.df = (float)(~((uint64_t)1 << 63) & ((uint64_t)Frs2.df)); 461 //fsr.ftt = fsr.cexc = 0 462 Fsr &= ~(7 << 14); 463 Fsr &= ~(0x1F); 464 }}); 465 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); 466 0x29: fsqrts({{Frd.sf = sqrt(Frs2.sf);}}); 467 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}}); 468 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 469 0x41: fadds({{Frd.sf = Frs1.sf + Frs2.sf;}}); 470 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 471 0x43: Trap::faddq({{fault = new FpDisabled;}}); 472 0x45: fsubs({{Frd.sf = Frs1.sf - Frs2.sf;}}); 473 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}}); 474 0x47: Trap::fsubq({{fault = new FpDisabled;}}); 475 0x49: fmuls({{Frd.sf = Frs1.sf * Frs2.sf;}}); 476 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 477 0x4B: Trap::fmulq({{fault = new FpDisabled;}}); 478 0x4D: fdivs({{Frd.sf = Frs1.sf / Frs2.sf;}}); 479 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 480 0x4F: Trap::fdivq({{fault = new FpDisabled;}}); 481 0x69: fsmuld({{Frd.df = Frs1.sf * Frs2.sf;}}); 482 0x6E: Trap::fdmulq({{fault = new FpDisabled;}}); 483 0x81: fstox({{ 484 Frd.df = (double)static_cast<int64_t>(Frs2.sf); 485 }}); 486 0x82: fdtox({{ 487 Frd.df = (double)static_cast<int64_t>(Frs2.df); 488 }}); 489 0x83: Trap::fqtox({{fault = new FpDisabled;}}); 490 0x84: fxtos({{ 491 Frd.sf = static_cast<float>((int64_t)Frs2.df); 492 }}); 493 0x88: fxtod({{ 494 Frd.df = static_cast<double>((int64_t)Frs2.df); 495 }}); 496 0x8C: Trap::fxtoq({{fault = new FpDisabled;}}); 497 0xC4: fitos({{ 498 Frd.sf = static_cast<float>((int32_t)Frs2.sf); 499 }}); 500 0xC6: fdtos({{Frd.sf = Frs2.df;}}); 501 0xC7: Trap::fqtos({{fault = new FpDisabled;}}); 502 0xC8: fitod({{ 503 Frd.df = static_cast<double>((int32_t)Frs2.sf); 504 }}); 505 0xC9: fstod({{Frd.df = Frs2.sf;}}); 506 0xCB: Trap::fqtod({{fault = new FpDisabled;}}); 507 0xCC: Trap::fitoq({{fault = new FpDisabled;}}); 508 0xCD: Trap::fstoq({{fault = new FpDisabled;}}); 509 0xCE: Trap::fdtoq({{fault = new FpDisabled;}}); 510 0xD1: fstoi({{ 511 Frd.sf = (float)static_cast<int32_t>(Frs2.sf); 512 }}); 513 0xD2: fdtoi({{ 514 Frd.sf = (float)static_cast<int32_t>(Frs2.df); 515 }}); 516 0xD3: Trap::fqtoi({{fault = new FpDisabled;}}); 517 default: Trap::fpop1({{fault = new FpDisabled;}}); 518 } 519 } 520 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 521 //This used to be just impdep1, but now it's a whole bunch 522 //of instructions 523 0x36: decode OPF{ 524 0x00: Trap::edge8({{fault = new IllegalInstruction;}}); 525 0x01: Trap::edge8n({{fault = new IllegalInstruction;}}); 526 0x02: Trap::edge8l({{fault = new IllegalInstruction;}}); 527 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}}); 528 0x04: Trap::edge16({{fault = new IllegalInstruction;}}); 529 0x05: Trap::edge16n({{fault = new IllegalInstruction;}}); 530 0x06: Trap::edge16l({{fault = new IllegalInstruction;}}); 531 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}}); 532 0x08: Trap::edge32({{fault = new IllegalInstruction;}}); 533 0x09: Trap::edge32n({{fault = new IllegalInstruction;}}); 534 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}}); 535 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}}); 536 0x10: Trap::array8({{fault = new IllegalInstruction;}}); 537 0x12: Trap::array16({{fault = new IllegalInstruction;}}); 538 0x14: Trap::array32({{fault = new IllegalInstruction;}}); 539 0x18: BasicOperate::alignaddress({{ 540 uint64_t sum = Rs1 + Rs2; 541 Frd = sum & ~7; 542 Gsr = (Gsr & ~7) | (sum & 7); 543 }}); 544 0x19: Trap::bmask({{fault = new IllegalInstruction;}}); 545 0x1A: BasicOperate::alignaddresslittle({{ 546 uint64_t sum = Rs1 + Rs2; 547 Frd = sum & ~7; 548 Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 549 }}); 550 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}}); 551 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}}); 552 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}}); 553 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}}); 554 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}}); 555 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}}); 556 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}}); 557 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}}); 558 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}}); 559 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}}); 560 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}}); 561 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}}); 562 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}}); 563 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}}); 564 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}}); 565 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 566 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 567 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 568 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 569 0x48: BasicOperate::faligndata({{ 570 uint64_t msbX = (uint64_t)Frs1; 571 uint64_t lsbX = (uint64_t)Frs2; 572 uint64_t msbShift = Gsr<2:0> * 8; 573 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 574 uint64_t msbMask = ((uint64_t)(-1)) << msbShift; 575 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 576 Frd = ((msbX << msbShift) & msbMask) | 577 ((lsbX << lsbShift) & lsbMask); 578 }}); 579 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 580 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}}); 581 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}}); 582 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}}); 583 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}}); 584 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}}); 585 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}}); 586 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}}); 587 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}}); 588 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}}); 589 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}}); 590 0x60: BasicOperate::fzero({{Frd.df = 0;}}); 591 0x61: BasicOperate::fzeros({{Frd.sf = 0;}}); 592 0x62: Trap::fnor({{fault = new IllegalInstruction;}}); 593 0x63: Trap::fnors({{fault = new IllegalInstruction;}}); 594 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}}); 595 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}}); 596 0x66: BasicOperate::fnot2({{ 597 Frd.df = (double)(~((uint64_t)Frs2.df)); 598 }}); 599 0x67: BasicOperate::fnot2s({{ 600 Frd.sf = (float)(~((uint32_t)Frs2.sf)); 601 }}); 602 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}}); 603 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}}); 604 0x6A: BasicOperate::fnot1({{ 605 Frd.df = (double)(~((uint64_t)Frs1.df)); 606 }}); 607 0x6B: BasicOperate::fnot1s({{ 608 Frd.sf = (float)(~((uint32_t)Frs1.sf)); 609 }}); 610 0x6C: Trap::fxor({{fault = new IllegalInstruction;}}); 611 0x6D: Trap::fxors({{fault = new IllegalInstruction;}}); 612 0x6E: Trap::fnand({{fault = new IllegalInstruction;}}); 613 0x6F: Trap::fnands({{fault = new IllegalInstruction;}}); 614 0x70: Trap::fand({{fault = new IllegalInstruction;}}); 615 0x71: Trap::fands({{fault = new IllegalInstruction;}}); 616 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); 617 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); 618 0x74: BasicOperate::fsrc1({{Frd.df = Frs1.df;}}); 619 0x75: BasicOperate::fsrc1s({{Frd.sf = Frs1.sf;}}); 620 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); 621 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); 622 0x78: BasicOperate::fsrc2({{Frd.df = Frs2.df;}}); 623 0x79: BasicOperate::fsrc2s({{Frd.sf = Frs2.sf;}}); 624 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); 625 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); 626 0x7C: Trap::for({{fault = new IllegalInstruction;}}); 627 0x7D: Trap::fors({{fault = new IllegalInstruction;}}); 628 0x7E: Trap::fone({{fault = new IllegalInstruction;}}); 629 0x7F: Trap::fones({{fault = new IllegalInstruction;}}); 630 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 631 0x81: Trap::siam({{fault = new IllegalInstruction;}}); 632 } 633 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 634 0x38: Branch::jmpl({{ 635 Addr target = Rs1 + Rs2_or_imm13; 636 if(target & 0x3) 637 fault = new MemAddressNotAligned; 638 else 639 { 640 Rd = xc->readPC(); 641 NNPC = target; 642 } 643 }}); 644 0x39: Branch::return({{ 645 //If both MemAddressNotAligned and 646 //a fill trap happen, it's not clear 647 //which one should be returned. 648 Addr target = Rs1 + Rs2_or_imm13; 649 if(target & 0x3) 650 fault = new MemAddressNotAligned; 651 else 652 NNPC = target; 653 if(fault == NoFault) 654 { 655 //CWP should be set directly so that it always happens 656 //Also, this will allow writing to the new window and 657 //reading from the old one 658 Cwp = (Cwp - 1 + NWindows) % NWindows; 659 if(Canrestore == 0) 660 { 661 if(Otherwin) 662 fault = new FillNOther(Wstate<5:3>); 663 else 664 fault = new FillNNormal(Wstate<2:0>); 665 } 666 else 667 { 668 Rd = Rs1 + Rs2_or_imm13; 669 Cansave = Cansave + 1; 670 Canrestore = Canrestore - 1; 671 } 672 //This is here to make sure the CWP is written 673 //no matter what. This ensures that the results 674 //are written in the new window as well. 675 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 676 } 677 }}); 678 0x3A: decode CC 679 { 680 0x0: Trap::tcci({{ 681 if(passesCondition(Ccr<3:0>, COND2)) 682 { 683 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 684 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 685#if FULL_SYSTEM 686 fault = new TrapInstruction(lTrapNum); 687#else 688 DPRINTF(Sparc, "The syscall number is %d\n", R1); 689 xc->syscall(R1); 690#endif 691 } 692 }}); 693 0x2: Trap::tccx({{ 694 if(passesCondition(Ccr<7:4>, COND2)) 695 { 696 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 697 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 698#if FULL_SYSTEM 699 fault = new TrapInstruction(lTrapNum); 700#else 701 DPRINTF(Sparc, "The syscall number is %d\n", R1); 702 xc->syscall(R1); 703#endif 704 } 705 }}); 706 } 707 0x3B: Nop::flush({{/*Instruction memory flush*/}}); 708 0x3C: save({{ 709 //CWP should be set directly so that it always happens 710 //Also, this will allow writing to the new window and 711 //reading from the old one 712 if(Cansave == 0) 713 { 714 if(Otherwin) 715 fault = new SpillNOther(Wstate<5:3>); 716 else 717 fault = new SpillNNormal(Wstate<2:0>); 718 Cwp = (Cwp + 2) % NWindows; 719 } 720 else if(Cleanwin - Canrestore == 0) 721 { 722 Cwp = (Cwp + 1) % NWindows; 723 fault = new CleanWindow; 724 } 725 else 726 { 727 Cwp = (Cwp + 1) % NWindows; 728 Rd = Rs1 + Rs2_or_imm13; 729 Cansave = Cansave - 1; 730 Canrestore = Canrestore + 1; 731 } 732 //This is here to make sure the CWP is written 733 //no matter what. This ensures that the results 734 //are written in the new window as well. 735 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 736 }}); 737 0x3D: restore({{ 738 //CWP should be set directly so that it always happens 739 //Also, this will allow writing to the new window and 740 //reading from the old one 741 Cwp = (Cwp - 1 + NWindows) % NWindows; 742 if(Canrestore == 0) 743 { 744 if(Otherwin) 745 fault = new FillNOther(Wstate<5:3>); 746 else 747 fault = new FillNNormal(Wstate<2:0>); 748 } 749 else 750 { 751 Rd = Rs1 + Rs2_or_imm13; 752 Cansave = Cansave + 1; 753 Canrestore = Canrestore - 1; 754 } 755 //This is here to make sure the CWP is written 756 //no matter what. This ensures that the results 757 //are written in the new window as well. 758 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 759 }}); 760 0x3E: decode FCN { 761 0x0: Priv::done({{ 762 if(Tl == 0) 763 return new IllegalInstruction; 764 765 Cwp = Tstate<4:0>; 766 Pstate = Tstate<20:8>; 767 Asi = Tstate<31:24>; 768 Ccr = Tstate<39:32>; 769 Gl = Tstate<42:40>; 770 NPC = Tnpc; 771 NNPC = Tnpc + 4; 772 Tl = Tl - 1; 773 }}); 774 0x1: Priv::retry({{ 775 if(Tl == 0) 776 return new IllegalInstruction; 777 Cwp = Tstate<4:0>; 778 Pstate = Tstate<20:8>; 779 Asi = Tstate<31:24>; 780 Ccr = Tstate<39:32>; 781 Gl = Tstate<42:40>; 782 NPC = Tpc; 783 NNPC = Tnpc + 4; 784 Tl = Tl - 1; 785 }}); 786 } 787 } 788 } 789 0x3: decode OP3 { 790 format Load { 791 0x00: lduw({{Rd = Mem;}}, {{32}}); 792 0x01: ldub({{Rd = Mem;}}, {{8}}); 793 0x02: lduh({{Rd = Mem;}}, {{16}}); 794 0x03: ldd({{ 795 uint64_t val = Mem; 796 RdLow = val<31:0>; 797 RdHigh = val<63:32>; 798 }}, {{64}}); 799 } 800 format Store { 801 0x04: stw({{Mem = Rd.sw;}}, {{32}}); 802 0x05: stb({{Mem = Rd.sb;}}, {{8}}); 803 0x06: sth({{Mem = Rd.shw;}}, {{16}}); 804 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 805 } 806 format Load { 807 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}}); 808 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}}); 809 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}}); 810 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}}); 811 0x0D: ldstub({{ 812 Rd = Mem; 813 Mem = 0xFF; 814 }}, {{8}}); 815 } 816 0x0E: Store::stx({{Mem = Rd}}, {{64}}); 817 0x0F: LoadStore::swap({{ 818 uint32_t temp = Rd; 819 Rd = Mem; 820 Mem = temp; 821 }}, {{32}}); 822 format Load { 823 0x10: lduwa({{Rd = Mem;}}, {{32}}); 824 0x11: lduba({{Rd = Mem;}}, {{8}}); 825 0x12: lduha({{Rd = Mem;}}, {{16}}); 826 0x13: ldda({{ 827 uint64_t val = Mem; 828 RdLow = val<31:0>; 829 RdHigh = val<63:32>; 830 }}, {{64}}); 831 } 832 format Store { 833 0x14: stwa({{Mem = Rd;}}, {{32}}); 834 0x15: stba({{Mem = Rd;}}, {{8}}); 835 0x16: stha({{Mem = Rd;}}, {{16}}); 836 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 837 } 838 format Load { 839 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}}); 840 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}}); 841 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}}); 842 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}}); 843 } 844 0x1D: LoadStore::ldstuba({{ 845 Rd = Mem; 846 Mem = 0xFF; 847 }}, {{8}}); 848 0x1E: Store::stxa({{Mem = Rd}}, {{64}}); 849 0x1F: LoadStore::swapa({{ 850 uint32_t temp = Rd; 851 Rd = Mem; 852 Mem = temp; 853 }}, {{32}}); 854 format Trap { 855 0x20: Load::ldf({{Frd.sf = ((float)Mem);}}, {{32}}); 856 0x21: decode X { 857 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}}); 858 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}}); 859 } 860 0x22: ldqf({{fault = new FpDisabled;}}); 861 0x23: Load::lddf({{Frd.df = ((double)Mem);}}, {{64}}); 862 0x24: Store::stf({{Mem = ((int32_t)Frd.sf);}}, {{32}}); 863 0x25: decode X { 864 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}}); 865 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}}); 866 } 867 0x26: stqf({{fault = new FpDisabled;}}); 868 0x27: Store::stdf({{Mem = ((int64_t)Frd.df);}}, {{64}}); 869 0x2D: Nop::prefetch({{ }}); 870 0x30: Load::ldfa({{Frd.sf = ((float)Mem);}}, {{32}}); 871 0x32: ldqfa({{fault = new FpDisabled;}}); 872 0x33: Load::lddfa({{Frd.df = ((double)Mem);}}, {{64}}); 873 0x34: Store::stfa({{Mem = ((int32_t)Frd.sf);}}, {{32}}); 874 0x36: stqfa({{fault = new FpDisabled;}}); 875 //XXX need to work in the ASI thing 876 0x37: Store::stdfa({{Mem = ((uint64_t)Frd.df);}}, {{64}}); 877 0x3C: Cas::casa({{ 878 uint64_t val = Mem.uw; 879 if(Rs2.uw == val) 880 Mem.uw = Rd.uw; 881 Rd.uw = val; 882 }}); 883 0x3D: Nop::prefetcha({{ }}); 884 0x3E: Cas::casxa({{ 885 uint64_t val = Mem.udw; 886 if(Rs2 == val) 887 Mem.udw = Rd; 888 Rd = val; 889 }}); 890 } 891 } 892} 893