decoder.isa revision 2632:1bb2f91485ea
1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 //Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 0x1: decode BPCC 43 { 44 format Branch19 45 { 46 0x0: bpcci({{ 47 if(passesCondition(CcrIcc, COND2)) 48 NNPC = xc->readPC() + disp; 49 else 50 handle_annul 51 }}); 52 0x2: bpccx({{ 53 if(passesCondition(CcrXcc, COND2)) 54 NNPC = xc->readPC() + disp; 55 else 56 handle_annul 57 }}); 58 } 59 } 60 0x2: Branch22::bicc({{ 61 if(passesCondition(CcrIcc, COND2)) 62 NNPC = xc->readPC() + disp; 63 else 64 handle_annul 65 }}); 66 0x3: decode RCOND2 67 { 68 format BranchSplit 69 { 70 0x1: bpreq({{ 71 if(Rs1.sdw == 0) 72 NNPC = xc->readPC() + disp; 73 else 74 handle_annul 75 }}); 76 0x2: bprle({{ 77 if(Rs1.sdw <= 0) 78 NNPC = xc->readPC() + disp; 79 else 80 handle_annul 81 }}); 82 0x3: bprl({{ 83 if(Rs1.sdw < 0) 84 NNPC = xc->readPC() + disp; 85 else 86 handle_annul 87 }}); 88 0x5: bprne({{ 89 if(Rs1.sdw != 0) 90 NNPC = xc->readPC() + disp; 91 else 92 handle_annul 93 }}); 94 0x6: bprg({{ 95 if(Rs1.sdw > 0) 96 NNPC = xc->readPC() + disp; 97 else 98 handle_annul 99 }}); 100 0x7: bprge({{ 101 if(Rs1.sdw >= 0) 102 NNPC = xc->readPC() + disp; 103 else 104 handle_annul 105 }}); 106 } 107 } 108 //SETHI (or NOP if rd == 0 and imm == 0) 109 0x4: SetHi::sethi({{Rd = imm;}}); 110 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 111 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 112 } 113 0x1: Branch30::call({{ 114 R15 = xc->readPC(); 115 NNPC = R15 + disp; 116 }}); 117 0x2: decode OP3 { 118 format IntOp { 119 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 120 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}}); 121 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}}); 122 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}}); 123 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 124 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}}); 125 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}}); 126 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}}); 127 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + CcrIccC;}}); 128 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}}); 129 0x0A: umul({{ 130 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 131 YValue = Rd<63:32>; 132 }}); 133 0x0B: smul({{ 134 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; 135 YValue = Rd.sdw; 136 }}); 137 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + CcrIccC;}}); 138 0x0D: udivx({{ 139 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 140 else Rd.udw = Rs1.udw / Rs2_or_imm13; 141 }}); 142 0x0E: udiv({{ 143 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 144 else 145 { 146 Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 147 if(Rd.udw >> 32 != 0) 148 Rd.udw = 0xFFFFFFFF; 149 } 150 }}); 151 0x0F: sdiv({{ 152 if(Rs2_or_imm13.sdw == 0) 153 fault = new DivisionByZero; 154 else 155 { 156 Rd.udw = ((int64_t)((YValue << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 157 if(Rd.udw<63:31> != 0) 158 Rd.udw = 0x7FFFFFFF; 159 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 160 Rd.udw = 0xFFFFFFFF80000000ULL; 161 } 162 }}); 163 } 164 format IntOpCc { 165 0x10: addcc({{ 166 int64_t resTemp, val2 = Rs2_or_imm13; 167 Rd = resTemp = Rs1 + val2;}}, 168 {{(Rs1<31:0> + val2<31:0>)<32:>}}, 169 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 170 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 171 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 172 ); 173 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 174 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 175 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 176 0x14: subcc({{ 177 int64_t val2 = Rs2_or_imm13; 178 Rd = Rs1 - val2;}}, 179 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 180 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 181 {{(~(Rs1<63:1> + (~val2)<63:1> + 182 (Rs1 | ~val2)<0:>))<63:>}}, 183 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 184 ); 185 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 186 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 187 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 188 0x18: addccc({{ 189 int64_t resTemp, val2 = Rs2_or_imm13; 190 int64_t carryin = CcrIccC; 191 Rd = resTemp = Rs1 + val2 + carryin;}}, 192 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 193 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 194 {{(Rs1<63:1> + val2<63:1> + 195 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, 196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 197 ); 198 0x1A: umulcc({{ 199 uint64_t resTemp; 200 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 201 YValue = resTemp<63:32>;}}, 202 {{0}},{{0}},{{0}},{{0}}); 203 0x1B: smulcc({{ 204 int64_t resTemp; 205 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; 206 YValue = resTemp<63:32>;}}, 207 {{0}},{{0}},{{0}},{{0}}); 208 0x1C: subccc({{ 209 int64_t resTemp, val2 = Rs2_or_imm13; 210 int64_t carryin = CcrIccC; 211 Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, 212 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, 213 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 214 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, 215 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 216 ); 217 0x1D: udivxcc({{ 218 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 219 else Rd = Rs1.udw / Rs2_or_imm13.udw;}} 220 ,{{0}},{{0}},{{0}},{{0}}); 221 0x1E: udivcc({{ 222 uint32_t resTemp, val2 = Rs2_or_imm13.udw; 223 int32_t overflow; 224 if(val2 == 0) fault = new DivisionByZero; 225 else 226 { 227 resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2; 228 overflow = (resTemp<63:32> != 0); 229 if(overflow) Rd = resTemp = 0xFFFFFFFF; 230 else Rd = resTemp; 231 } }}, 232 {{0}}, 233 {{overflow}}, 234 {{0}}, 235 {{0}} 236 ); 237 0x1F: sdivcc({{ 238 int32_t resTemp, val2 = Rs2_or_imm13.sdw; 239 int32_t overflow, underflow; 240 if(val2 == 0) fault = new DivisionByZero; 241 else 242 { 243 Rd = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2; 244 overflow = (resTemp<63:31> != 0); 245 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); 246 if(overflow) Rd = resTemp = 0x7FFFFFFF; 247 else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000ULL; 248 else Rd = resTemp; 249 } }}, 250 {{0}}, 251 {{overflow || underflow}}, 252 {{0}}, 253 {{0}} 254 ); 255 0x20: taddcc({{ 256 int64_t resTemp, val2 = Rs2_or_imm13; 257 Rd = resTemp = Rs1 + val2; 258 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 259 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 260 {{overflow}}, 261 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 262 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 263 ); 264 0x21: tsubcc({{ 265 int64_t resTemp, val2 = Rs2_or_imm13; 266 Rd = resTemp = Rs1 + val2; 267 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 268 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}}, 269 {{overflow}}, 270 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 271 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 272 ); 273 0x22: taddcctv({{ 274 int64_t resTemp, val2 = Rs2_or_imm13; 275 Rd = resTemp = Rs1 + val2; 276 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 277 if(overflow) fault = new TagOverflow;}}, 278 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 279 {{overflow}}, 280 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 281 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 282 ); 283 0x23: tsubcctv({{ 284 int64_t resTemp, val2 = Rs2_or_imm13; 285 Rd = resTemp = Rs1 + val2; 286 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 287 if(overflow) fault = new TagOverflow;}}, 288 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, 289 {{overflow}}, 290 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 291 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 292 ); 293 0x24: mulscc({{ 294 int64_t resTemp, multiplicand = Rs2_or_imm13; 295 int32_t multiplier = Rs1<31:0>; 296 int32_t savedLSB = Rs1<0:>; 297 multiplier = multiplier<31:1> | 298 ((CcrIccN 299 ^ CcrIccV) << 32); 300 if(!YValue<0:>) 301 multiplicand = 0; 302 Rd = resTemp = multiplicand + multiplier; 303 YValue = YValue<31:1> | (savedLSB << 31);}}, 304 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, 305 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 306 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 307 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 308 ); 309 } 310 format IntOp 311 { 312 0x25: decode X { 313 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 314 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 315 } 316 0x26: decode X { 317 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 318 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 319 } 320 0x27: decode X { 321 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 322 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 323 } 324 0x28: decode RS1 { 325 0x0: rdy({{Rd = YValue;}}); 326 0x2: rdccr({{Rd = Ccr;}}); 327 0x3: rdasi({{Rd = Asi;}}); 328 0x4: PrivTick::rdtick({{Rd = Tick;}}); 329 0x5: rdpc({{Rd = xc->readPC();}}); 330 0x6: rdfprs({{Rd = Fprs;}}); 331 0xF: decode I { 332 0x0: Nop::membar({{/*Membar isn't needed yet*/}}); 333 0x1: Nop::stbar({{/*Stbar isn't needed yet*/}}); 334 } 335 } 336 0x2A: decode RS1 { 337 format Priv 338 { 339 0x0: rdprtpc({{ 340 Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl); 341 }}); 342 0x1: rdprtnpc({{ 343 Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); 344 }}); 345 0x2: rdprtstate({{ 346 Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl); 347 }}); 348 0x3: rdprtt({{ 349 Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl); 350 }}); 351 0x4: rdprtick({{Rd = Tick;}}); 352 0x5: rdprtba({{Rd = Tba;}}); 353 0x6: rdprpstate({{Rd = Pstate;}}); 354 0x7: rdprtl({{Rd = Tl;}}); 355 0x8: rdprpil({{Rd = Pil;}}); 356 0x9: rdprcwp({{Rd = Cwp;}}); 357 0xA: rdprcansave({{Rd = Cansave;}}); 358 0xB: rdprcanrestore({{Rd = Canrestore;}}); 359 0xC: rdprcleanwin({{Rd = Cleanwin;}}); 360 0xD: rdprotherwin({{Rd = Otherwin;}}); 361 0xE: rdprwstate({{Rd = Wstate;}}); 362 } 363 //The floating point queue isn't implemented right now. 364 0xF: Trap::rdprfq({{fault = new IllegalInstruction;}}); 365 0x1F: Priv::rdprver({{Rd = Ver;}}); 366 } 367 0x2B: BasicOperate::flushw({{ 368 if(NWindows - 2 - Cansave == 0) 369 { 370 if(Otherwin) 371 fault = new SpillNOther(WstateOther); 372 else 373 fault = new SpillNNormal(WstateNormal); 374 } 375 }}); 376 0x2C: decode MOVCC3 377 { 378 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 379 0x1: decode CC 380 { 381 0x0: movcci({{ 382 if(passesCondition(CcrIcc, COND4)) 383 Rd = Rs2_or_imm11; 384 else 385 Rd = Rd; 386 }}); 387 0x2: movccx({{ 388 if(passesCondition(CcrXcc, COND4)) 389 Rd = Rs2_or_imm11; 390 else 391 Rd = Rd; 392 }}); 393 } 394 } 395 0x2D: sdivx({{ 396 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 397 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 398 }}); 399 0x2E: decode RS1 { 400 0x0: IntOp::popc({{ 401 int64_t count = 0; 402 uint64_t temp = Rs2_or_imm13; 403 //Count the 1s in the front 4bits until none are left 404 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}; 405 while(temp) 406 { 407 count += oneBits[temp & 0xF]; 408 temp = temp >> 4; 409 } 410 Rd = count; 411 }}); 412 } 413 0x2F: decode RCOND3 414 { 415 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 416 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 417 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 418 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 419 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 420 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 421 } 422 0x30: decode RD { 423 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}}); 424 0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 425 0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 426 0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}}); 427 0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}}); 428 } 429 0x31: decode FCN { 430 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 431 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); 432 } 433 0x32: decode RD { 434 format Priv 435 { 436 0x0: wrprtpc({{ 437 xc->setMiscReg(MISCREG_TPC_BASE + Tl, 438 Rs1 ^ Rs2_or_imm13); 439 }}); 440 0x1: wrprtnpc({{ 441 xc->setMiscReg(MISCREG_TNPC_BASE + Tl, 442 Rs1 ^ Rs2_or_imm13); 443 }}); 444 0x2: wrprtstate({{ 445 xc->setMiscReg(MISCREG_TSTATE_BASE + Tl, 446 Rs1 ^ Rs2_or_imm13); 447 }}); 448 0x3: wrprtt({{ 449 xc->setMiscReg(MISCREG_TT_BASE + Tl, 450 Rs1 ^ Rs2_or_imm13); 451 }}); 452 0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 453 0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 454 0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 455 0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}}); 456 0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 457 0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 458 0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 459 0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 460 0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 461 0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 462 0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 463 } 464 } 465 0x34: Trap::fpop1({{fault = new FpDisabled;}}); 466 0x35: Trap::fpop2({{fault = new FpDisabled;}}); 467 0x38: Branch::jmpl({{ 468 Addr target = Rs1 + Rs2_or_imm13; 469 if(target & 0x3) 470 fault = new MemAddressNotAligned; 471 else 472 { 473 Rd = xc->readPC(); 474 NNPC = target; 475 } 476 }}); 477 0x39: Branch::return({{ 478 //If both MemAddressNotAligned and 479 //a fill trap happen, it's not clear 480 //which one should be returned. 481 Addr target = Rs1 + Rs2_or_imm13; 482 if(target & 0x3) 483 fault = new MemAddressNotAligned; 484 else 485 NNPC = target; 486 if(fault == NoFault) 487 { 488 //CWP should be set directly so that it always happens 489 //Also, this will allow writing to the new window and 490 //reading from the old one 491 Cwp = (Cwp - 1 + NWindows) % NWindows; 492 if(Canrestore == 0) 493 { 494 if(Otherwin) 495 fault = new FillNOther(WstateOther); 496 else 497 fault = new FillNNormal(WstateNormal); 498 } 499 else 500 { 501 Rd = Rs1 + Rs2_or_imm13; 502 Cansave = Cansave + 1; 503 Canrestore = Canrestore - 1; 504 } 505 //This is here to make sure the CWP is written 506 //no matter what. This ensures that the results 507 //are written in the new window as well. 508 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 509 } 510 }}); 511 0x3A: decode CC 512 { 513 0x0: Trap::tcci({{ 514 if(passesCondition(CcrIcc, COND2)) 515 { 516 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 517 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 518#if FULL_SYSTEM 519 fault = new TrapInstruction(lTrapNum); 520#else 521 DPRINTF(Sparc, "The syscall number is %d\n", R1); 522 xc->syscall(R1); 523#endif 524 } 525 }}); 526 0x2: Trap::tccx({{ 527 if(passesCondition(CcrXcc, COND2)) 528 { 529 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 530 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 531#if FULL_SYSTEM 532 fault = new TrapInstruction(lTrapNum); 533#else 534 DPRINTF(Sparc, "The syscall number is %d\n", R1); 535 xc->syscall(R1); 536#endif 537 } 538 }}); 539 } 540 0x3B: Nop::flush({{/*Instruction memory flush*/}}); 541 0x3C: save({{ 542 //CWP should be set directly so that it always happens 543 //Also, this will allow writing to the new window and 544 //reading from the old one 545 if(Cansave == 0) 546 { 547 if(Otherwin) 548 fault = new SpillNOther(WstateOther); 549 else 550 fault = new SpillNNormal(WstateNormal); 551 Cwp = (Cwp + 2) % NWindows; 552 } 553 else if(Cleanwin - Canrestore == 0) 554 { 555 Cwp = (Cwp + 1) % NWindows; 556 fault = new CleanWindow; 557 } 558 else 559 { 560 Cwp = (Cwp + 1) % NWindows; 561 Rd = Rs1 + Rs2_or_imm13; 562 Cansave = Cansave - 1; 563 Canrestore = Canrestore + 1; 564 } 565 //This is here to make sure the CWP is written 566 //no matter what. This ensures that the results 567 //are written in the new window as well. 568 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 569 }}); 570 0x3D: restore({{ 571 //CWP should be set directly so that it always happens 572 //Also, this will allow writing to the new window and 573 //reading from the old one 574 Cwp = (Cwp - 1 + NWindows) % NWindows; 575 if(Canrestore == 0) 576 { 577 if(Otherwin) 578 fault = new FillNOther(WstateOther); 579 else 580 fault = new FillNNormal(WstateNormal); 581 } 582 else 583 { 584 Rd = Rs1 + Rs2_or_imm13; 585 Cansave = Cansave + 1; 586 Canrestore = Canrestore - 1; 587 } 588 //This is here to make sure the CWP is written 589 //no matter what. This ensures that the results 590 //are written in the new window as well. 591 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); 592 }}); 593 0x3E: decode FCN { 594 0x0: Priv::done({{ 595 if(Tl == 0) 596 return new IllegalInstruction; 597 Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl); 598 Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl); 599 Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl); 600 Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl); 601 NPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); 602 NNPC = NPC + 4; 603 Tl = Tl - 1; 604 }}); 605 0x1: BasicOperate::retry({{ 606 if(Tl == 0) 607 return new IllegalInstruction; 608 Cwp = xc->readMiscReg(MISCREG_TSTATE_CWP_BASE + Tl); 609 Asi = xc->readMiscReg(MISCREG_TSTATE_ASI_BASE + Tl); 610 Ccr = xc->readMiscReg(MISCREG_TSTATE_CCR_BASE + Tl); 611 Pstate = xc->readMiscReg(MISCREG_TSTATE_PSTATE_BASE + Tl); 612 NPC = xc->readMiscReg(MISCREG_TPC_BASE + Tl); 613 NNPC = xc->readMiscReg(MISCREG_TNPC_BASE + Tl); 614 Tl = Tl - 1; 615 }}); 616 } 617 } 618 } 619 0x3: decode OP3 { 620 format Load { 621 0x00: lduw({{Rd = Mem;}}, {{32}}); 622 0x01: ldub({{Rd = Mem;}}, {{8}}); 623 0x02: lduh({{Rd = Mem;}}, {{16}}); 624 0x03: ldd({{ 625 uint64_t val = Mem; 626 RdLow = val<31:0>; 627 RdHigh = val<63:32>; 628 }}, {{64}}); 629 } 630 format Store { 631 0x04: stw({{Mem = Rd.sw;}}, {{32}}); 632 0x05: stb({{Mem = Rd.sb;}}, {{8}}); 633 0x06: sth({{Mem = Rd.shw;}}, {{16}}); 634 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 635 } 636 format Load { 637 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}}); 638 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}}); 639 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}}); 640 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}}); 641 0x0D: ldstub({{ 642 Rd = Mem; 643 Mem = 0xFF; 644 }}, {{8}}); 645 } 646 0x0E: Store::stx({{Mem = Rd}}, {{64}}); 647 0x0F: LoadStore::swap({{ 648 uint32_t temp = Rd; 649 Rd = Mem; 650 Mem = temp; 651 }}, {{32}}); 652 format Load { 653 0x10: lduwa({{Rd = Mem;}}, {{32}}); 654 0x11: lduba({{Rd = Mem;}}, {{8}}); 655 0x12: lduha({{Rd = Mem;}}, {{16}}); 656 0x13: ldda({{ 657 uint64_t val = Mem; 658 RdLow = val<31:0>; 659 RdHigh = val<63:32>; 660 }}, {{64}}); 661 } 662 format Store { 663 0x14: stwa({{Mem = Rd;}}, {{32}}); 664 0x15: stba({{Mem = Rd;}}, {{8}}); 665 0x16: stha({{Mem = Rd;}}, {{16}}); 666 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}}); 667 } 668 format Load { 669 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}}); 670 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}}); 671 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}}); 672 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}}); 673 } 674 0x1D: LoadStore::ldstuba({{ 675 Rd = Mem; 676 Mem = 0xFF; 677 }}, {{8}}); 678 0x1E: Store::stxa({{Mem = Rd}}, {{64}}); 679 0x1F: LoadStore::swapa({{ 680 uint32_t temp = Rd; 681 Rd = Mem; 682 Mem = temp; 683 }}, {{32}}); 684 format Trap { 685 0x20: ldf({{fault = new FpDisabled;}}); 686 0x21: decode X { 687 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}}); 688 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}}); 689 } 690 0x22: ldqf({{fault = new FpDisabled;}}); 691 0x23: lddf({{fault = new FpDisabled;}}); 692 0x24: stf({{fault = new FpDisabled;}}); 693 0x25: decode X { 694 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}}); 695 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}}); 696 } 697 0x26: stqf({{fault = new FpDisabled;}}); 698 0x27: stdf({{fault = new FpDisabled;}}); 699 0x2D: Nop::prefetch({{ }}); 700 0x30: ldfa({{return new FpDisabled;}}); 701 0x32: ldqfa({{fault = new FpDisabled;}}); 702 0x33: lddfa({{fault = new FpDisabled;}}); 703 0x34: stfa({{fault = new FpDisabled;}}); 704 0x35: stqfa({{fault = new FpDisabled;}}); 705 0x36: stdfa({{fault = new FpDisabled;}}); 706 0x3C: Cas::casa({{ 707 uint64_t val = Mem.uw; 708 if(Rs2.uw == val) 709 Mem.uw = Rd.uw; 710 Rd.uw = val; 711 }}); 712 0x3D: Nop::prefetcha({{ }}); 713 0x3E: Cas::casxa({{ 714 uint64_t val = Mem.udw; 715 if(Rs2 == val) 716 Mem.udw = Rd; 717 Rd = val; 718 }}); 719 } 720 } 721} 722