isa.hh revision 9920:028e4da64b42 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_ISA_HH__
32#define __ARCH_SPARC_ISA_HH__
33
34#include <ostream>
35#include <string>
36
37#include "arch/sparc/registers.hh"
38#include "arch/sparc/types.hh"
39#include "cpu/cpuevent.hh"
40#include "sim/sim_object.hh"
41
42class Checkpoint;
43class EventManager;
44struct SparcISAParams;
45class ThreadContext;
46
47namespace SparcISA
48{
49class ISA : public SimObject
50{
51  private:
52
53    /* ASR Registers */
54    // uint64_t y;          // Y (used in obsolete multiplication)
55    // uint8_t ccr;         // Condition Code Register
56    uint8_t asi;            // Address Space Identifier
57    uint64_t tick;          // Hardware clock-tick counter
58    uint8_t fprs;           // Floating-Point Register State
59    uint64_t gsr;           // General Status Register
60    uint64_t softint;
61    uint64_t tick_cmpr;     // Hardware tick compare registers
62    uint64_t stick;         // Hardware clock-tick counter
63    uint64_t stick_cmpr;    // Hardware tick compare registers
64
65
66    /* Privileged Registers */
67    uint64_t tpc[MaxTL];    // Trap Program Counter (value from
68                            // previous trap level)
69    uint64_t tnpc[MaxTL];   // Trap Next Program Counter (value from
70                            // previous trap level)
71    uint64_t tstate[MaxTL]; // Trap State
72    uint16_t tt[MaxTL];     // Trap Type (Type of trap which occured
73                            // on the previous level)
74    uint64_t tba;           // Trap Base Address
75
76    PSTATE pstate;        // Process State Register
77    uint8_t tl;             // Trap Level
78    uint8_t pil;            // Process Interrupt Register
79    uint8_t cwp;            // Current Window Pointer
80    // uint8_t cansave;     // Savable windows
81    // uint8_t canrestore;  // Restorable windows
82    // uint8_t cleanwin;    // Clean windows
83    // uint8_t otherwin;    // Other windows
84    // uint8_t wstate;      // Window State
85    uint8_t gl;             // Global level register
86
87    /** Hyperprivileged Registers */
88    HPSTATE hpstate;       // Hyperprivileged State Register
89    uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
90    uint64_t hintp;
91    uint64_t htba;          // Hyperprivileged Trap Base Address register
92    uint64_t hstick_cmpr;   // Hardware tick compare registers
93
94    uint64_t strandStatusReg;// Per strand status register
95
96    /** Floating point misc registers. */
97    uint64_t fsr;           // Floating-Point State Register
98
99    /** MMU Internal Registers */
100    uint16_t priContext;
101    uint16_t secContext;
102    uint16_t partId;
103    uint64_t lsuCtrlReg;
104
105    uint64_t scratchPad[8];
106
107    uint64_t cpu_mondo_head;
108    uint64_t cpu_mondo_tail;
109    uint64_t dev_mondo_head;
110    uint64_t dev_mondo_tail;
111    uint64_t res_error_head;
112    uint64_t res_error_tail;
113    uint64_t nres_error_head;
114    uint64_t nres_error_tail;
115
116    // These need to check the int_dis field and if 0 then
117    // set appropriate bit in softint and checkinterrutps on the cpu
118    void  setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
119    MiscReg readFSReg(int miscReg, ThreadContext * tc);
120
121    // Update interrupt state on softint or pil change
122    void checkSoftInt(ThreadContext *tc);
123
124    /** Process a tick compare event and generate an interrupt on the cpu if
125     * appropriate. */
126    void processTickCompare(ThreadContext *tc);
127    void processSTickCompare(ThreadContext *tc);
128    void processHSTickCompare(ThreadContext *tc);
129
130    typedef CpuEventWrapper<ISA,
131            &ISA::processTickCompare> TickCompareEvent;
132    TickCompareEvent *tickCompare;
133
134    typedef CpuEventWrapper<ISA,
135            &ISA::processSTickCompare> STickCompareEvent;
136    STickCompareEvent *sTickCompare;
137
138    typedef CpuEventWrapper<ISA,
139            &ISA::processHSTickCompare> HSTickCompareEvent;
140    HSTickCompareEvent *hSTickCompare;
141
142    static const int NumGlobalRegs = 8;
143    static const int NumWindowedRegs = 24;
144    static const int WindowOverlap = 8;
145
146    static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
147    static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
148    static const int TotalWindowed = NWindows * RegsPerWindow;
149
150    enum InstIntRegOffsets {
151        CurrentGlobalsOffset = 0,
152        CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
153        MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,
154        NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs,
155        NextWindowOffset = NextGlobalsOffset + NumGlobalRegs,
156        PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs,
157        PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs,
158        TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs
159    };
160
161    RegIndex intRegMap[TotalInstIntRegs];
162    void installWindow(int cwp, int offset);
163    void installGlobals(int gl, int offset);
164    void reloadRegMap();
165
166  public:
167
168    void clear();
169
170    void serialize(std::ostream & os);
171
172    void unserialize(Checkpoint *cp, const std::string & section);
173
174    void startup(ThreadContext *tc) {}
175
176    /// Explicitly import the otherwise hidden startup
177    using SimObject::startup;
178
179  protected:
180
181    bool isHyperPriv() { return hpstate.hpriv; }
182    bool isPriv() { return hpstate.hpriv || pstate.priv; }
183    bool isNonPriv() { return !isPriv(); }
184
185  public:
186
187    MiscReg readMiscRegNoEffect(int miscReg);
188    MiscReg readMiscReg(int miscReg, ThreadContext *tc);
189
190    void setMiscRegNoEffect(int miscReg, const MiscReg val);
191    void setMiscReg(int miscReg, const MiscReg val,
192            ThreadContext *tc);
193
194    int
195    flattenIntIndex(int reg)
196    {
197        assert(reg < TotalInstIntRegs);
198        RegIndex flatIndex = intRegMap[reg];
199        assert(flatIndex < NumIntRegs);
200        return flatIndex;
201    }
202
203    int
204    flattenFloatIndex(int reg)
205    {
206        return reg;
207    }
208
209    // dummy
210    int
211    flattenCCIndex(int reg)
212    {
213        return reg;
214    }
215
216    typedef SparcISAParams Params;
217    const Params *params() const;
218
219    ISA(Params *p);
220};
221}
222
223#endif
224