isa.cc revision 6313
1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/sparc/isa.hh" 32#include "cpu/thread_context.hh" 33 34namespace SparcISA 35{ 36 37void 38ISA::clear() 39{ 40 miscRegFile.clear(); 41} 42 43MiscReg 44ISA::readMiscRegNoEffect(int miscReg) 45{ 46 return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg); 47} 48 49MiscReg 50ISA::readMiscReg(int miscReg, ThreadContext *tc) 51{ 52 return miscRegFile.readReg((MiscRegIndex)miscReg, tc); 53} 54 55void 56ISA::setMiscRegNoEffect(int miscReg, const MiscReg val) 57{ 58 miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val); 59} 60 61void 62ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc) 63{ 64 miscRegFile.setReg((MiscRegIndex)miscReg, val, tc); 65} 66 67int 68ISA::flattenIntIndex(int reg) 69{ 70 int gl = miscRegFile.readRegNoEffect(MISCREG_GL); 71 int cwp = miscRegFile.readRegNoEffect(MISCREG_CWP); 72 //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp); 73 int newReg; 74 //The total number of global registers 75 int numGlobals = (MaxGL + 1) * 8; 76 if(reg < 8) 77 { 78 //Global register 79 //Put it in the appropriate set of globals 80 newReg = reg + gl * 8; 81 } 82 else if(reg < NumIntArchRegs) 83 { 84 //Regular windowed register 85 //Put it in the window pointed to by cwp 86 newReg = numGlobals + 87 ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16)); 88 } 89 else if(reg < NumIntArchRegs + NumMicroIntRegs) 90 { 91 //Microcode register 92 //Displace from the end of the regular registers 93 newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16; 94 } 95 else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs) 96 { 97 reg -= (NumIntArchRegs + NumMicroIntRegs); 98 if(reg < 8) 99 { 100 //Global register from the next window 101 //Put it in the appropriate set of globals 102 newReg = reg + gl * 8; 103 } 104 else 105 { 106 //Windowed register from the previous window 107 //Put it in the window before the one pointed to by cwp 108 newReg = numGlobals + 109 ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16)); 110 } 111 } 112 else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs) 113 { 114 reg -= (2 * NumIntArchRegs + NumMicroIntRegs); 115 if(reg < 8) 116 { 117 //Global register from the previous window 118 //Put it in the appropriate set of globals 119 newReg = reg + gl * 8; 120 } 121 else 122 { 123 //Windowed register from the next window 124 //Put it in the window after the one pointed to by cwp 125 newReg = numGlobals + 126 ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16)); 127 } 128 } 129 else 130 panic("Tried to flatten invalid register index %d!\n", reg); 131 DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg); 132 return newReg; 133} 134 135void 136ISA::serialize(EventManager *em, std::ostream &os) 137{ 138 miscRegFile.serialize(em, os); 139} 140 141void 142ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) 143{ 144 miscRegFile.unserialize(em, cp, section); 145} 146 147} 148