isa.cc revision 9377
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 36313Sgblack@eecs.umich.edu * All rights reserved. 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146313Sgblack@eecs.umich.edu * this software without specific prior written permission. 156313Sgblack@eecs.umich.edu * 166313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * Authors: Gabe Black 296313Sgblack@eecs.umich.edu */ 306313Sgblack@eecs.umich.edu 316335Sgblack@eecs.umich.edu#include "arch/sparc/asi.hh" 329377Sgblack@eecs.umich.edu#include "arch/sparc/decoder.hh" 336313Sgblack@eecs.umich.edu#include "arch/sparc/isa.hh" 346335Sgblack@eecs.umich.edu#include "base/bitfield.hh" 356335Sgblack@eecs.umich.edu#include "base/trace.hh" 366335Sgblack@eecs.umich.edu#include "cpu/base.hh" 376313Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 388232Snate@binkert.org#include "debug/MiscRegs.hh" 398232Snate@binkert.org#include "debug/Timer.hh" 406313Sgblack@eecs.umich.edu 416313Sgblack@eecs.umich.edunamespace SparcISA 426313Sgblack@eecs.umich.edu{ 436313Sgblack@eecs.umich.edu 448829Sgblack@eecs.umich.edustatic PSTATE 458829Sgblack@eecs.umich.edubuildPstateMask() 466335Sgblack@eecs.umich.edu{ 478829Sgblack@eecs.umich.edu PSTATE mask = 0; 488829Sgblack@eecs.umich.edu mask.ie = 1; 498829Sgblack@eecs.umich.edu mask.priv = 1; 508829Sgblack@eecs.umich.edu mask.am = 1; 518829Sgblack@eecs.umich.edu mask.pef = 1; 528829Sgblack@eecs.umich.edu mask.mm = 3; 538829Sgblack@eecs.umich.edu mask.tle = 1; 548829Sgblack@eecs.umich.edu mask.cle = 1; 558829Sgblack@eecs.umich.edu mask.pid1 = 1; 568829Sgblack@eecs.umich.edu return mask; 578829Sgblack@eecs.umich.edu} 588829Sgblack@eecs.umich.edu 598829Sgblack@eecs.umich.edustatic const PSTATE PstateMask = buildPstateMask(); 606335Sgblack@eecs.umich.edu 616313Sgblack@eecs.umich.eduvoid 626337Sgblack@eecs.umich.eduISA::reloadRegMap() 636337Sgblack@eecs.umich.edu{ 646337Sgblack@eecs.umich.edu installGlobals(gl, CurrentGlobalsOffset); 656337Sgblack@eecs.umich.edu installWindow(cwp, CurrentWindowOffset); 666337Sgblack@eecs.umich.edu // Microcode registers. 676337Sgblack@eecs.umich.edu for (int i = 0; i < NumMicroIntRegs; i++) 686337Sgblack@eecs.umich.edu intRegMap[MicroIntOffset + i] = i + TotalGlobals + NWindows * 16; 696337Sgblack@eecs.umich.edu installGlobals(gl, NextGlobalsOffset); 706337Sgblack@eecs.umich.edu installWindow(cwp - 1, NextWindowOffset); 716337Sgblack@eecs.umich.edu installGlobals(gl, PreviousGlobalsOffset); 726337Sgblack@eecs.umich.edu installWindow(cwp + 1, PreviousWindowOffset); 736337Sgblack@eecs.umich.edu} 746337Sgblack@eecs.umich.edu 756337Sgblack@eecs.umich.eduvoid 766337Sgblack@eecs.umich.eduISA::installWindow(int cwp, int offset) 776337Sgblack@eecs.umich.edu{ 786337Sgblack@eecs.umich.edu assert(offset >= 0 && offset + NumWindowedRegs <= NumIntRegs); 796337Sgblack@eecs.umich.edu RegIndex *mapChunk = intRegMap + offset; 806337Sgblack@eecs.umich.edu for (int i = 0; i < NumWindowedRegs; i++) 816337Sgblack@eecs.umich.edu mapChunk[i] = TotalGlobals + 826337Sgblack@eecs.umich.edu ((i - cwp * RegsPerWindow + TotalWindowed) % (TotalWindowed)); 836337Sgblack@eecs.umich.edu} 846337Sgblack@eecs.umich.edu 856337Sgblack@eecs.umich.eduvoid 866337Sgblack@eecs.umich.eduISA::installGlobals(int gl, int offset) 876337Sgblack@eecs.umich.edu{ 886337Sgblack@eecs.umich.edu assert(offset >= 0 && offset + NumGlobalRegs <= NumIntRegs); 896337Sgblack@eecs.umich.edu RegIndex *mapChunk = intRegMap + offset; 906337Sgblack@eecs.umich.edu mapChunk[0] = 0; 916337Sgblack@eecs.umich.edu for (int i = 1; i < NumGlobalRegs; i++) 926337Sgblack@eecs.umich.edu mapChunk[i] = i + gl * NumGlobalRegs; 936337Sgblack@eecs.umich.edu} 946337Sgblack@eecs.umich.edu 956337Sgblack@eecs.umich.eduvoid 966313Sgblack@eecs.umich.eduISA::clear() 976313Sgblack@eecs.umich.edu{ 986337Sgblack@eecs.umich.edu cwp = 0; 996337Sgblack@eecs.umich.edu gl = 0; 1006337Sgblack@eecs.umich.edu reloadRegMap(); 1016337Sgblack@eecs.umich.edu 1027741Sgblack@eecs.umich.edu // y = 0; 1037741Sgblack@eecs.umich.edu // ccr = 0; 1046335Sgblack@eecs.umich.edu asi = 0; 1056335Sgblack@eecs.umich.edu tick = ULL(1) << 63; 1066335Sgblack@eecs.umich.edu fprs = 0; 1076335Sgblack@eecs.umich.edu gsr = 0; 1086335Sgblack@eecs.umich.edu softint = 0; 1096335Sgblack@eecs.umich.edu tick_cmpr = 0; 1106335Sgblack@eecs.umich.edu stick = 0; 1116335Sgblack@eecs.umich.edu stick_cmpr = 0; 1126335Sgblack@eecs.umich.edu memset(tpc, 0, sizeof(tpc)); 1136335Sgblack@eecs.umich.edu memset(tnpc, 0, sizeof(tnpc)); 1146335Sgblack@eecs.umich.edu memset(tstate, 0, sizeof(tstate)); 1156335Sgblack@eecs.umich.edu memset(tt, 0, sizeof(tt)); 1167703Sgblack@eecs.umich.edu tba = 0; 1176335Sgblack@eecs.umich.edu pstate = 0; 1186335Sgblack@eecs.umich.edu tl = 0; 1196335Sgblack@eecs.umich.edu pil = 0; 1207741Sgblack@eecs.umich.edu // cansave = 0; 1217741Sgblack@eecs.umich.edu // canrestore = 0; 1227741Sgblack@eecs.umich.edu // cleanwin = 0; 1237741Sgblack@eecs.umich.edu // otherwin = 0; 1247741Sgblack@eecs.umich.edu // wstate = 0; 1257741Sgblack@eecs.umich.edu // In a T1, bit 11 is apparently always 1 1268829Sgblack@eecs.umich.edu hpstate = 0; 1278829Sgblack@eecs.umich.edu hpstate.id = 1; 1286335Sgblack@eecs.umich.edu memset(htstate, 0, sizeof(htstate)); 1296335Sgblack@eecs.umich.edu hintp = 0; 1306335Sgblack@eecs.umich.edu htba = 0; 1316335Sgblack@eecs.umich.edu hstick_cmpr = 0; 1327741Sgblack@eecs.umich.edu // This is set this way in Legion for some reason 1336335Sgblack@eecs.umich.edu strandStatusReg = 0x50000; 1346335Sgblack@eecs.umich.edu fsr = 0; 1356335Sgblack@eecs.umich.edu 1366335Sgblack@eecs.umich.edu priContext = 0; 1376335Sgblack@eecs.umich.edu secContext = 0; 1386335Sgblack@eecs.umich.edu partId = 0; 1396335Sgblack@eecs.umich.edu lsuCtrlReg = 0; 1406335Sgblack@eecs.umich.edu 1416335Sgblack@eecs.umich.edu memset(scratchPad, 0, sizeof(scratchPad)); 1427703Sgblack@eecs.umich.edu 1437703Sgblack@eecs.umich.edu cpu_mondo_head = 0; 1447703Sgblack@eecs.umich.edu cpu_mondo_tail = 0; 1457703Sgblack@eecs.umich.edu dev_mondo_head = 0; 1467703Sgblack@eecs.umich.edu dev_mondo_tail = 0; 1477703Sgblack@eecs.umich.edu res_error_head = 0; 1487703Sgblack@eecs.umich.edu res_error_tail = 0; 1497703Sgblack@eecs.umich.edu nres_error_head = 0; 1507703Sgblack@eecs.umich.edu nres_error_tail = 0; 1517703Sgblack@eecs.umich.edu 1527703Sgblack@eecs.umich.edu // If one of these events is active, it's not obvious to me how to get 1537703Sgblack@eecs.umich.edu // rid of it cleanly. For now we'll just assert that they're not. 1547703Sgblack@eecs.umich.edu if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL) 1557703Sgblack@eecs.umich.edu panic("Tick comparison event active when clearing the ISA object.\n"); 1566313Sgblack@eecs.umich.edu} 1576313Sgblack@eecs.umich.edu 1586313Sgblack@eecs.umich.eduMiscReg 1596313Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int miscReg) 1606313Sgblack@eecs.umich.edu{ 1616335Sgblack@eecs.umich.edu 1626335Sgblack@eecs.umich.edu // The three miscRegs are moved up from the switch statement 1636335Sgblack@eecs.umich.edu // due to more frequent calls. 1646335Sgblack@eecs.umich.edu 1656335Sgblack@eecs.umich.edu if (miscReg == MISCREG_GL) 1666335Sgblack@eecs.umich.edu return gl; 1676335Sgblack@eecs.umich.edu if (miscReg == MISCREG_CWP) 1686335Sgblack@eecs.umich.edu return cwp; 1696335Sgblack@eecs.umich.edu if (miscReg == MISCREG_TLB_DATA) { 1706335Sgblack@eecs.umich.edu /* Package up all the data for the tlb: 1716335Sgblack@eecs.umich.edu * 6666555555555544444444443333333333222222222211111111110000000000 1726335Sgblack@eecs.umich.edu * 3210987654321098765432109876543210987654321098765432109876543210 1736335Sgblack@eecs.umich.edu * secContext | priContext | |tl|partid| |||||^hpriv 1746335Sgblack@eecs.umich.edu * ||||^red 1756335Sgblack@eecs.umich.edu * |||^priv 1766335Sgblack@eecs.umich.edu * ||^am 1776335Sgblack@eecs.umich.edu * |^lsuim 1786335Sgblack@eecs.umich.edu * ^lsudm 1796335Sgblack@eecs.umich.edu */ 1808829Sgblack@eecs.umich.edu return (uint64_t)hpstate.hpriv | 1818829Sgblack@eecs.umich.edu (uint64_t)hpstate.red << 1 | 1828829Sgblack@eecs.umich.edu (uint64_t)pstate.priv << 2 | 1838829Sgblack@eecs.umich.edu (uint64_t)pstate.am << 3 | 1846335Sgblack@eecs.umich.edu bits((uint64_t)lsuCtrlReg,3,2) << 4 | 1856335Sgblack@eecs.umich.edu bits((uint64_t)partId,7,0) << 8 | 1866335Sgblack@eecs.umich.edu bits((uint64_t)tl,2,0) << 16 | 1876335Sgblack@eecs.umich.edu (uint64_t)priContext << 32 | 1886335Sgblack@eecs.umich.edu (uint64_t)secContext << 48; 1896335Sgblack@eecs.umich.edu } 1906335Sgblack@eecs.umich.edu 1916335Sgblack@eecs.umich.edu switch (miscReg) { 1927741Sgblack@eecs.umich.edu // case MISCREG_TLB_DATA: 1936335Sgblack@eecs.umich.edu // [original contents see above] 1947741Sgblack@eecs.umich.edu // case MISCREG_Y: 1956335Sgblack@eecs.umich.edu // return y; 1967741Sgblack@eecs.umich.edu // case MISCREG_CCR: 1976335Sgblack@eecs.umich.edu // return ccr; 1986335Sgblack@eecs.umich.edu case MISCREG_ASI: 1996335Sgblack@eecs.umich.edu return asi; 2006335Sgblack@eecs.umich.edu case MISCREG_FPRS: 2016335Sgblack@eecs.umich.edu return fprs; 2026335Sgblack@eecs.umich.edu case MISCREG_TICK: 2036335Sgblack@eecs.umich.edu return tick; 2046335Sgblack@eecs.umich.edu case MISCREG_PCR: 2056335Sgblack@eecs.umich.edu panic("PCR not implemented\n"); 2066335Sgblack@eecs.umich.edu case MISCREG_PIC: 2076335Sgblack@eecs.umich.edu panic("PIC not implemented\n"); 2086335Sgblack@eecs.umich.edu case MISCREG_GSR: 2096335Sgblack@eecs.umich.edu return gsr; 2106335Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 2116335Sgblack@eecs.umich.edu return softint; 2126335Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 2136335Sgblack@eecs.umich.edu return tick_cmpr; 2146335Sgblack@eecs.umich.edu case MISCREG_STICK: 2156335Sgblack@eecs.umich.edu return stick; 2166335Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 2176335Sgblack@eecs.umich.edu return stick_cmpr; 2186335Sgblack@eecs.umich.edu 2196335Sgblack@eecs.umich.edu /** Privilged Registers */ 2206335Sgblack@eecs.umich.edu case MISCREG_TPC: 2216335Sgblack@eecs.umich.edu return tpc[tl-1]; 2226335Sgblack@eecs.umich.edu case MISCREG_TNPC: 2236335Sgblack@eecs.umich.edu return tnpc[tl-1]; 2246335Sgblack@eecs.umich.edu case MISCREG_TSTATE: 2256335Sgblack@eecs.umich.edu return tstate[tl-1]; 2266335Sgblack@eecs.umich.edu case MISCREG_TT: 2276335Sgblack@eecs.umich.edu return tt[tl-1]; 2286335Sgblack@eecs.umich.edu case MISCREG_PRIVTICK: 2296335Sgblack@eecs.umich.edu panic("Priviliged access to tick registers not implemented\n"); 2306335Sgblack@eecs.umich.edu case MISCREG_TBA: 2316335Sgblack@eecs.umich.edu return tba; 2326335Sgblack@eecs.umich.edu case MISCREG_PSTATE: 2338829Sgblack@eecs.umich.edu return (MiscReg)pstate; 2346335Sgblack@eecs.umich.edu case MISCREG_TL: 2356335Sgblack@eecs.umich.edu return tl; 2366335Sgblack@eecs.umich.edu case MISCREG_PIL: 2376335Sgblack@eecs.umich.edu return pil; 2387741Sgblack@eecs.umich.edu // CWP, GL moved 2397741Sgblack@eecs.umich.edu // case MISCREG_CWP: 2407741Sgblack@eecs.umich.edu // return cwp; 2417741Sgblack@eecs.umich.edu // case MISCREG_CANSAVE: 2427741Sgblack@eecs.umich.edu // return cansave; 2437741Sgblack@eecs.umich.edu // case MISCREG_CANRESTORE: 2447741Sgblack@eecs.umich.edu // return canrestore; 2457741Sgblack@eecs.umich.edu // case MISCREG_CLEANWIN: 2467741Sgblack@eecs.umich.edu // return cleanwin; 2477741Sgblack@eecs.umich.edu // case MISCREG_OTHERWIN: 2487741Sgblack@eecs.umich.edu // return otherwin; 2497741Sgblack@eecs.umich.edu // case MISCREG_WSTATE: 2507741Sgblack@eecs.umich.edu // return wstate; 2517741Sgblack@eecs.umich.edu // case MISCREG_GL: 2527741Sgblack@eecs.umich.edu // return gl; 2536335Sgblack@eecs.umich.edu 2546335Sgblack@eecs.umich.edu /** Hyper privileged registers */ 2556335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 2568829Sgblack@eecs.umich.edu return (MiscReg)hpstate; 2576335Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 2586335Sgblack@eecs.umich.edu return htstate[tl-1]; 2596335Sgblack@eecs.umich.edu case MISCREG_HINTP: 2606335Sgblack@eecs.umich.edu return hintp; 2616335Sgblack@eecs.umich.edu case MISCREG_HTBA: 2626335Sgblack@eecs.umich.edu return htba; 2636335Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2646335Sgblack@eecs.umich.edu return strandStatusReg; 2656335Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 2666335Sgblack@eecs.umich.edu return hstick_cmpr; 2676335Sgblack@eecs.umich.edu 2686335Sgblack@eecs.umich.edu /** Floating Point Status Register */ 2696335Sgblack@eecs.umich.edu case MISCREG_FSR: 2706335Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr); 2716335Sgblack@eecs.umich.edu return fsr; 2726335Sgblack@eecs.umich.edu 2736335Sgblack@eecs.umich.edu case MISCREG_MMU_P_CONTEXT: 2746335Sgblack@eecs.umich.edu return priContext; 2756335Sgblack@eecs.umich.edu case MISCREG_MMU_S_CONTEXT: 2766335Sgblack@eecs.umich.edu return secContext; 2776335Sgblack@eecs.umich.edu case MISCREG_MMU_PART_ID: 2786335Sgblack@eecs.umich.edu return partId; 2796335Sgblack@eecs.umich.edu case MISCREG_MMU_LSU_CTRL: 2806335Sgblack@eecs.umich.edu return lsuCtrlReg; 2816335Sgblack@eecs.umich.edu 2826335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R0: 2836335Sgblack@eecs.umich.edu return scratchPad[0]; 2846335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R1: 2856335Sgblack@eecs.umich.edu return scratchPad[1]; 2866335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R2: 2876335Sgblack@eecs.umich.edu return scratchPad[2]; 2886335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R3: 2896335Sgblack@eecs.umich.edu return scratchPad[3]; 2906335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R4: 2916335Sgblack@eecs.umich.edu return scratchPad[4]; 2926335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R5: 2936335Sgblack@eecs.umich.edu return scratchPad[5]; 2946335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R6: 2956335Sgblack@eecs.umich.edu return scratchPad[6]; 2966335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R7: 2976335Sgblack@eecs.umich.edu return scratchPad[7]; 2986335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 2996335Sgblack@eecs.umich.edu return cpu_mondo_head; 3006335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 3016335Sgblack@eecs.umich.edu return cpu_mondo_tail; 3026335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 3036335Sgblack@eecs.umich.edu return dev_mondo_head; 3046335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 3056335Sgblack@eecs.umich.edu return dev_mondo_tail; 3066335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 3076335Sgblack@eecs.umich.edu return res_error_head; 3086335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 3096335Sgblack@eecs.umich.edu return res_error_tail; 3106335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 3116335Sgblack@eecs.umich.edu return nres_error_head; 3126335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 3136335Sgblack@eecs.umich.edu return nres_error_tail; 3146335Sgblack@eecs.umich.edu default: 3156335Sgblack@eecs.umich.edu panic("Miscellaneous register %d not implemented\n", miscReg); 3166335Sgblack@eecs.umich.edu } 3176313Sgblack@eecs.umich.edu} 3186313Sgblack@eecs.umich.edu 3196313Sgblack@eecs.umich.eduMiscReg 3206335Sgblack@eecs.umich.eduISA::readMiscReg(int miscReg, ThreadContext * tc) 3216313Sgblack@eecs.umich.edu{ 3226335Sgblack@eecs.umich.edu switch (miscReg) { 3236335Sgblack@eecs.umich.edu // tick and stick are aliased to each other in niagra 3246335Sgblack@eecs.umich.edu // well store the tick data in stick and the interrupt bit in tick 3256335Sgblack@eecs.umich.edu case MISCREG_STICK: 3266335Sgblack@eecs.umich.edu case MISCREG_TICK: 3276335Sgblack@eecs.umich.edu case MISCREG_PRIVTICK: 3286335Sgblack@eecs.umich.edu // I'm not sure why legion ignores the lowest two bits, but we'll go 3296335Sgblack@eecs.umich.edu // with it 3306335Sgblack@eecs.umich.edu // change from curCycle() to instCount() until we're done with legion 3316335Sgblack@eecs.umich.edu DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n", 3326335Sgblack@eecs.umich.edu tc->getCpuPtr()->instCount(), stick); 3336335Sgblack@eecs.umich.edu return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) | 3346335Sgblack@eecs.umich.edu mbits(tick,63,63); 3356335Sgblack@eecs.umich.edu case MISCREG_FPRS: 3366335Sgblack@eecs.umich.edu // in legion if fp is enabled du and dl are set 3376335Sgblack@eecs.umich.edu return fprs | 0x3; 3386335Sgblack@eecs.umich.edu case MISCREG_PCR: 3396335Sgblack@eecs.umich.edu case MISCREG_PIC: 3406335Sgblack@eecs.umich.edu panic("Performance Instrumentation not impl\n"); 3416335Sgblack@eecs.umich.edu case MISCREG_SOFTINT_CLR: 3426335Sgblack@eecs.umich.edu case MISCREG_SOFTINT_SET: 3436335Sgblack@eecs.umich.edu panic("Can read from softint clr/set\n"); 3446335Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 3456335Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 3466335Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 3476335Sgblack@eecs.umich.edu case MISCREG_HINTP: 3486335Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 3496335Sgblack@eecs.umich.edu case MISCREG_HTBA: 3506335Sgblack@eecs.umich.edu case MISCREG_HVER: 3516335Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 3526335Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 3536335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 3546335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 3556335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 3566335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 3576335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 3586335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 3596335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 3606335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 3616335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 3626335Sgblack@eecs.umich.edu return readFSReg(miscReg, tc); 3636335Sgblack@eecs.umich.edu } 3646335Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg); 3656313Sgblack@eecs.umich.edu} 3666313Sgblack@eecs.umich.edu 3676313Sgblack@eecs.umich.eduvoid 3686335Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int miscReg, MiscReg val) 3696313Sgblack@eecs.umich.edu{ 3706335Sgblack@eecs.umich.edu switch (miscReg) { 3716335Sgblack@eecs.umich.edu// case MISCREG_Y: 3726335Sgblack@eecs.umich.edu// y = val; 3736335Sgblack@eecs.umich.edu// break; 3746335Sgblack@eecs.umich.edu// case MISCREG_CCR: 3756335Sgblack@eecs.umich.edu// ccr = val; 3766335Sgblack@eecs.umich.edu// break; 3776335Sgblack@eecs.umich.edu case MISCREG_ASI: 3786335Sgblack@eecs.umich.edu asi = val; 3796335Sgblack@eecs.umich.edu break; 3806335Sgblack@eecs.umich.edu case MISCREG_FPRS: 3816335Sgblack@eecs.umich.edu fprs = val; 3826335Sgblack@eecs.umich.edu break; 3836335Sgblack@eecs.umich.edu case MISCREG_TICK: 3846335Sgblack@eecs.umich.edu tick = val; 3856335Sgblack@eecs.umich.edu break; 3866335Sgblack@eecs.umich.edu case MISCREG_PCR: 3876335Sgblack@eecs.umich.edu panic("PCR not implemented\n"); 3886335Sgblack@eecs.umich.edu case MISCREG_PIC: 3896335Sgblack@eecs.umich.edu panic("PIC not implemented\n"); 3906335Sgblack@eecs.umich.edu case MISCREG_GSR: 3916335Sgblack@eecs.umich.edu gsr = val; 3926335Sgblack@eecs.umich.edu break; 3936335Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 3946335Sgblack@eecs.umich.edu softint = val; 3956335Sgblack@eecs.umich.edu break; 3966335Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 3976335Sgblack@eecs.umich.edu tick_cmpr = val; 3986335Sgblack@eecs.umich.edu break; 3996335Sgblack@eecs.umich.edu case MISCREG_STICK: 4006335Sgblack@eecs.umich.edu stick = val; 4016335Sgblack@eecs.umich.edu break; 4026335Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 4036335Sgblack@eecs.umich.edu stick_cmpr = val; 4046335Sgblack@eecs.umich.edu break; 4056335Sgblack@eecs.umich.edu 4066335Sgblack@eecs.umich.edu /** Privilged Registers */ 4076335Sgblack@eecs.umich.edu case MISCREG_TPC: 4086335Sgblack@eecs.umich.edu tpc[tl-1] = val; 4096335Sgblack@eecs.umich.edu break; 4106335Sgblack@eecs.umich.edu case MISCREG_TNPC: 4116335Sgblack@eecs.umich.edu tnpc[tl-1] = val; 4126335Sgblack@eecs.umich.edu break; 4136335Sgblack@eecs.umich.edu case MISCREG_TSTATE: 4146335Sgblack@eecs.umich.edu tstate[tl-1] = val; 4156335Sgblack@eecs.umich.edu break; 4166335Sgblack@eecs.umich.edu case MISCREG_TT: 4176335Sgblack@eecs.umich.edu tt[tl-1] = val; 4186335Sgblack@eecs.umich.edu break; 4196335Sgblack@eecs.umich.edu case MISCREG_PRIVTICK: 4206335Sgblack@eecs.umich.edu panic("Priviliged access to tick regesiters not implemented\n"); 4216335Sgblack@eecs.umich.edu case MISCREG_TBA: 4226335Sgblack@eecs.umich.edu // clear lower 7 bits on writes. 4236335Sgblack@eecs.umich.edu tba = val & ULL(~0x7FFF); 4246335Sgblack@eecs.umich.edu break; 4256335Sgblack@eecs.umich.edu case MISCREG_PSTATE: 4268829Sgblack@eecs.umich.edu pstate = (val & PstateMask); 4276335Sgblack@eecs.umich.edu break; 4286335Sgblack@eecs.umich.edu case MISCREG_TL: 4296335Sgblack@eecs.umich.edu tl = val; 4306335Sgblack@eecs.umich.edu break; 4316335Sgblack@eecs.umich.edu case MISCREG_PIL: 4326335Sgblack@eecs.umich.edu pil = val; 4336335Sgblack@eecs.umich.edu break; 4346335Sgblack@eecs.umich.edu case MISCREG_CWP: 4356335Sgblack@eecs.umich.edu cwp = val; 4366335Sgblack@eecs.umich.edu break; 4376335Sgblack@eecs.umich.edu// case MISCREG_CANSAVE: 4386335Sgblack@eecs.umich.edu// cansave = val; 4396335Sgblack@eecs.umich.edu// break; 4406335Sgblack@eecs.umich.edu// case MISCREG_CANRESTORE: 4416335Sgblack@eecs.umich.edu// canrestore = val; 4426335Sgblack@eecs.umich.edu// break; 4436335Sgblack@eecs.umich.edu// case MISCREG_CLEANWIN: 4446335Sgblack@eecs.umich.edu// cleanwin = val; 4456335Sgblack@eecs.umich.edu// break; 4466335Sgblack@eecs.umich.edu// case MISCREG_OTHERWIN: 4476335Sgblack@eecs.umich.edu// otherwin = val; 4486335Sgblack@eecs.umich.edu// break; 4496335Sgblack@eecs.umich.edu// case MISCREG_WSTATE: 4506335Sgblack@eecs.umich.edu// wstate = val; 4516335Sgblack@eecs.umich.edu// break; 4526335Sgblack@eecs.umich.edu case MISCREG_GL: 4536335Sgblack@eecs.umich.edu gl = val; 4546335Sgblack@eecs.umich.edu break; 4556335Sgblack@eecs.umich.edu 4566335Sgblack@eecs.umich.edu /** Hyper privileged registers */ 4576335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 4586335Sgblack@eecs.umich.edu hpstate = val; 4596335Sgblack@eecs.umich.edu break; 4606335Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 4616335Sgblack@eecs.umich.edu htstate[tl-1] = val; 4626335Sgblack@eecs.umich.edu break; 4636335Sgblack@eecs.umich.edu case MISCREG_HINTP: 4646335Sgblack@eecs.umich.edu hintp = val; 4656335Sgblack@eecs.umich.edu case MISCREG_HTBA: 4666335Sgblack@eecs.umich.edu htba = val; 4676335Sgblack@eecs.umich.edu break; 4686335Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 4696335Sgblack@eecs.umich.edu strandStatusReg = val; 4706335Sgblack@eecs.umich.edu break; 4716335Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 4726335Sgblack@eecs.umich.edu hstick_cmpr = val; 4736335Sgblack@eecs.umich.edu break; 4746335Sgblack@eecs.umich.edu 4756335Sgblack@eecs.umich.edu /** Floating Point Status Register */ 4766335Sgblack@eecs.umich.edu case MISCREG_FSR: 4776335Sgblack@eecs.umich.edu fsr = val; 4786335Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr); 4796335Sgblack@eecs.umich.edu break; 4806335Sgblack@eecs.umich.edu 4816335Sgblack@eecs.umich.edu case MISCREG_MMU_P_CONTEXT: 4826335Sgblack@eecs.umich.edu priContext = val; 4836335Sgblack@eecs.umich.edu break; 4846335Sgblack@eecs.umich.edu case MISCREG_MMU_S_CONTEXT: 4856335Sgblack@eecs.umich.edu secContext = val; 4866335Sgblack@eecs.umich.edu break; 4876335Sgblack@eecs.umich.edu case MISCREG_MMU_PART_ID: 4886335Sgblack@eecs.umich.edu partId = val; 4896335Sgblack@eecs.umich.edu break; 4906335Sgblack@eecs.umich.edu case MISCREG_MMU_LSU_CTRL: 4916335Sgblack@eecs.umich.edu lsuCtrlReg = val; 4926335Sgblack@eecs.umich.edu break; 4936335Sgblack@eecs.umich.edu 4946335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R0: 4956335Sgblack@eecs.umich.edu scratchPad[0] = val; 4966335Sgblack@eecs.umich.edu break; 4976335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R1: 4986335Sgblack@eecs.umich.edu scratchPad[1] = val; 4996335Sgblack@eecs.umich.edu break; 5006335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R2: 5016335Sgblack@eecs.umich.edu scratchPad[2] = val; 5026335Sgblack@eecs.umich.edu break; 5036335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R3: 5046335Sgblack@eecs.umich.edu scratchPad[3] = val; 5056335Sgblack@eecs.umich.edu break; 5066335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R4: 5076335Sgblack@eecs.umich.edu scratchPad[4] = val; 5086335Sgblack@eecs.umich.edu break; 5096335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R5: 5106335Sgblack@eecs.umich.edu scratchPad[5] = val; 5116335Sgblack@eecs.umich.edu break; 5126335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R6: 5136335Sgblack@eecs.umich.edu scratchPad[6] = val; 5146335Sgblack@eecs.umich.edu break; 5156335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R7: 5166335Sgblack@eecs.umich.edu scratchPad[7] = val; 5176335Sgblack@eecs.umich.edu break; 5186335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 5196335Sgblack@eecs.umich.edu cpu_mondo_head = val; 5206335Sgblack@eecs.umich.edu break; 5216335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 5226335Sgblack@eecs.umich.edu cpu_mondo_tail = val; 5236335Sgblack@eecs.umich.edu break; 5246335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 5256335Sgblack@eecs.umich.edu dev_mondo_head = val; 5266335Sgblack@eecs.umich.edu break; 5276335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 5286335Sgblack@eecs.umich.edu dev_mondo_tail = val; 5296335Sgblack@eecs.umich.edu break; 5306335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 5316335Sgblack@eecs.umich.edu res_error_head = val; 5326335Sgblack@eecs.umich.edu break; 5336335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 5346335Sgblack@eecs.umich.edu res_error_tail = val; 5356335Sgblack@eecs.umich.edu break; 5366335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 5376335Sgblack@eecs.umich.edu nres_error_head = val; 5386335Sgblack@eecs.umich.edu break; 5396335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 5406335Sgblack@eecs.umich.edu nres_error_tail = val; 5416335Sgblack@eecs.umich.edu break; 5426335Sgblack@eecs.umich.edu default: 5436335Sgblack@eecs.umich.edu panic("Miscellaneous register %d not implemented\n", miscReg); 5446335Sgblack@eecs.umich.edu } 5456313Sgblack@eecs.umich.edu} 5466313Sgblack@eecs.umich.edu 5476313Sgblack@eecs.umich.eduvoid 5486335Sgblack@eecs.umich.eduISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 5496313Sgblack@eecs.umich.edu{ 5506335Sgblack@eecs.umich.edu MiscReg new_val = val; 5516335Sgblack@eecs.umich.edu 5526335Sgblack@eecs.umich.edu switch (miscReg) { 5539375Sgblack@eecs.umich.edu case MISCREG_ASI: 5549377Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(val); 5559375Sgblack@eecs.umich.edu break; 5566335Sgblack@eecs.umich.edu case MISCREG_STICK: 5576335Sgblack@eecs.umich.edu case MISCREG_TICK: 5586335Sgblack@eecs.umich.edu // stick and tick are same thing on niagra 5596335Sgblack@eecs.umich.edu // use stick for offset and tick for holding intrrupt bit 5606335Sgblack@eecs.umich.edu stick = mbits(val,62,0) - tc->getCpuPtr()->instCount(); 5616335Sgblack@eecs.umich.edu tick = mbits(val,63,63); 5626335Sgblack@eecs.umich.edu DPRINTF(Timer, "Writing TICK=%#X\n", val); 5636335Sgblack@eecs.umich.edu break; 5646335Sgblack@eecs.umich.edu case MISCREG_FPRS: 5657741Sgblack@eecs.umich.edu // Configure the fpu based on the fprs 5666335Sgblack@eecs.umich.edu break; 5676335Sgblack@eecs.umich.edu case MISCREG_PCR: 5687741Sgblack@eecs.umich.edu // Set up performance counting based on pcr value 5696335Sgblack@eecs.umich.edu break; 5706335Sgblack@eecs.umich.edu case MISCREG_PSTATE: 5718829Sgblack@eecs.umich.edu pstate = val & PstateMask; 5726335Sgblack@eecs.umich.edu return; 5736335Sgblack@eecs.umich.edu case MISCREG_TL: 5748829Sgblack@eecs.umich.edu { 5758829Sgblack@eecs.umich.edu tl = val; 5768829Sgblack@eecs.umich.edu if (hpstate.tlz && tl == 0 && !hpstate.hpriv) 5778829Sgblack@eecs.umich.edu tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); 5788829Sgblack@eecs.umich.edu else 5798829Sgblack@eecs.umich.edu tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); 5808829Sgblack@eecs.umich.edu return; 5818829Sgblack@eecs.umich.edu } 5826335Sgblack@eecs.umich.edu case MISCREG_CWP: 5836335Sgblack@eecs.umich.edu new_val = val >= NWindows ? NWindows - 1 : val; 5846335Sgblack@eecs.umich.edu if (val >= NWindows) 5856335Sgblack@eecs.umich.edu new_val = NWindows - 1; 5866337Sgblack@eecs.umich.edu 5876337Sgblack@eecs.umich.edu installWindow(new_val, CurrentWindowOffset); 5886337Sgblack@eecs.umich.edu installWindow(new_val - 1, NextWindowOffset); 5896337Sgblack@eecs.umich.edu installWindow(new_val + 1, PreviousWindowOffset); 5906335Sgblack@eecs.umich.edu break; 5916335Sgblack@eecs.umich.edu case MISCREG_GL: 5926337Sgblack@eecs.umich.edu installGlobals(val, CurrentGlobalsOffset); 5936337Sgblack@eecs.umich.edu installGlobals(val, NextGlobalsOffset); 5946337Sgblack@eecs.umich.edu installGlobals(val, PreviousGlobalsOffset); 5956335Sgblack@eecs.umich.edu break; 5966335Sgblack@eecs.umich.edu case MISCREG_PIL: 5976335Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 5986335Sgblack@eecs.umich.edu case MISCREG_SOFTINT_SET: 5996335Sgblack@eecs.umich.edu case MISCREG_SOFTINT_CLR: 6006335Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 6016335Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 6026335Sgblack@eecs.umich.edu case MISCREG_HINTP: 6036335Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 6046335Sgblack@eecs.umich.edu case MISCREG_HTBA: 6056335Sgblack@eecs.umich.edu case MISCREG_HVER: 6066335Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 6076335Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 6086335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 6096335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 6106335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 6116335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 6126335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 6136335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 6146335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 6156335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 6166335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 6176335Sgblack@eecs.umich.edu setFSReg(miscReg, val, tc); 6186335Sgblack@eecs.umich.edu return; 6196335Sgblack@eecs.umich.edu } 6206335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, new_val); 6216335Sgblack@eecs.umich.edu} 6226335Sgblack@eecs.umich.edu 6236335Sgblack@eecs.umich.eduvoid 6246335Sgblack@eecs.umich.eduISA::serialize(EventManager *em, std::ostream &os) 6256335Sgblack@eecs.umich.edu{ 6266335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(asi); 6276335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tick); 6286335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(fprs); 6296335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(gsr); 6306335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(softint); 6316335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tick_cmpr); 6326335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(stick); 6336335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(stick_cmpr); 6346335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(tpc,MaxTL); 6356335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(tnpc,MaxTL); 6366335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(tstate,MaxTL); 6376335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(tt,MaxTL); 6386335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tba); 6398829Sgblack@eecs.umich.edu SERIALIZE_SCALAR((uint16_t)pstate); 6406335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tl); 6416335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(pil); 6426335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cwp); 6436335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(gl); 6448829Sgblack@eecs.umich.edu SERIALIZE_SCALAR((uint64_t)hpstate); 6456335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(htstate,MaxTL); 6466335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(hintp); 6476335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(htba); 6486335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(hstick_cmpr); 6496335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(strandStatusReg); 6506335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(fsr); 6516335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(priContext); 6526335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(secContext); 6536335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(partId); 6546335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(lsuCtrlReg); 6556335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(scratchPad,8); 6566335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cpu_mondo_head); 6576335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cpu_mondo_tail); 6586335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(dev_mondo_head); 6596335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(dev_mondo_tail); 6606335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(res_error_head); 6616335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(res_error_tail); 6626335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(nres_error_head); 6636335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(nres_error_tail); 6646335Sgblack@eecs.umich.edu Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0; 6656335Sgblack@eecs.umich.edu ThreadContext *tc = NULL; 6666335Sgblack@eecs.umich.edu BaseCPU *cpu = NULL; 6676335Sgblack@eecs.umich.edu int tc_num = 0; 6686335Sgblack@eecs.umich.edu bool tick_intr_sched = true; 6696335Sgblack@eecs.umich.edu 6706335Sgblack@eecs.umich.edu if (tickCompare) 6716335Sgblack@eecs.umich.edu tc = tickCompare->getTC(); 6726335Sgblack@eecs.umich.edu else if (sTickCompare) 6736335Sgblack@eecs.umich.edu tc = sTickCompare->getTC(); 6746335Sgblack@eecs.umich.edu else if (hSTickCompare) 6756335Sgblack@eecs.umich.edu tc = hSTickCompare->getTC(); 6766335Sgblack@eecs.umich.edu else 6776335Sgblack@eecs.umich.edu tick_intr_sched = false; 6786335Sgblack@eecs.umich.edu 6796335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tick_intr_sched); 6806335Sgblack@eecs.umich.edu 6816335Sgblack@eecs.umich.edu if (tc) { 6826335Sgblack@eecs.umich.edu cpu = tc->getCpuPtr(); 6836335Sgblack@eecs.umich.edu tc_num = cpu->findContext(tc); 6846335Sgblack@eecs.umich.edu if (tickCompare && tickCompare->scheduled()) 6856335Sgblack@eecs.umich.edu tick_cmp = tickCompare->when(); 6866335Sgblack@eecs.umich.edu if (sTickCompare && sTickCompare->scheduled()) 6876335Sgblack@eecs.umich.edu stick_cmp = sTickCompare->when(); 6886335Sgblack@eecs.umich.edu if (hSTickCompare && hSTickCompare->scheduled()) 6896335Sgblack@eecs.umich.edu hstick_cmp = hSTickCompare->when(); 6906335Sgblack@eecs.umich.edu 6916335Sgblack@eecs.umich.edu SERIALIZE_OBJPTR(cpu); 6926335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tc_num); 6936335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tick_cmp); 6946335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(stick_cmp); 6956335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(hstick_cmp); 6966335Sgblack@eecs.umich.edu } 6976335Sgblack@eecs.umich.edu} 6986335Sgblack@eecs.umich.edu 6996335Sgblack@eecs.umich.eduvoid 7006335Sgblack@eecs.umich.eduISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) 7016335Sgblack@eecs.umich.edu{ 7026335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(asi); 7036335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tick); 7046335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(fprs); 7056335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(gsr); 7066335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(softint); 7076335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tick_cmpr); 7086335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(stick); 7096335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(stick_cmpr); 7106335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(tpc,MaxTL); 7116335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(tnpc,MaxTL); 7126335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(tstate,MaxTL); 7136335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(tt,MaxTL); 7146335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tba); 7158829Sgblack@eecs.umich.edu { 7168829Sgblack@eecs.umich.edu uint16_t pstate; 7178829Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(pstate); 7188829Sgblack@eecs.umich.edu this->pstate = pstate; 7198829Sgblack@eecs.umich.edu } 7206335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tl); 7216335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(pil); 7226335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cwp); 7236335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(gl); 7246337Sgblack@eecs.umich.edu reloadRegMap(); 7258829Sgblack@eecs.umich.edu { 7268829Sgblack@eecs.umich.edu uint64_t hpstate; 7278829Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(hpstate); 7288829Sgblack@eecs.umich.edu this->hpstate = hpstate; 7298829Sgblack@eecs.umich.edu } 7306335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(htstate,MaxTL); 7316335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(hintp); 7326335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(htba); 7336335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(hstick_cmpr); 7346335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(strandStatusReg); 7356335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(fsr); 7366335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(priContext); 7376335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(secContext); 7386335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(partId); 7396335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(lsuCtrlReg); 7406335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(scratchPad,8); 7416335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cpu_mondo_head); 7426335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cpu_mondo_tail); 7436335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(dev_mondo_head); 7446335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(dev_mondo_tail); 7456335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(res_error_head); 7466335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(res_error_tail); 7476335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(nres_error_head); 7486335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(nres_error_tail); 7496335Sgblack@eecs.umich.edu 7506335Sgblack@eecs.umich.edu Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0; 7516335Sgblack@eecs.umich.edu ThreadContext *tc = NULL; 7526335Sgblack@eecs.umich.edu BaseCPU *cpu = NULL; 7536335Sgblack@eecs.umich.edu int tc_num; 7546335Sgblack@eecs.umich.edu bool tick_intr_sched; 7556335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tick_intr_sched); 7566335Sgblack@eecs.umich.edu if (tick_intr_sched) { 7576335Sgblack@eecs.umich.edu UNSERIALIZE_OBJPTR(cpu); 7586335Sgblack@eecs.umich.edu if (cpu) { 7596335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tc_num); 7606335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tick_cmp); 7616335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(stick_cmp); 7626335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(hstick_cmp); 7636335Sgblack@eecs.umich.edu tc = cpu->getContext(tc_num); 7646335Sgblack@eecs.umich.edu 7656335Sgblack@eecs.umich.edu if (tick_cmp) { 7666335Sgblack@eecs.umich.edu tickCompare = new TickCompareEvent(this, tc); 7676335Sgblack@eecs.umich.edu em->schedule(tickCompare, tick_cmp); 7686335Sgblack@eecs.umich.edu } 7696335Sgblack@eecs.umich.edu if (stick_cmp) { 7706335Sgblack@eecs.umich.edu sTickCompare = new STickCompareEvent(this, tc); 7716335Sgblack@eecs.umich.edu em->schedule(sTickCompare, stick_cmp); 7726335Sgblack@eecs.umich.edu } 7736335Sgblack@eecs.umich.edu if (hstick_cmp) { 7746335Sgblack@eecs.umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 7756335Sgblack@eecs.umich.edu em->schedule(hSTickCompare, hstick_cmp); 7766335Sgblack@eecs.umich.edu } 7776335Sgblack@eecs.umich.edu } 7786335Sgblack@eecs.umich.edu } 7796335Sgblack@eecs.umich.edu 7806313Sgblack@eecs.umich.edu} 7816313Sgblack@eecs.umich.edu 7826313Sgblack@eecs.umich.edu} 783