isa.cc revision 11793
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 36313Sgblack@eecs.umich.edu * All rights reserved. 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146313Sgblack@eecs.umich.edu * this software without specific prior written permission. 156313Sgblack@eecs.umich.edu * 166313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * Authors: Gabe Black 296313Sgblack@eecs.umich.edu */ 306313Sgblack@eecs.umich.edu 3111793Sbrandon.potter@amd.com#include "arch/sparc/isa.hh" 3211793Sbrandon.potter@amd.com 336335Sgblack@eecs.umich.edu#include "arch/sparc/asi.hh" 349377Sgblack@eecs.umich.edu#include "arch/sparc/decoder.hh" 356335Sgblack@eecs.umich.edu#include "base/bitfield.hh" 366335Sgblack@eecs.umich.edu#include "base/trace.hh" 376335Sgblack@eecs.umich.edu#include "cpu/base.hh" 386313Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 398232Snate@binkert.org#include "debug/MiscRegs.hh" 408232Snate@binkert.org#include "debug/Timer.hh" 419384SAndreas.Sandberg@arm.com#include "params/SparcISA.hh" 426313Sgblack@eecs.umich.edu 436313Sgblack@eecs.umich.edunamespace SparcISA 446313Sgblack@eecs.umich.edu{ 456313Sgblack@eecs.umich.edu 468829Sgblack@eecs.umich.edustatic PSTATE 478829Sgblack@eecs.umich.edubuildPstateMask() 486335Sgblack@eecs.umich.edu{ 498829Sgblack@eecs.umich.edu PSTATE mask = 0; 508829Sgblack@eecs.umich.edu mask.ie = 1; 518829Sgblack@eecs.umich.edu mask.priv = 1; 528829Sgblack@eecs.umich.edu mask.am = 1; 538829Sgblack@eecs.umich.edu mask.pef = 1; 548829Sgblack@eecs.umich.edu mask.mm = 3; 558829Sgblack@eecs.umich.edu mask.tle = 1; 568829Sgblack@eecs.umich.edu mask.cle = 1; 578829Sgblack@eecs.umich.edu mask.pid1 = 1; 588829Sgblack@eecs.umich.edu return mask; 598829Sgblack@eecs.umich.edu} 608829Sgblack@eecs.umich.edu 618829Sgblack@eecs.umich.edustatic const PSTATE PstateMask = buildPstateMask(); 626335Sgblack@eecs.umich.edu 639384SAndreas.Sandberg@arm.comISA::ISA(Params *p) 649384SAndreas.Sandberg@arm.com : SimObject(p) 659384SAndreas.Sandberg@arm.com{ 669384SAndreas.Sandberg@arm.com tickCompare = NULL; 679384SAndreas.Sandberg@arm.com sTickCompare = NULL; 689384SAndreas.Sandberg@arm.com hSTickCompare = NULL; 699384SAndreas.Sandberg@arm.com 709384SAndreas.Sandberg@arm.com clear(); 719384SAndreas.Sandberg@arm.com} 729384SAndreas.Sandberg@arm.com 739384SAndreas.Sandberg@arm.comconst SparcISAParams * 749384SAndreas.Sandberg@arm.comISA::params() const 759384SAndreas.Sandberg@arm.com{ 769384SAndreas.Sandberg@arm.com return dynamic_cast<const Params *>(_params); 779384SAndreas.Sandberg@arm.com} 789384SAndreas.Sandberg@arm.com 796313Sgblack@eecs.umich.eduvoid 806337Sgblack@eecs.umich.eduISA::reloadRegMap() 816337Sgblack@eecs.umich.edu{ 826337Sgblack@eecs.umich.edu installGlobals(gl, CurrentGlobalsOffset); 836337Sgblack@eecs.umich.edu installWindow(cwp, CurrentWindowOffset); 846337Sgblack@eecs.umich.edu // Microcode registers. 856337Sgblack@eecs.umich.edu for (int i = 0; i < NumMicroIntRegs; i++) 866337Sgblack@eecs.umich.edu intRegMap[MicroIntOffset + i] = i + TotalGlobals + NWindows * 16; 876337Sgblack@eecs.umich.edu installGlobals(gl, NextGlobalsOffset); 886337Sgblack@eecs.umich.edu installWindow(cwp - 1, NextWindowOffset); 896337Sgblack@eecs.umich.edu installGlobals(gl, PreviousGlobalsOffset); 906337Sgblack@eecs.umich.edu installWindow(cwp + 1, PreviousWindowOffset); 916337Sgblack@eecs.umich.edu} 926337Sgblack@eecs.umich.edu 936337Sgblack@eecs.umich.eduvoid 946337Sgblack@eecs.umich.eduISA::installWindow(int cwp, int offset) 956337Sgblack@eecs.umich.edu{ 966337Sgblack@eecs.umich.edu assert(offset >= 0 && offset + NumWindowedRegs <= NumIntRegs); 976337Sgblack@eecs.umich.edu RegIndex *mapChunk = intRegMap + offset; 986337Sgblack@eecs.umich.edu for (int i = 0; i < NumWindowedRegs; i++) 996337Sgblack@eecs.umich.edu mapChunk[i] = TotalGlobals + 1006337Sgblack@eecs.umich.edu ((i - cwp * RegsPerWindow + TotalWindowed) % (TotalWindowed)); 1016337Sgblack@eecs.umich.edu} 1026337Sgblack@eecs.umich.edu 1036337Sgblack@eecs.umich.eduvoid 1046337Sgblack@eecs.umich.eduISA::installGlobals(int gl, int offset) 1056337Sgblack@eecs.umich.edu{ 1066337Sgblack@eecs.umich.edu assert(offset >= 0 && offset + NumGlobalRegs <= NumIntRegs); 1076337Sgblack@eecs.umich.edu RegIndex *mapChunk = intRegMap + offset; 1086337Sgblack@eecs.umich.edu mapChunk[0] = 0; 1096337Sgblack@eecs.umich.edu for (int i = 1; i < NumGlobalRegs; i++) 1106337Sgblack@eecs.umich.edu mapChunk[i] = i + gl * NumGlobalRegs; 1116337Sgblack@eecs.umich.edu} 1126337Sgblack@eecs.umich.edu 1136337Sgblack@eecs.umich.eduvoid 1146313Sgblack@eecs.umich.eduISA::clear() 1156313Sgblack@eecs.umich.edu{ 1166337Sgblack@eecs.umich.edu cwp = 0; 1176337Sgblack@eecs.umich.edu gl = 0; 1186337Sgblack@eecs.umich.edu reloadRegMap(); 1196337Sgblack@eecs.umich.edu 1207741Sgblack@eecs.umich.edu // y = 0; 1217741Sgblack@eecs.umich.edu // ccr = 0; 1226335Sgblack@eecs.umich.edu asi = 0; 1236335Sgblack@eecs.umich.edu tick = ULL(1) << 63; 1246335Sgblack@eecs.umich.edu fprs = 0; 1256335Sgblack@eecs.umich.edu gsr = 0; 1266335Sgblack@eecs.umich.edu softint = 0; 1276335Sgblack@eecs.umich.edu tick_cmpr = 0; 1286335Sgblack@eecs.umich.edu stick = 0; 1296335Sgblack@eecs.umich.edu stick_cmpr = 0; 1306335Sgblack@eecs.umich.edu memset(tpc, 0, sizeof(tpc)); 1316335Sgblack@eecs.umich.edu memset(tnpc, 0, sizeof(tnpc)); 1326335Sgblack@eecs.umich.edu memset(tstate, 0, sizeof(tstate)); 1336335Sgblack@eecs.umich.edu memset(tt, 0, sizeof(tt)); 1347703Sgblack@eecs.umich.edu tba = 0; 1356335Sgblack@eecs.umich.edu pstate = 0; 1366335Sgblack@eecs.umich.edu tl = 0; 1376335Sgblack@eecs.umich.edu pil = 0; 1387741Sgblack@eecs.umich.edu // cansave = 0; 1397741Sgblack@eecs.umich.edu // canrestore = 0; 1407741Sgblack@eecs.umich.edu // cleanwin = 0; 1417741Sgblack@eecs.umich.edu // otherwin = 0; 1427741Sgblack@eecs.umich.edu // wstate = 0; 1437741Sgblack@eecs.umich.edu // In a T1, bit 11 is apparently always 1 1448829Sgblack@eecs.umich.edu hpstate = 0; 1458829Sgblack@eecs.umich.edu hpstate.id = 1; 1466335Sgblack@eecs.umich.edu memset(htstate, 0, sizeof(htstate)); 1476335Sgblack@eecs.umich.edu hintp = 0; 1486335Sgblack@eecs.umich.edu htba = 0; 1496335Sgblack@eecs.umich.edu hstick_cmpr = 0; 1507741Sgblack@eecs.umich.edu // This is set this way in Legion for some reason 1516335Sgblack@eecs.umich.edu strandStatusReg = 0x50000; 1526335Sgblack@eecs.umich.edu fsr = 0; 1536335Sgblack@eecs.umich.edu 1546335Sgblack@eecs.umich.edu priContext = 0; 1556335Sgblack@eecs.umich.edu secContext = 0; 1566335Sgblack@eecs.umich.edu partId = 0; 1576335Sgblack@eecs.umich.edu lsuCtrlReg = 0; 1586335Sgblack@eecs.umich.edu 1596335Sgblack@eecs.umich.edu memset(scratchPad, 0, sizeof(scratchPad)); 1607703Sgblack@eecs.umich.edu 1617703Sgblack@eecs.umich.edu cpu_mondo_head = 0; 1627703Sgblack@eecs.umich.edu cpu_mondo_tail = 0; 1637703Sgblack@eecs.umich.edu dev_mondo_head = 0; 1647703Sgblack@eecs.umich.edu dev_mondo_tail = 0; 1657703Sgblack@eecs.umich.edu res_error_head = 0; 1667703Sgblack@eecs.umich.edu res_error_tail = 0; 1677703Sgblack@eecs.umich.edu nres_error_head = 0; 1687703Sgblack@eecs.umich.edu nres_error_tail = 0; 1697703Sgblack@eecs.umich.edu 1707703Sgblack@eecs.umich.edu // If one of these events is active, it's not obvious to me how to get 1717703Sgblack@eecs.umich.edu // rid of it cleanly. For now we'll just assert that they're not. 1727703Sgblack@eecs.umich.edu if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL) 1737703Sgblack@eecs.umich.edu panic("Tick comparison event active when clearing the ISA object.\n"); 1746313Sgblack@eecs.umich.edu} 1756313Sgblack@eecs.umich.edu 1766313Sgblack@eecs.umich.eduMiscReg 17710698Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int miscReg) const 1786313Sgblack@eecs.umich.edu{ 1796335Sgblack@eecs.umich.edu 1806335Sgblack@eecs.umich.edu // The three miscRegs are moved up from the switch statement 1816335Sgblack@eecs.umich.edu // due to more frequent calls. 1826335Sgblack@eecs.umich.edu 1836335Sgblack@eecs.umich.edu if (miscReg == MISCREG_GL) 1846335Sgblack@eecs.umich.edu return gl; 1856335Sgblack@eecs.umich.edu if (miscReg == MISCREG_CWP) 1866335Sgblack@eecs.umich.edu return cwp; 1876335Sgblack@eecs.umich.edu if (miscReg == MISCREG_TLB_DATA) { 1886335Sgblack@eecs.umich.edu /* Package up all the data for the tlb: 1896335Sgblack@eecs.umich.edu * 6666555555555544444444443333333333222222222211111111110000000000 1906335Sgblack@eecs.umich.edu * 3210987654321098765432109876543210987654321098765432109876543210 1916335Sgblack@eecs.umich.edu * secContext | priContext | |tl|partid| |||||^hpriv 1926335Sgblack@eecs.umich.edu * ||||^red 1936335Sgblack@eecs.umich.edu * |||^priv 1946335Sgblack@eecs.umich.edu * ||^am 1956335Sgblack@eecs.umich.edu * |^lsuim 1966335Sgblack@eecs.umich.edu * ^lsudm 1976335Sgblack@eecs.umich.edu */ 1988829Sgblack@eecs.umich.edu return (uint64_t)hpstate.hpriv | 1998829Sgblack@eecs.umich.edu (uint64_t)hpstate.red << 1 | 2008829Sgblack@eecs.umich.edu (uint64_t)pstate.priv << 2 | 2018829Sgblack@eecs.umich.edu (uint64_t)pstate.am << 3 | 2026335Sgblack@eecs.umich.edu bits((uint64_t)lsuCtrlReg,3,2) << 4 | 2036335Sgblack@eecs.umich.edu bits((uint64_t)partId,7,0) << 8 | 2046335Sgblack@eecs.umich.edu bits((uint64_t)tl,2,0) << 16 | 2056335Sgblack@eecs.umich.edu (uint64_t)priContext << 32 | 2066335Sgblack@eecs.umich.edu (uint64_t)secContext << 48; 2076335Sgblack@eecs.umich.edu } 2086335Sgblack@eecs.umich.edu 2096335Sgblack@eecs.umich.edu switch (miscReg) { 2107741Sgblack@eecs.umich.edu // case MISCREG_TLB_DATA: 2116335Sgblack@eecs.umich.edu // [original contents see above] 2127741Sgblack@eecs.umich.edu // case MISCREG_Y: 2136335Sgblack@eecs.umich.edu // return y; 2147741Sgblack@eecs.umich.edu // case MISCREG_CCR: 2156335Sgblack@eecs.umich.edu // return ccr; 2166335Sgblack@eecs.umich.edu case MISCREG_ASI: 2176335Sgblack@eecs.umich.edu return asi; 2186335Sgblack@eecs.umich.edu case MISCREG_FPRS: 2196335Sgblack@eecs.umich.edu return fprs; 2206335Sgblack@eecs.umich.edu case MISCREG_TICK: 2216335Sgblack@eecs.umich.edu return tick; 2226335Sgblack@eecs.umich.edu case MISCREG_PCR: 2236335Sgblack@eecs.umich.edu panic("PCR not implemented\n"); 2246335Sgblack@eecs.umich.edu case MISCREG_PIC: 2256335Sgblack@eecs.umich.edu panic("PIC not implemented\n"); 2266335Sgblack@eecs.umich.edu case MISCREG_GSR: 2276335Sgblack@eecs.umich.edu return gsr; 2286335Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 2296335Sgblack@eecs.umich.edu return softint; 2306335Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 2316335Sgblack@eecs.umich.edu return tick_cmpr; 2326335Sgblack@eecs.umich.edu case MISCREG_STICK: 2336335Sgblack@eecs.umich.edu return stick; 2346335Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 2356335Sgblack@eecs.umich.edu return stick_cmpr; 2366335Sgblack@eecs.umich.edu 2376335Sgblack@eecs.umich.edu /** Privilged Registers */ 2386335Sgblack@eecs.umich.edu case MISCREG_TPC: 2396335Sgblack@eecs.umich.edu return tpc[tl-1]; 2406335Sgblack@eecs.umich.edu case MISCREG_TNPC: 2416335Sgblack@eecs.umich.edu return tnpc[tl-1]; 2426335Sgblack@eecs.umich.edu case MISCREG_TSTATE: 2436335Sgblack@eecs.umich.edu return tstate[tl-1]; 2446335Sgblack@eecs.umich.edu case MISCREG_TT: 2456335Sgblack@eecs.umich.edu return tt[tl-1]; 2466335Sgblack@eecs.umich.edu case MISCREG_PRIVTICK: 2476335Sgblack@eecs.umich.edu panic("Priviliged access to tick registers not implemented\n"); 2486335Sgblack@eecs.umich.edu case MISCREG_TBA: 2496335Sgblack@eecs.umich.edu return tba; 2506335Sgblack@eecs.umich.edu case MISCREG_PSTATE: 2518829Sgblack@eecs.umich.edu return (MiscReg)pstate; 2526335Sgblack@eecs.umich.edu case MISCREG_TL: 2536335Sgblack@eecs.umich.edu return tl; 2546335Sgblack@eecs.umich.edu case MISCREG_PIL: 2556335Sgblack@eecs.umich.edu return pil; 2567741Sgblack@eecs.umich.edu // CWP, GL moved 2577741Sgblack@eecs.umich.edu // case MISCREG_CWP: 2587741Sgblack@eecs.umich.edu // return cwp; 2597741Sgblack@eecs.umich.edu // case MISCREG_CANSAVE: 2607741Sgblack@eecs.umich.edu // return cansave; 2617741Sgblack@eecs.umich.edu // case MISCREG_CANRESTORE: 2627741Sgblack@eecs.umich.edu // return canrestore; 2637741Sgblack@eecs.umich.edu // case MISCREG_CLEANWIN: 2647741Sgblack@eecs.umich.edu // return cleanwin; 2657741Sgblack@eecs.umich.edu // case MISCREG_OTHERWIN: 2667741Sgblack@eecs.umich.edu // return otherwin; 2677741Sgblack@eecs.umich.edu // case MISCREG_WSTATE: 2687741Sgblack@eecs.umich.edu // return wstate; 2697741Sgblack@eecs.umich.edu // case MISCREG_GL: 2707741Sgblack@eecs.umich.edu // return gl; 2716335Sgblack@eecs.umich.edu 2726335Sgblack@eecs.umich.edu /** Hyper privileged registers */ 2736335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 2748829Sgblack@eecs.umich.edu return (MiscReg)hpstate; 2756335Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 2766335Sgblack@eecs.umich.edu return htstate[tl-1]; 2776335Sgblack@eecs.umich.edu case MISCREG_HINTP: 2786335Sgblack@eecs.umich.edu return hintp; 2796335Sgblack@eecs.umich.edu case MISCREG_HTBA: 2806335Sgblack@eecs.umich.edu return htba; 2816335Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2826335Sgblack@eecs.umich.edu return strandStatusReg; 2836335Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 2846335Sgblack@eecs.umich.edu return hstick_cmpr; 2856335Sgblack@eecs.umich.edu 2866335Sgblack@eecs.umich.edu /** Floating Point Status Register */ 2876335Sgblack@eecs.umich.edu case MISCREG_FSR: 2886335Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr); 2896335Sgblack@eecs.umich.edu return fsr; 2906335Sgblack@eecs.umich.edu 2916335Sgblack@eecs.umich.edu case MISCREG_MMU_P_CONTEXT: 2926335Sgblack@eecs.umich.edu return priContext; 2936335Sgblack@eecs.umich.edu case MISCREG_MMU_S_CONTEXT: 2946335Sgblack@eecs.umich.edu return secContext; 2956335Sgblack@eecs.umich.edu case MISCREG_MMU_PART_ID: 2966335Sgblack@eecs.umich.edu return partId; 2976335Sgblack@eecs.umich.edu case MISCREG_MMU_LSU_CTRL: 2986335Sgblack@eecs.umich.edu return lsuCtrlReg; 2996335Sgblack@eecs.umich.edu 3006335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R0: 3016335Sgblack@eecs.umich.edu return scratchPad[0]; 3026335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R1: 3036335Sgblack@eecs.umich.edu return scratchPad[1]; 3046335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R2: 3056335Sgblack@eecs.umich.edu return scratchPad[2]; 3066335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R3: 3076335Sgblack@eecs.umich.edu return scratchPad[3]; 3086335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R4: 3096335Sgblack@eecs.umich.edu return scratchPad[4]; 3106335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R5: 3116335Sgblack@eecs.umich.edu return scratchPad[5]; 3126335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R6: 3136335Sgblack@eecs.umich.edu return scratchPad[6]; 3146335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R7: 3156335Sgblack@eecs.umich.edu return scratchPad[7]; 3166335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 3176335Sgblack@eecs.umich.edu return cpu_mondo_head; 3186335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 3196335Sgblack@eecs.umich.edu return cpu_mondo_tail; 3206335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 3216335Sgblack@eecs.umich.edu return dev_mondo_head; 3226335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 3236335Sgblack@eecs.umich.edu return dev_mondo_tail; 3246335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 3256335Sgblack@eecs.umich.edu return res_error_head; 3266335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 3276335Sgblack@eecs.umich.edu return res_error_tail; 3286335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 3296335Sgblack@eecs.umich.edu return nres_error_head; 3306335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 3316335Sgblack@eecs.umich.edu return nres_error_tail; 3326335Sgblack@eecs.umich.edu default: 3336335Sgblack@eecs.umich.edu panic("Miscellaneous register %d not implemented\n", miscReg); 3346335Sgblack@eecs.umich.edu } 3356313Sgblack@eecs.umich.edu} 3366313Sgblack@eecs.umich.edu 3376313Sgblack@eecs.umich.eduMiscReg 3386335Sgblack@eecs.umich.eduISA::readMiscReg(int miscReg, ThreadContext * tc) 3396313Sgblack@eecs.umich.edu{ 3406335Sgblack@eecs.umich.edu switch (miscReg) { 3416335Sgblack@eecs.umich.edu // tick and stick are aliased to each other in niagra 3426335Sgblack@eecs.umich.edu // well store the tick data in stick and the interrupt bit in tick 3436335Sgblack@eecs.umich.edu case MISCREG_STICK: 3446335Sgblack@eecs.umich.edu case MISCREG_TICK: 3456335Sgblack@eecs.umich.edu case MISCREG_PRIVTICK: 3466335Sgblack@eecs.umich.edu // I'm not sure why legion ignores the lowest two bits, but we'll go 3476335Sgblack@eecs.umich.edu // with it 3486335Sgblack@eecs.umich.edu // change from curCycle() to instCount() until we're done with legion 3496335Sgblack@eecs.umich.edu DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n", 3506335Sgblack@eecs.umich.edu tc->getCpuPtr()->instCount(), stick); 3516335Sgblack@eecs.umich.edu return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) | 3526335Sgblack@eecs.umich.edu mbits(tick,63,63); 3536335Sgblack@eecs.umich.edu case MISCREG_FPRS: 3546335Sgblack@eecs.umich.edu // in legion if fp is enabled du and dl are set 3556335Sgblack@eecs.umich.edu return fprs | 0x3; 3566335Sgblack@eecs.umich.edu case MISCREG_PCR: 3576335Sgblack@eecs.umich.edu case MISCREG_PIC: 3586335Sgblack@eecs.umich.edu panic("Performance Instrumentation not impl\n"); 3596335Sgblack@eecs.umich.edu case MISCREG_SOFTINT_CLR: 3606335Sgblack@eecs.umich.edu case MISCREG_SOFTINT_SET: 3616335Sgblack@eecs.umich.edu panic("Can read from softint clr/set\n"); 3626335Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 3636335Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 3646335Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 3656335Sgblack@eecs.umich.edu case MISCREG_HINTP: 3666335Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 3676335Sgblack@eecs.umich.edu case MISCREG_HTBA: 3686335Sgblack@eecs.umich.edu case MISCREG_HVER: 3696335Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 3706335Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 3716335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 3726335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 3736335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 3746335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 3756335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 3766335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 3776335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 3786335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 3796335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 3806335Sgblack@eecs.umich.edu return readFSReg(miscReg, tc); 3816335Sgblack@eecs.umich.edu } 3826335Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg); 3836313Sgblack@eecs.umich.edu} 3846313Sgblack@eecs.umich.edu 3856313Sgblack@eecs.umich.eduvoid 3866335Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int miscReg, MiscReg val) 3876313Sgblack@eecs.umich.edu{ 3886335Sgblack@eecs.umich.edu switch (miscReg) { 3896335Sgblack@eecs.umich.edu// case MISCREG_Y: 3906335Sgblack@eecs.umich.edu// y = val; 3916335Sgblack@eecs.umich.edu// break; 3926335Sgblack@eecs.umich.edu// case MISCREG_CCR: 3936335Sgblack@eecs.umich.edu// ccr = val; 3946335Sgblack@eecs.umich.edu// break; 3956335Sgblack@eecs.umich.edu case MISCREG_ASI: 3966335Sgblack@eecs.umich.edu asi = val; 3976335Sgblack@eecs.umich.edu break; 3986335Sgblack@eecs.umich.edu case MISCREG_FPRS: 3996335Sgblack@eecs.umich.edu fprs = val; 4006335Sgblack@eecs.umich.edu break; 4016335Sgblack@eecs.umich.edu case MISCREG_TICK: 4026335Sgblack@eecs.umich.edu tick = val; 4036335Sgblack@eecs.umich.edu break; 4046335Sgblack@eecs.umich.edu case MISCREG_PCR: 4056335Sgblack@eecs.umich.edu panic("PCR not implemented\n"); 4066335Sgblack@eecs.umich.edu case MISCREG_PIC: 4076335Sgblack@eecs.umich.edu panic("PIC not implemented\n"); 4086335Sgblack@eecs.umich.edu case MISCREG_GSR: 4096335Sgblack@eecs.umich.edu gsr = val; 4106335Sgblack@eecs.umich.edu break; 4116335Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 4126335Sgblack@eecs.umich.edu softint = val; 4136335Sgblack@eecs.umich.edu break; 4146335Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 4156335Sgblack@eecs.umich.edu tick_cmpr = val; 4166335Sgblack@eecs.umich.edu break; 4176335Sgblack@eecs.umich.edu case MISCREG_STICK: 4186335Sgblack@eecs.umich.edu stick = val; 4196335Sgblack@eecs.umich.edu break; 4206335Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 4216335Sgblack@eecs.umich.edu stick_cmpr = val; 4226335Sgblack@eecs.umich.edu break; 4236335Sgblack@eecs.umich.edu 4246335Sgblack@eecs.umich.edu /** Privilged Registers */ 4256335Sgblack@eecs.umich.edu case MISCREG_TPC: 4266335Sgblack@eecs.umich.edu tpc[tl-1] = val; 4276335Sgblack@eecs.umich.edu break; 4286335Sgblack@eecs.umich.edu case MISCREG_TNPC: 4296335Sgblack@eecs.umich.edu tnpc[tl-1] = val; 4306335Sgblack@eecs.umich.edu break; 4316335Sgblack@eecs.umich.edu case MISCREG_TSTATE: 4326335Sgblack@eecs.umich.edu tstate[tl-1] = val; 4336335Sgblack@eecs.umich.edu break; 4346335Sgblack@eecs.umich.edu case MISCREG_TT: 4356335Sgblack@eecs.umich.edu tt[tl-1] = val; 4366335Sgblack@eecs.umich.edu break; 4376335Sgblack@eecs.umich.edu case MISCREG_PRIVTICK: 4386335Sgblack@eecs.umich.edu panic("Priviliged access to tick regesiters not implemented\n"); 4396335Sgblack@eecs.umich.edu case MISCREG_TBA: 4406335Sgblack@eecs.umich.edu // clear lower 7 bits on writes. 4416335Sgblack@eecs.umich.edu tba = val & ULL(~0x7FFF); 4426335Sgblack@eecs.umich.edu break; 4436335Sgblack@eecs.umich.edu case MISCREG_PSTATE: 4448829Sgblack@eecs.umich.edu pstate = (val & PstateMask); 4456335Sgblack@eecs.umich.edu break; 4466335Sgblack@eecs.umich.edu case MISCREG_TL: 4476335Sgblack@eecs.umich.edu tl = val; 4486335Sgblack@eecs.umich.edu break; 4496335Sgblack@eecs.umich.edu case MISCREG_PIL: 4506335Sgblack@eecs.umich.edu pil = val; 4516335Sgblack@eecs.umich.edu break; 4526335Sgblack@eecs.umich.edu case MISCREG_CWP: 4536335Sgblack@eecs.umich.edu cwp = val; 4546335Sgblack@eecs.umich.edu break; 4556335Sgblack@eecs.umich.edu// case MISCREG_CANSAVE: 4566335Sgblack@eecs.umich.edu// cansave = val; 4576335Sgblack@eecs.umich.edu// break; 4586335Sgblack@eecs.umich.edu// case MISCREG_CANRESTORE: 4596335Sgblack@eecs.umich.edu// canrestore = val; 4606335Sgblack@eecs.umich.edu// break; 4616335Sgblack@eecs.umich.edu// case MISCREG_CLEANWIN: 4626335Sgblack@eecs.umich.edu// cleanwin = val; 4636335Sgblack@eecs.umich.edu// break; 4646335Sgblack@eecs.umich.edu// case MISCREG_OTHERWIN: 4656335Sgblack@eecs.umich.edu// otherwin = val; 4666335Sgblack@eecs.umich.edu// break; 4676335Sgblack@eecs.umich.edu// case MISCREG_WSTATE: 4686335Sgblack@eecs.umich.edu// wstate = val; 4696335Sgblack@eecs.umich.edu// break; 4706335Sgblack@eecs.umich.edu case MISCREG_GL: 4716335Sgblack@eecs.umich.edu gl = val; 4726335Sgblack@eecs.umich.edu break; 4736335Sgblack@eecs.umich.edu 4746335Sgblack@eecs.umich.edu /** Hyper privileged registers */ 4756335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 4766335Sgblack@eecs.umich.edu hpstate = val; 4776335Sgblack@eecs.umich.edu break; 4786335Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 4796335Sgblack@eecs.umich.edu htstate[tl-1] = val; 4806335Sgblack@eecs.umich.edu break; 4816335Sgblack@eecs.umich.edu case MISCREG_HINTP: 4826335Sgblack@eecs.umich.edu hintp = val; 4836335Sgblack@eecs.umich.edu case MISCREG_HTBA: 4846335Sgblack@eecs.umich.edu htba = val; 4856335Sgblack@eecs.umich.edu break; 4866335Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 4876335Sgblack@eecs.umich.edu strandStatusReg = val; 4886335Sgblack@eecs.umich.edu break; 4896335Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 4906335Sgblack@eecs.umich.edu hstick_cmpr = val; 4916335Sgblack@eecs.umich.edu break; 4926335Sgblack@eecs.umich.edu 4936335Sgblack@eecs.umich.edu /** Floating Point Status Register */ 4946335Sgblack@eecs.umich.edu case MISCREG_FSR: 4956335Sgblack@eecs.umich.edu fsr = val; 4966335Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr); 4976335Sgblack@eecs.umich.edu break; 4986335Sgblack@eecs.umich.edu 4996335Sgblack@eecs.umich.edu case MISCREG_MMU_P_CONTEXT: 5006335Sgblack@eecs.umich.edu priContext = val; 5016335Sgblack@eecs.umich.edu break; 5026335Sgblack@eecs.umich.edu case MISCREG_MMU_S_CONTEXT: 5036335Sgblack@eecs.umich.edu secContext = val; 5046335Sgblack@eecs.umich.edu break; 5056335Sgblack@eecs.umich.edu case MISCREG_MMU_PART_ID: 5066335Sgblack@eecs.umich.edu partId = val; 5076335Sgblack@eecs.umich.edu break; 5086335Sgblack@eecs.umich.edu case MISCREG_MMU_LSU_CTRL: 5096335Sgblack@eecs.umich.edu lsuCtrlReg = val; 5106335Sgblack@eecs.umich.edu break; 5116335Sgblack@eecs.umich.edu 5126335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R0: 5136335Sgblack@eecs.umich.edu scratchPad[0] = val; 5146335Sgblack@eecs.umich.edu break; 5156335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R1: 5166335Sgblack@eecs.umich.edu scratchPad[1] = val; 5176335Sgblack@eecs.umich.edu break; 5186335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R2: 5196335Sgblack@eecs.umich.edu scratchPad[2] = val; 5206335Sgblack@eecs.umich.edu break; 5216335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R3: 5226335Sgblack@eecs.umich.edu scratchPad[3] = val; 5236335Sgblack@eecs.umich.edu break; 5246335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R4: 5256335Sgblack@eecs.umich.edu scratchPad[4] = val; 5266335Sgblack@eecs.umich.edu break; 5276335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R5: 5286335Sgblack@eecs.umich.edu scratchPad[5] = val; 5296335Sgblack@eecs.umich.edu break; 5306335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R6: 5316335Sgblack@eecs.umich.edu scratchPad[6] = val; 5326335Sgblack@eecs.umich.edu break; 5336335Sgblack@eecs.umich.edu case MISCREG_SCRATCHPAD_R7: 5346335Sgblack@eecs.umich.edu scratchPad[7] = val; 5356335Sgblack@eecs.umich.edu break; 5366335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 5376335Sgblack@eecs.umich.edu cpu_mondo_head = val; 5386335Sgblack@eecs.umich.edu break; 5396335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 5406335Sgblack@eecs.umich.edu cpu_mondo_tail = val; 5416335Sgblack@eecs.umich.edu break; 5426335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 5436335Sgblack@eecs.umich.edu dev_mondo_head = val; 5446335Sgblack@eecs.umich.edu break; 5456335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 5466335Sgblack@eecs.umich.edu dev_mondo_tail = val; 5476335Sgblack@eecs.umich.edu break; 5486335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 5496335Sgblack@eecs.umich.edu res_error_head = val; 5506335Sgblack@eecs.umich.edu break; 5516335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 5526335Sgblack@eecs.umich.edu res_error_tail = val; 5536335Sgblack@eecs.umich.edu break; 5546335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 5556335Sgblack@eecs.umich.edu nres_error_head = val; 5566335Sgblack@eecs.umich.edu break; 5576335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 5586335Sgblack@eecs.umich.edu nres_error_tail = val; 5596335Sgblack@eecs.umich.edu break; 5606335Sgblack@eecs.umich.edu default: 5616335Sgblack@eecs.umich.edu panic("Miscellaneous register %d not implemented\n", miscReg); 5626335Sgblack@eecs.umich.edu } 5636313Sgblack@eecs.umich.edu} 5646313Sgblack@eecs.umich.edu 5656313Sgblack@eecs.umich.eduvoid 5666335Sgblack@eecs.umich.eduISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 5676313Sgblack@eecs.umich.edu{ 5686335Sgblack@eecs.umich.edu MiscReg new_val = val; 5696335Sgblack@eecs.umich.edu 5706335Sgblack@eecs.umich.edu switch (miscReg) { 5719375Sgblack@eecs.umich.edu case MISCREG_ASI: 5729377Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(val); 5739375Sgblack@eecs.umich.edu break; 5746335Sgblack@eecs.umich.edu case MISCREG_STICK: 5756335Sgblack@eecs.umich.edu case MISCREG_TICK: 5766335Sgblack@eecs.umich.edu // stick and tick are same thing on niagra 5776335Sgblack@eecs.umich.edu // use stick for offset and tick for holding intrrupt bit 5786335Sgblack@eecs.umich.edu stick = mbits(val,62,0) - tc->getCpuPtr()->instCount(); 5796335Sgblack@eecs.umich.edu tick = mbits(val,63,63); 5806335Sgblack@eecs.umich.edu DPRINTF(Timer, "Writing TICK=%#X\n", val); 5816335Sgblack@eecs.umich.edu break; 5826335Sgblack@eecs.umich.edu case MISCREG_FPRS: 5837741Sgblack@eecs.umich.edu // Configure the fpu based on the fprs 5846335Sgblack@eecs.umich.edu break; 5856335Sgblack@eecs.umich.edu case MISCREG_PCR: 5867741Sgblack@eecs.umich.edu // Set up performance counting based on pcr value 5876335Sgblack@eecs.umich.edu break; 5886335Sgblack@eecs.umich.edu case MISCREG_PSTATE: 5898829Sgblack@eecs.umich.edu pstate = val & PstateMask; 5906335Sgblack@eecs.umich.edu return; 5916335Sgblack@eecs.umich.edu case MISCREG_TL: 5928829Sgblack@eecs.umich.edu { 5938829Sgblack@eecs.umich.edu tl = val; 5948829Sgblack@eecs.umich.edu if (hpstate.tlz && tl == 0 && !hpstate.hpriv) 59511150Smitch.hayenga@arm.com tc->getCpuPtr()->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0); 5968829Sgblack@eecs.umich.edu else 59711150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0); 5988829Sgblack@eecs.umich.edu return; 5998829Sgblack@eecs.umich.edu } 6006335Sgblack@eecs.umich.edu case MISCREG_CWP: 6016335Sgblack@eecs.umich.edu new_val = val >= NWindows ? NWindows - 1 : val; 6026335Sgblack@eecs.umich.edu if (val >= NWindows) 6036335Sgblack@eecs.umich.edu new_val = NWindows - 1; 6046337Sgblack@eecs.umich.edu 6056337Sgblack@eecs.umich.edu installWindow(new_val, CurrentWindowOffset); 6066337Sgblack@eecs.umich.edu installWindow(new_val - 1, NextWindowOffset); 6076337Sgblack@eecs.umich.edu installWindow(new_val + 1, PreviousWindowOffset); 6086335Sgblack@eecs.umich.edu break; 6096335Sgblack@eecs.umich.edu case MISCREG_GL: 6106337Sgblack@eecs.umich.edu installGlobals(val, CurrentGlobalsOffset); 6116337Sgblack@eecs.umich.edu installGlobals(val, NextGlobalsOffset); 6126337Sgblack@eecs.umich.edu installGlobals(val, PreviousGlobalsOffset); 6136335Sgblack@eecs.umich.edu break; 6146335Sgblack@eecs.umich.edu case MISCREG_PIL: 6156335Sgblack@eecs.umich.edu case MISCREG_SOFTINT: 6166335Sgblack@eecs.umich.edu case MISCREG_SOFTINT_SET: 6176335Sgblack@eecs.umich.edu case MISCREG_SOFTINT_CLR: 6186335Sgblack@eecs.umich.edu case MISCREG_TICK_CMPR: 6196335Sgblack@eecs.umich.edu case MISCREG_STICK_CMPR: 6206335Sgblack@eecs.umich.edu case MISCREG_HINTP: 6216335Sgblack@eecs.umich.edu case MISCREG_HTSTATE: 6226335Sgblack@eecs.umich.edu case MISCREG_HTBA: 6236335Sgblack@eecs.umich.edu case MISCREG_HVER: 6246335Sgblack@eecs.umich.edu case MISCREG_STRAND_STS_REG: 6256335Sgblack@eecs.umich.edu case MISCREG_HSTICK_CMPR: 6266335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 6276335Sgblack@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 6286335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 6296335Sgblack@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 6306335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 6316335Sgblack@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 6326335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 6336335Sgblack@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 6346335Sgblack@eecs.umich.edu case MISCREG_HPSTATE: 6356335Sgblack@eecs.umich.edu setFSReg(miscReg, val, tc); 6366335Sgblack@eecs.umich.edu return; 6376335Sgblack@eecs.umich.edu } 6386335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, new_val); 6396335Sgblack@eecs.umich.edu} 6406335Sgblack@eecs.umich.edu 6416335Sgblack@eecs.umich.eduvoid 64210905Sandreas.sandberg@arm.comISA::serialize(CheckpointOut &cp) const 6436335Sgblack@eecs.umich.edu{ 6446335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(asi); 6456335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tick); 6466335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(fprs); 6476335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(gsr); 6486335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(softint); 6496335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tick_cmpr); 6506335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(stick); 6516335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(stick_cmpr); 6526335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(tpc,MaxTL); 6536335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(tnpc,MaxTL); 6546335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(tstate,MaxTL); 6556335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(tt,MaxTL); 6566335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tba); 6578829Sgblack@eecs.umich.edu SERIALIZE_SCALAR((uint16_t)pstate); 6586335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tl); 6596335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(pil); 6606335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cwp); 6616335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(gl); 6628829Sgblack@eecs.umich.edu SERIALIZE_SCALAR((uint64_t)hpstate); 6636335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(htstate,MaxTL); 6646335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(hintp); 6656335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(htba); 6666335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(hstick_cmpr); 6676335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(strandStatusReg); 6686335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(fsr); 6696335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(priContext); 6706335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(secContext); 6716335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(partId); 6726335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(lsuCtrlReg); 6736335Sgblack@eecs.umich.edu SERIALIZE_ARRAY(scratchPad,8); 6746335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cpu_mondo_head); 6756335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(cpu_mondo_tail); 6766335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(dev_mondo_head); 6776335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(dev_mondo_tail); 6786335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(res_error_head); 6796335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(res_error_tail); 6806335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(nres_error_head); 6816335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(nres_error_tail); 6826335Sgblack@eecs.umich.edu Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0; 6836335Sgblack@eecs.umich.edu ThreadContext *tc = NULL; 6846335Sgblack@eecs.umich.edu BaseCPU *cpu = NULL; 6856335Sgblack@eecs.umich.edu int tc_num = 0; 6866335Sgblack@eecs.umich.edu bool tick_intr_sched = true; 6876335Sgblack@eecs.umich.edu 6886335Sgblack@eecs.umich.edu if (tickCompare) 6896335Sgblack@eecs.umich.edu tc = tickCompare->getTC(); 6906335Sgblack@eecs.umich.edu else if (sTickCompare) 6916335Sgblack@eecs.umich.edu tc = sTickCompare->getTC(); 6926335Sgblack@eecs.umich.edu else if (hSTickCompare) 6936335Sgblack@eecs.umich.edu tc = hSTickCompare->getTC(); 6946335Sgblack@eecs.umich.edu else 6956335Sgblack@eecs.umich.edu tick_intr_sched = false; 6966335Sgblack@eecs.umich.edu 6976335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tick_intr_sched); 6986335Sgblack@eecs.umich.edu 6996335Sgblack@eecs.umich.edu if (tc) { 7006335Sgblack@eecs.umich.edu cpu = tc->getCpuPtr(); 7016335Sgblack@eecs.umich.edu tc_num = cpu->findContext(tc); 7026335Sgblack@eecs.umich.edu if (tickCompare && tickCompare->scheduled()) 7036335Sgblack@eecs.umich.edu tick_cmp = tickCompare->when(); 7046335Sgblack@eecs.umich.edu if (sTickCompare && sTickCompare->scheduled()) 7056335Sgblack@eecs.umich.edu stick_cmp = sTickCompare->when(); 7066335Sgblack@eecs.umich.edu if (hSTickCompare && hSTickCompare->scheduled()) 7076335Sgblack@eecs.umich.edu hstick_cmp = hSTickCompare->when(); 7086335Sgblack@eecs.umich.edu 7096335Sgblack@eecs.umich.edu SERIALIZE_OBJPTR(cpu); 7106335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tc_num); 7116335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(tick_cmp); 7126335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(stick_cmp); 7136335Sgblack@eecs.umich.edu SERIALIZE_SCALAR(hstick_cmp); 7146335Sgblack@eecs.umich.edu } 7156335Sgblack@eecs.umich.edu} 7166335Sgblack@eecs.umich.edu 7176335Sgblack@eecs.umich.eduvoid 71810905Sandreas.sandberg@arm.comISA::unserialize(CheckpointIn &cp) 7196335Sgblack@eecs.umich.edu{ 7206335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(asi); 7216335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tick); 7226335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(fprs); 7236335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(gsr); 7246335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(softint); 7256335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tick_cmpr); 7266335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(stick); 7276335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(stick_cmpr); 7286335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(tpc,MaxTL); 7296335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(tnpc,MaxTL); 7306335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(tstate,MaxTL); 7316335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(tt,MaxTL); 7326335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tba); 7338829Sgblack@eecs.umich.edu { 7348829Sgblack@eecs.umich.edu uint16_t pstate; 7358829Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(pstate); 7368829Sgblack@eecs.umich.edu this->pstate = pstate; 7378829Sgblack@eecs.umich.edu } 7386335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tl); 7396335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(pil); 7406335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cwp); 7416335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(gl); 7426337Sgblack@eecs.umich.edu reloadRegMap(); 7438829Sgblack@eecs.umich.edu { 7448829Sgblack@eecs.umich.edu uint64_t hpstate; 7458829Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(hpstate); 7468829Sgblack@eecs.umich.edu this->hpstate = hpstate; 7478829Sgblack@eecs.umich.edu } 7486335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(htstate,MaxTL); 7496335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(hintp); 7506335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(htba); 7516335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(hstick_cmpr); 7526335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(strandStatusReg); 7536335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(fsr); 7546335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(priContext); 7556335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(secContext); 7566335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(partId); 7576335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(lsuCtrlReg); 7586335Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(scratchPad,8); 7596335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cpu_mondo_head); 7606335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(cpu_mondo_tail); 7616335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(dev_mondo_head); 7626335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(dev_mondo_tail); 7636335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(res_error_head); 7646335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(res_error_tail); 7656335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(nres_error_head); 7666335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(nres_error_tail); 7676335Sgblack@eecs.umich.edu 7686335Sgblack@eecs.umich.edu Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0; 7696335Sgblack@eecs.umich.edu ThreadContext *tc = NULL; 7706335Sgblack@eecs.umich.edu BaseCPU *cpu = NULL; 7716335Sgblack@eecs.umich.edu int tc_num; 7726335Sgblack@eecs.umich.edu bool tick_intr_sched; 7736335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tick_intr_sched); 7746335Sgblack@eecs.umich.edu if (tick_intr_sched) { 7756335Sgblack@eecs.umich.edu UNSERIALIZE_OBJPTR(cpu); 7766335Sgblack@eecs.umich.edu if (cpu) { 7776335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tc_num); 7786335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(tick_cmp); 7796335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(stick_cmp); 7806335Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(hstick_cmp); 7816335Sgblack@eecs.umich.edu tc = cpu->getContext(tc_num); 7826335Sgblack@eecs.umich.edu 7836335Sgblack@eecs.umich.edu if (tick_cmp) { 7846335Sgblack@eecs.umich.edu tickCompare = new TickCompareEvent(this, tc); 7859425SAndreas.Sandberg@ARM.com schedule(tickCompare, tick_cmp); 7866335Sgblack@eecs.umich.edu } 7876335Sgblack@eecs.umich.edu if (stick_cmp) { 7886335Sgblack@eecs.umich.edu sTickCompare = new STickCompareEvent(this, tc); 7899425SAndreas.Sandberg@ARM.com schedule(sTickCompare, stick_cmp); 7906335Sgblack@eecs.umich.edu } 7916335Sgblack@eecs.umich.edu if (hstick_cmp) { 7926335Sgblack@eecs.umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 7939425SAndreas.Sandberg@ARM.com schedule(hSTickCompare, hstick_cmp); 7946335Sgblack@eecs.umich.edu } 7956335Sgblack@eecs.umich.edu } 7966335Sgblack@eecs.umich.edu } 7976335Sgblack@eecs.umich.edu 7986313Sgblack@eecs.umich.edu} 7996313Sgblack@eecs.umich.edu 8006313Sgblack@eecs.umich.edu} 8019384SAndreas.Sandberg@arm.com 8029384SAndreas.Sandberg@arm.comSparcISA::ISA * 8039384SAndreas.Sandberg@arm.comSparcISAParams::create() 8049384SAndreas.Sandberg@arm.com{ 8059384SAndreas.Sandberg@arm.com return new SparcISA::ISA(this); 8069384SAndreas.Sandberg@arm.com} 807