interrupts.hh revision 3948:bd29868997f4 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_SPARC_INTERRUPT_HH__
30#define __ARCH_SPARC_INTERRUPT_HH__
31
32#include "arch/sparc/faults.hh"
33#include "cpu/thread_context.hh"
34
35namespace SparcISA
36{
37
38enum interrupts_t {
39    trap_level_zero,
40    hstick_match,
41    interrupt_vector,
42    cpu_mondo,
43    dev_mondo,
44    resumable_error,
45    soft_interrupt,
46    num_interrupt_types
47};
48
49    class Interrupts
50    {
51
52      private:
53
54        bool interrupts[num_interrupt_types];
55        int numPosted;
56
57      public:
58        Interrupts()
59        {
60            for (int i = 0; i < num_interrupt_types; ++i) {
61                interrupts[i] = false;
62            }
63            numPosted = 0;
64        }
65
66        void post(int int_type)
67        {
68            if (int_type < 0 || int_type >= num_interrupt_types)
69                panic("posting unknown interrupt!\n");
70
71            if (interrupts[int_type] == false) {
72                interrupts[int_type] = true;
73                ++numPosted;
74            }
75        }
76
77        void post(int int_num, int index)
78        {
79
80        }
81
82        void clear(int int_num, int index)
83        {
84
85        }
86
87        void clear_all()
88        {
89
90        }
91
92        bool check_interrupts(ThreadContext * tc) const
93        {
94            if (numPosted)
95                return true;
96            else
97                return false;
98        }
99
100        Fault getInterrupt(ThreadContext * tc)
101        {
102            int hpstate = tc->readMiscReg(MISCREG_HPSTATE);
103            int pstate = tc->readMiscReg(MISCREG_PSTATE);
104            bool ie = pstate & PSTATE::ie;
105
106            // THESE ARE IN ORDER OF PRIORITY
107            // since there are early returns, and the highest
108            // priority interrupts should get serviced,
109            // it is v. important that new interrupts are inserted
110            // in the right order of processing
111            if (hpstate & HPSTATE::hpriv) {
112                if (ie) {
113                    if (interrupts[hstick_match]) {
114                        if (tc->readMiscReg(MISCREG_HINTP) & 1) {
115                            interrupts[hstick_match] = false;
116                            --numPosted;
117                            return new HstickMatch;
118                        }
119                    }
120                    if (interrupts[interrupt_vector]) {
121                        interrupts[interrupt_vector] = false;
122                        --numPosted;
123                        //HAVEN'T IMPLed THIS YET
124                        return NoFault;
125                    }
126                } else {
127                    if (interrupts[hstick_match]) {
128                        return NoFault;
129                    }
130
131                }
132            } else {
133                if (interrupts[trap_level_zero]) {
134                    if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) {
135                        interrupts[trap_level_zero] = false;
136                        --numPosted;
137                        return new TrapLevelZero;
138                    }
139                }
140                if (interrupts[hstick_match]) {
141                    if (tc->readMiscReg(MISCREG_HINTP) & 1) {
142                        interrupts[hstick_match] = false;
143                        --numPosted;
144                        return new HstickMatch;
145                        }
146                }
147                if (ie) {
148                    if (interrupts[cpu_mondo]) {
149                        interrupts[cpu_mondo] = false;
150                        --numPosted;
151                        return new CpuMondo;
152                    }
153                    if (interrupts[dev_mondo]) {
154                        interrupts[dev_mondo] = false;
155                        --numPosted;
156                        return new DevMondo;
157                    }
158                    if (interrupts[soft_interrupt]) {
159                        int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
160                        // it seems that interrupt vectors are right in
161                        // the middle of interrupt levels with regard to
162                        // priority, so have to check
163                        if ((il < 6) &&
164                            interrupts[interrupt_vector]) {
165                                // may require more details here since there
166                                // may be lots of interrupts embedded in an
167                                // platform interrupt vector
168                                interrupts[interrupt_vector] = false;
169                                --numPosted;
170                                //HAVEN'T IMPLed YET
171                                return NoFault;
172                        } else {
173                            if (il > tc->readMiscReg(MISCREG_PIL)) {
174                                uint64_t si = tc->readMiscReg(MISCREG_SOFTINT);
175                                uint64_t more = si & ~(1 << (il + 1));
176                                if (!InterruptLevel(more)) {
177                                    interrupts[soft_interrupt] = false;
178                                    --numPosted;
179                                }
180                                return new InterruptLevelN(il);
181                            }
182                        }
183                    }
184                    if (interrupts[resumable_error]) {
185                        interrupts[resumable_error] = false;
186                        --numPosted;
187                        return new ResumableError;
188                    }
189                }
190            }
191            return NoFault;
192        }
193
194        void updateIntrInfo(ThreadContext * tc)
195        {
196
197        }
198
199        void serialize(std::ostream &os)
200        {
201        }
202
203        void unserialize(Checkpoint *cp, const std::string &section)
204        {
205        }
206    };
207}
208
209#endif // __ARCH_SPARC_INTERRUPT_HH__
210