faults.hh revision 9554:406fbcf60223
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#ifndef __SPARC_FAULTS_HH__
33#define __SPARC_FAULTS_HH__
34
35#include "cpu/static_inst.hh"
36#include "sim/faults.hh"
37
38// The design of the "name" and "vect" functions is in sim/faults.hh
39
40namespace SparcISA
41{
42
43typedef uint32_t TrapType;
44typedef uint32_t FaultPriority;
45
46class ITB;
47
48class SparcFaultBase : public FaultBase
49{
50  public:
51    enum PrivilegeLevel
52    {
53        U, User = U,
54        P, Privileged = P,
55        H, Hyperprivileged = H,
56        NumLevels,
57        SH = -1,
58        ShouldntHappen = SH
59    };
60    struct FaultVals
61    {
62        const FaultName name;
63        const TrapType trapType;
64        const FaultPriority priority;
65        const PrivilegeLevel nextPrivilegeLevel[NumLevels];
66        FaultStat count;
67    };
68    void invoke(ThreadContext * tc,
69            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
70    virtual TrapType trapType() = 0;
71    virtual FaultPriority priority() = 0;
72    virtual FaultStat & countStat() = 0;
73    virtual PrivilegeLevel getNextLevel(PrivilegeLevel current) = 0;
74};
75
76template<typename T>
77class SparcFault : public SparcFaultBase
78{
79  protected:
80    static FaultVals vals;
81  public:
82    FaultName name() const { return vals.name; }
83    TrapType trapType() { return vals.trapType; }
84    FaultPriority priority() { return vals.priority; }
85    FaultStat & countStat() { return vals.count; }
86
87    PrivilegeLevel
88    getNextLevel(PrivilegeLevel current)
89    {
90        return vals.nextPrivilegeLevel[current];
91    }
92};
93
94class PowerOnReset : public SparcFault<PowerOnReset>
95{
96    void invoke(ThreadContext * tc,
97            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
98};
99
100class WatchDogReset : public SparcFault<WatchDogReset> {};
101
102class ExternallyInitiatedReset : public SparcFault<ExternallyInitiatedReset> {};
103
104class SoftwareInitiatedReset : public SparcFault<SoftwareInitiatedReset> {};
105
106class REDStateException : public SparcFault<REDStateException> {};
107
108class StoreError : public SparcFault<StoreError> {};
109
110class InstructionAccessException : public SparcFault<InstructionAccessException> {};
111
112// class InstructionAccessMMUMiss : public SparcFault<InstructionAccessMMUMiss> {};
113
114class InstructionAccessError : public SparcFault<InstructionAccessError> {};
115
116class IllegalInstruction : public SparcFault<IllegalInstruction> {};
117
118class PrivilegedOpcode : public SparcFault<PrivilegedOpcode> {};
119
120// class UnimplementedLDD : public SparcFault<UnimplementedLDD> {};
121
122// class UnimplementedSTD : public SparcFault<UnimplementedSTD> {};
123
124class FpDisabled : public SparcFault<FpDisabled> {};
125
126class FpExceptionIEEE754 : public SparcFault<FpExceptionIEEE754> {};
127
128class FpExceptionOther : public SparcFault<FpExceptionOther> {};
129
130class TagOverflow : public SparcFault<TagOverflow> {};
131
132class CleanWindow : public SparcFault<CleanWindow> {};
133
134class DivisionByZero : public SparcFault<DivisionByZero> {};
135
136class InternalProcessorError :
137    public SparcFault<InternalProcessorError> {};
138
139class InstructionInvalidTSBEntry :
140    public SparcFault<InstructionInvalidTSBEntry> {};
141
142class DataInvalidTSBEntry : public SparcFault<DataInvalidTSBEntry> {};
143
144class DataAccessException : public SparcFault<DataAccessException> {};
145
146// class DataAccessMMUMiss : public SparcFault<DataAccessMMUMiss> {};
147
148class DataAccessError : public SparcFault<DataAccessError> {};
149
150class DataAccessProtection : public SparcFault<DataAccessProtection> {};
151
152class MemAddressNotAligned :
153    public SparcFault<MemAddressNotAligned> {};
154
155class LDDFMemAddressNotAligned : public SparcFault<LDDFMemAddressNotAligned> {};
156
157class STDFMemAddressNotAligned : public SparcFault<STDFMemAddressNotAligned> {};
158
159class PrivilegedAction : public SparcFault<PrivilegedAction> {};
160
161class LDQFMemAddressNotAligned : public SparcFault<LDQFMemAddressNotAligned> {};
162
163class STQFMemAddressNotAligned : public SparcFault<STQFMemAddressNotAligned> {};
164
165class InstructionRealTranslationMiss :
166    public SparcFault<InstructionRealTranslationMiss> {};
167
168class DataRealTranslationMiss : public SparcFault<DataRealTranslationMiss> {};
169
170// class AsyncDataError : public SparcFault<AsyncDataError> {};
171
172template <class T>
173class EnumeratedFault : public SparcFault<T>
174{
175  protected:
176    uint32_t _n;
177  public:
178    EnumeratedFault(uint32_t n) : SparcFault<T>(), _n(n) {}
179    TrapType trapType() { return SparcFault<T>::trapType() + _n; }
180};
181
182class InterruptLevelN : public EnumeratedFault<InterruptLevelN>
183{
184  public:
185    InterruptLevelN(uint32_t n) : EnumeratedFault<InterruptLevelN>(n) {;}
186    FaultPriority priority() { return 3200 - _n*100; }
187};
188
189class HstickMatch : public SparcFault<HstickMatch> {};
190
191class TrapLevelZero : public SparcFault<TrapLevelZero> {};
192
193class InterruptVector : public SparcFault<InterruptVector> {};
194
195class PAWatchpoint : public SparcFault<PAWatchpoint> {};
196
197class VAWatchpoint : public SparcFault<VAWatchpoint> {};
198
199class FastInstructionAccessMMUMiss :
200    public SparcFault<FastInstructionAccessMMUMiss>
201{
202  protected:
203    Addr vaddr;
204  public:
205    FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
206    {}
207    FastInstructionAccessMMUMiss() : vaddr(0)
208    {}
209    void invoke(ThreadContext * tc,
210            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
211};
212
213class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
214{
215  protected:
216    Addr vaddr;
217  public:
218    FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
219    {}
220    FastDataAccessMMUMiss() : vaddr(0)
221    {}
222    void invoke(ThreadContext * tc,
223            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
224};
225
226class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};
227
228class InstructionBreakpoint : public SparcFault<InstructionBreakpoint> {};
229
230class CpuMondo : public SparcFault<CpuMondo> {};
231
232class DevMondo : public SparcFault<DevMondo> {};
233
234class ResumableError : public SparcFault<ResumableError> {};
235
236class SpillNNormal : public EnumeratedFault<SpillNNormal>
237{
238  public:
239    SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;}
240    // These need to be handled specially to enable spill traps in SE
241    void invoke(ThreadContext * tc,
242            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
243};
244
245class SpillNOther : public EnumeratedFault<SpillNOther>
246{
247  public:
248    SpillNOther(uint32_t n) : EnumeratedFault<SpillNOther>(n)
249    {}
250};
251
252class FillNNormal : public EnumeratedFault<FillNNormal>
253{
254  public:
255    FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n)
256    {}
257    // These need to be handled specially to enable fill traps in SE
258    void invoke(ThreadContext * tc,
259            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
260};
261
262class FillNOther : public EnumeratedFault<FillNOther>
263{
264  public:
265    FillNOther(uint32_t n) : EnumeratedFault<FillNOther>(n)
266    {}
267};
268
269class TrapInstruction : public EnumeratedFault<TrapInstruction>
270{
271  public:
272    TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n)
273    {}
274    // In SE, trap instructions are requesting services from the OS.
275    void invoke(ThreadContext * tc,
276            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
277};
278
279void enterREDState(ThreadContext *tc);
280
281void doREDFault(ThreadContext *tc, TrapType tt);
282
283void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv);
284
285void getREDVector(MiscReg TT, Addr &PC, Addr &NPC);
286
287void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT);
288
289void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT,
290                   MiscReg TL);
291
292} // namespace SparcISA
293
294#endif // __SPARC_FAULTS_HH__
295