faults.hh revision 7741:340b6f01d69b
11689SN/A/* 22316SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Gabe Black 291689SN/A * Kevin Lim 301061SN/A */ 315596Sgblack@eecs.umich.edu 321061SN/A#ifndef __SPARC_FAULTS_HH__ 331061SN/A#define __SPARC_FAULTS_HH__ 345596Sgblack@eecs.umich.edu 355596Sgblack@eecs.umich.edu#include "config/full_system.hh" 365596Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 375596Sgblack@eecs.umich.edu#include "sim/faults.hh" 385596Sgblack@eecs.umich.edu 394637SN/A// The design of the "name" and "vect" functions is in sim/faults.hh 405596Sgblack@eecs.umich.edu 414637SN/Anamespace SparcISA 424637SN/A{ 434637SN/A 444637SN/Atypedef uint32_t TrapType; 454637SN/Atypedef uint32_t FaultPriority; 465596Sgblack@eecs.umich.edu 475596Sgblack@eecs.umich.educlass ITB; 485596Sgblack@eecs.umich.edu 495596Sgblack@eecs.umich.educlass SparcFaultBase : public FaultBase 505596Sgblack@eecs.umich.edu{ 514637SN/A public: 525596Sgblack@eecs.umich.edu enum PrivilegeLevel 531061SN/A { 542292SN/A U, User = U, 551061SN/A P, Privileged = P, 561061SN/A H, Hyperprivileged = H, 571061SN/A NumLevels, 585596Sgblack@eecs.umich.edu SH = -1, 591464SN/A ShouldntHappen = SH 601061SN/A }; 612292SN/A struct FaultVals 622292SN/A { 632292SN/A const FaultName name; 642292SN/A const TrapType trapType; 652292SN/A const FaultPriority priority; 665596Sgblack@eecs.umich.edu const PrivilegeLevel nextPrivilegeLevel[NumLevels]; 672292SN/A FaultStat count; 681464SN/A }; 691464SN/A#if FULL_SYSTEM 701464SN/A void invoke(ThreadContext * tc, 712292SN/A StaticInstPtr inst = StaticInst::nullStaticInstPtr); 723782SN/A#endif 731464SN/A virtual TrapType trapType() = 0; 741464SN/A virtual FaultPriority priority() = 0; 752292SN/A virtual FaultStat & countStat() = 0; 763782SN/A virtual PrivilegeLevel getNextLevel(PrivilegeLevel current) = 0; 772292SN/A}; 781464SN/A 791061SN/Atemplate<typename T> 801061SN/Aclass SparcFault : public SparcFaultBase 812292SN/A{ 822292SN/A protected: 835596Sgblack@eecs.umich.edu static FaultVals vals; 842292SN/A public: 852348SN/A FaultName name() const { return vals.name; } 862680SN/A TrapType trapType() { return vals.trapType; } 872348SN/A FaultPriority priority() { return vals.priority; } 882680SN/A FaultStat & countStat() { return vals.count; } 892292SN/A 902292SN/A PrivilegeLevel 912292SN/A getNextLevel(PrivilegeLevel current) 922292SN/A { 932292SN/A return vals.nextPrivilegeLevel[current]; 942292SN/A } 952292SN/A}; 962292SN/A 972292SN/Aclass PowerOnReset : public SparcFault<PowerOnReset> 982292SN/A{ 992292SN/A#if FULL_SYSTEM 1002292SN/A void invoke(ThreadContext * tc, 1015596Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 1022292SN/A#endif 1032348SN/A}; 1042680SN/A 1052348SN/Aclass WatchDogReset : public SparcFault<WatchDogReset> {}; 1062680SN/A 1072292SN/Aclass ExternallyInitiatedReset : public SparcFault<ExternallyInitiatedReset> {}; 1082292SN/A 1092292SN/Aclass SoftwareInitiatedReset : public SparcFault<SoftwareInitiatedReset> {}; 1102292SN/A 1112292SN/Aclass REDStateException : public SparcFault<REDStateException> {}; 1122292SN/A 1132292SN/Aclass StoreError : public SparcFault<StoreError> {}; 1142292SN/A 1152292SN/Aclass InstructionAccessException : public SparcFault<InstructionAccessException> {}; 1162292SN/A 1172292SN/A// class InstructionAccessMMUMiss : public SparcFault<InstructionAccessMMUMiss> {}; 1182292SN/A 1195596Sgblack@eecs.umich.educlass InstructionAccessError : public SparcFault<InstructionAccessError> {}; 1202292SN/A 1212790SN/Aclass IllegalInstruction : public SparcFault<IllegalInstruction> {}; 1222292SN/A 1232292SN/Aclass PrivilegedOpcode : public SparcFault<PrivilegedOpcode> {}; 1242292SN/A 1252292SN/A// class UnimplementedLDD : public SparcFault<UnimplementedLDD> {}; 1261858SN/A 1271061SN/A// class UnimplementedSTD : public SparcFault<UnimplementedSTD> {}; 1282132SN/A 1295596Sgblack@eecs.umich.educlass FpDisabled : public SparcFault<FpDisabled> {}; 1301061SN/A 1315596Sgblack@eecs.umich.educlass FpExceptionIEEE754 : public SparcFault<FpExceptionIEEE754> {}; 1322348SN/A 1333521SN/Aclass FpExceptionOther : public SparcFault<FpExceptionOther> {}; 1342292SN/A 1352292SN/Aclass TagOverflow : public SparcFault<TagOverflow> {}; 1362348SN/A 1374172SN/Aclass CleanWindow : public SparcFault<CleanWindow> {}; 1382292SN/A 1392292SN/Aclass DivisionByZero : public SparcFault<DivisionByZero> {}; 1402292SN/A 1412292SN/Aclass InternalProcessorError : 1425596Sgblack@eecs.umich.edu public SparcFault<InternalProcessorError> 1432292SN/A{ 1445596Sgblack@eecs.umich.edu public: 1452292SN/A bool isMachineCheckFault() const { return true; } 1462292SN/A}; 1471061SN/A 1481061SN/Aclass InstructionInvalidTSBEntry : 1491061SN/A public SparcFault<InstructionInvalidTSBEntry> {}; 1501061SN/A 1515596Sgblack@eecs.umich.educlass DataInvalidTSBEntry : public SparcFault<DataInvalidTSBEntry> {}; 1521061SN/A 1532292SN/Aclass DataAccessException : public SparcFault<DataAccessException> {}; 1541061SN/A 1551061SN/A// class DataAccessMMUMiss : public SparcFault<DataAccessMMUMiss> {}; 1561061SN/A 1571061SN/Aclass DataAccessError : public SparcFault<DataAccessError> {}; 1585596Sgblack@eecs.umich.edu 1591061SN/Aclass DataAccessProtection : public SparcFault<DataAccessProtection> {}; 1605596Sgblack@eecs.umich.edu 1615596Sgblack@eecs.umich.educlass MemAddressNotAligned : 1625596Sgblack@eecs.umich.edu public SparcFault<MemAddressNotAligned> 1632316SN/A{ 1641061SN/A public: 1651061SN/A bool isAlignmentFault() const { return true; } 1661061SN/A}; 1671061SN/A 1685596Sgblack@eecs.umich.educlass LDDFMemAddressNotAligned : public SparcFault<LDDFMemAddressNotAligned> {}; 1691061SN/A 1705556SN/Aclass STDFMemAddressNotAligned : public SparcFault<STDFMemAddressNotAligned> {}; 1715556SN/A 1725556SN/Aclass PrivilegedAction : public SparcFault<PrivilegedAction> {}; 1735556SN/A 1742669SN/Aclass LDQFMemAddressNotAligned : public SparcFault<LDQFMemAddressNotAligned> {}; 1755556SN/A 1765556SN/Aclass STQFMemAddressNotAligned : public SparcFault<STQFMemAddressNotAligned> {}; 1775556SN/A 1785556SN/Aclass InstructionRealTranslationMiss : 1791061SN/A public SparcFault<InstructionRealTranslationMiss> {}; 1801061SN/A 1811061SN/Aclass DataRealTranslationMiss : public SparcFault<DataRealTranslationMiss> {}; 182 183// class AsyncDataError : public SparcFault<AsyncDataError> {}; 184 185template <class T> 186class EnumeratedFault : public SparcFault<T> 187{ 188 protected: 189 uint32_t _n; 190 public: 191 EnumeratedFault(uint32_t n) : SparcFault<T>(), _n(n) {} 192 TrapType trapType() { return SparcFault<T>::trapType() + _n; } 193}; 194 195class InterruptLevelN : public EnumeratedFault<InterruptLevelN> 196{ 197 public: 198 InterruptLevelN(uint32_t n) : EnumeratedFault<InterruptLevelN>(n) {;} 199 FaultPriority priority() { return 3200 - _n*100; } 200}; 201 202class HstickMatch : public SparcFault<HstickMatch> {}; 203 204class TrapLevelZero : public SparcFault<TrapLevelZero> {}; 205 206class InterruptVector : public SparcFault<InterruptVector> {}; 207 208class PAWatchpoint : public SparcFault<PAWatchpoint> {}; 209 210class VAWatchpoint : public SparcFault<VAWatchpoint> {}; 211 212class FastInstructionAccessMMUMiss : 213 public SparcFault<FastInstructionAccessMMUMiss> 214{ 215#if !FULL_SYSTEM 216 protected: 217 Addr vaddr; 218 public: 219 FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr) 220 {} 221 void invoke(ThreadContext * tc, 222 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 223#endif 224}; 225 226class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss> 227{ 228#if !FULL_SYSTEM 229 protected: 230 Addr vaddr; 231 public: 232 FastDataAccessMMUMiss(Addr addr) : vaddr(addr) 233 {} 234 void invoke(ThreadContext * tc, 235 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 236#endif 237}; 238 239class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {}; 240 241class InstructionBreakpoint : public SparcFault<InstructionBreakpoint> {}; 242 243class CpuMondo : public SparcFault<CpuMondo> {}; 244 245class DevMondo : public SparcFault<DevMondo> {}; 246 247class ResumableError : public SparcFault<ResumableError> {}; 248 249class SpillNNormal : public EnumeratedFault<SpillNNormal> 250{ 251 public: 252 SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;} 253 // These need to be handled specially to enable spill traps in SE 254#if !FULL_SYSTEM 255 void invoke(ThreadContext * tc, 256 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 257#endif 258}; 259 260class SpillNOther : public EnumeratedFault<SpillNOther> 261{ 262 public: 263 SpillNOther(uint32_t n) : EnumeratedFault<SpillNOther>(n) 264 {} 265}; 266 267class FillNNormal : public EnumeratedFault<FillNNormal> 268{ 269 public: 270 FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n) 271 {} 272 // These need to be handled specially to enable fill traps in SE 273#if !FULL_SYSTEM 274 void invoke(ThreadContext * tc, 275 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 276#endif 277}; 278 279class FillNOther : public EnumeratedFault<FillNOther> 280{ 281 public: 282 FillNOther(uint32_t n) : EnumeratedFault<FillNOther>(n) 283 {} 284}; 285 286class TrapInstruction : public EnumeratedFault<TrapInstruction> 287{ 288 public: 289 TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n) 290 {} 291 // In SE, trap instructions are requesting services from the OS. 292#if !FULL_SYSTEM 293 void invoke(ThreadContext * tc, 294 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 295#endif 296}; 297 298static inline Fault 299genMachineCheckFault() 300{ 301 return new InternalProcessorError; 302} 303 304 305} // SparcISA namespace 306 307#endif // __SPARC_FAULTS_HH__ 308