faults.cc revision 8806 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#include <algorithm>
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/process.hh"
37#include "arch/sparc/types.hh"
38#include "base/bitfield.hh"
39#include "base/trace.hh"
40#include "sim/full_system.hh"
41#include "cpu/base.hh"
42#include "cpu/thread_context.hh"
43#include "mem/page_table.hh"
44#include "sim/process.hh"
45#include "sim/full_system.hh"
46
47using namespace std;
48
49namespace SparcISA
50{
51
52template<> SparcFaultBase::FaultVals
53    SparcFault<PowerOnReset>::vals =
54    {"power_on_reset", 0x001, 0, {H, H, H}};
55
56template<> SparcFaultBase::FaultVals
57    SparcFault<WatchDogReset>::vals =
58    {"watch_dog_reset", 0x002, 120, {H, H, H}};
59
60template<> SparcFaultBase::FaultVals
61    SparcFault<ExternallyInitiatedReset>::vals =
62    {"externally_initiated_reset", 0x003, 110, {H, H, H}};
63
64template<> SparcFaultBase::FaultVals
65    SparcFault<SoftwareInitiatedReset>::vals =
66    {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
67
68template<> SparcFaultBase::FaultVals
69    SparcFault<REDStateException>::vals =
70    {"RED_state_exception", 0x005, 1, {H, H, H}};
71
72template<> SparcFaultBase::FaultVals
73    SparcFault<StoreError>::vals =
74    {"store_error", 0x007, 201, {H, H, H}};
75
76template<> SparcFaultBase::FaultVals
77    SparcFault<InstructionAccessException>::vals =
78    {"instruction_access_exception", 0x008, 300, {H, H, H}};
79
80//XXX This trap is apparently dropped from ua2005
81/*template<> SparcFaultBase::FaultVals
82    SparcFault<InstructionAccessMMUMiss>::vals =
83    {"inst_mmu", 0x009, 2, {H, H, H}};*/
84
85template<> SparcFaultBase::FaultVals
86    SparcFault<InstructionAccessError>::vals =
87    {"instruction_access_error", 0x00A, 400, {H, H, H}};
88
89template<> SparcFaultBase::FaultVals
90    SparcFault<IllegalInstruction>::vals =
91    {"illegal_instruction", 0x010, 620, {H, H, H}};
92
93template<> SparcFaultBase::FaultVals
94    SparcFault<PrivilegedOpcode>::vals =
95    {"privileged_opcode", 0x011, 700, {P, SH, SH}};
96
97//XXX This trap is apparently dropped from ua2005
98/*template<> SparcFaultBase::FaultVals
99    SparcFault<UnimplementedLDD>::vals =
100    {"unimp_ldd", 0x012, 6, {H, H, H}};*/
101
102//XXX This trap is apparently dropped from ua2005
103/*template<> SparcFaultBase::FaultVals
104    SparcFault<UnimplementedSTD>::vals =
105    {"unimp_std", 0x013, 6, {H, H, H}};*/
106
107template<> SparcFaultBase::FaultVals
108    SparcFault<FpDisabled>::vals =
109    {"fp_disabled", 0x020, 800, {P, P, H}};
110
111template<> SparcFaultBase::FaultVals
112    SparcFault<FpExceptionIEEE754>::vals =
113    {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
114
115template<> SparcFaultBase::FaultVals
116    SparcFault<FpExceptionOther>::vals =
117    {"fp_exception_other", 0x022, 1110, {P, P, H}};
118
119template<> SparcFaultBase::FaultVals
120    SparcFault<TagOverflow>::vals =
121    {"tag_overflow", 0x023, 1400, {P, P, H}};
122
123template<> SparcFaultBase::FaultVals
124    SparcFault<CleanWindow>::vals =
125    {"clean_window", 0x024, 1010, {P, P, H}};
126
127template<> SparcFaultBase::FaultVals
128    SparcFault<DivisionByZero>::vals =
129    {"division_by_zero", 0x028, 1500, {P, P, H}};
130
131template<> SparcFaultBase::FaultVals
132    SparcFault<InternalProcessorError>::vals =
133    {"internal_processor_error", 0x029, 4, {H, H, H}};
134
135template<> SparcFaultBase::FaultVals
136    SparcFault<InstructionInvalidTSBEntry>::vals =
137    {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
138
139template<> SparcFaultBase::FaultVals
140    SparcFault<DataInvalidTSBEntry>::vals =
141    {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
142
143template<> SparcFaultBase::FaultVals
144    SparcFault<DataAccessException>::vals =
145    {"data_access_exception", 0x030, 1201, {H, H, H}};
146
147//XXX This trap is apparently dropped from ua2005
148/*template<> SparcFaultBase::FaultVals
149    SparcFault<DataAccessMMUMiss>::vals =
150    {"data_mmu", 0x031, 12, {H, H, H}};*/
151
152template<> SparcFaultBase::FaultVals
153    SparcFault<DataAccessError>::vals =
154    {"data_access_error", 0x032, 1210, {H, H, H}};
155
156template<> SparcFaultBase::FaultVals
157    SparcFault<DataAccessProtection>::vals =
158    {"data_access_protection", 0x033, 1207, {H, H, H}};
159
160template<> SparcFaultBase::FaultVals
161    SparcFault<MemAddressNotAligned>::vals =
162    {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
163
164template<> SparcFaultBase::FaultVals
165    SparcFault<LDDFMemAddressNotAligned>::vals =
166    {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
167
168template<> SparcFaultBase::FaultVals
169    SparcFault<STDFMemAddressNotAligned>::vals =
170    {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
171
172template<> SparcFaultBase::FaultVals
173    SparcFault<PrivilegedAction>::vals =
174    {"privileged_action", 0x037, 1110, {H, H, SH}};
175
176template<> SparcFaultBase::FaultVals
177    SparcFault<LDQFMemAddressNotAligned>::vals =
178    {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
179
180template<> SparcFaultBase::FaultVals
181    SparcFault<STQFMemAddressNotAligned>::vals =
182    {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
183
184template<> SparcFaultBase::FaultVals
185    SparcFault<InstructionRealTranslationMiss>::vals =
186    {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
187
188template<> SparcFaultBase::FaultVals
189    SparcFault<DataRealTranslationMiss>::vals =
190    {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
191
192//XXX This trap is apparently dropped from ua2005
193/*template<> SparcFaultBase::FaultVals
194    SparcFault<AsyncDataError>::vals =
195    {"async_data", 0x040, 2, {H, H, H}};*/
196
197template<> SparcFaultBase::FaultVals
198    SparcFault<InterruptLevelN>::vals =
199    {"interrupt_level_n", 0x040, 0, {P, P, SH}};
200
201template<> SparcFaultBase::FaultVals
202    SparcFault<HstickMatch>::vals =
203    {"hstick_match", 0x05E, 1601, {H, H, H}};
204
205template<> SparcFaultBase::FaultVals
206    SparcFault<TrapLevelZero>::vals =
207    {"trap_level_zero", 0x05F, 202, {H, H, SH}};
208
209template<> SparcFaultBase::FaultVals
210    SparcFault<InterruptVector>::vals =
211    {"interrupt_vector", 0x060, 2630, {H, H, H}};
212
213template<> SparcFaultBase::FaultVals
214    SparcFault<PAWatchpoint>::vals =
215    {"PA_watchpoint", 0x061, 1209, {H, H, H}};
216
217template<> SparcFaultBase::FaultVals
218    SparcFault<VAWatchpoint>::vals =
219    {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
220
221template<> SparcFaultBase::FaultVals
222    SparcFault<FastInstructionAccessMMUMiss>::vals =
223    {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
224
225template<> SparcFaultBase::FaultVals
226    SparcFault<FastDataAccessMMUMiss>::vals =
227    {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
228
229template<> SparcFaultBase::FaultVals
230    SparcFault<FastDataAccessProtection>::vals =
231    {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
232
233template<> SparcFaultBase::FaultVals
234    SparcFault<InstructionBreakpoint>::vals =
235    {"instruction_break", 0x076, 610, {H, H, H}};
236
237template<> SparcFaultBase::FaultVals
238    SparcFault<CpuMondo>::vals =
239    {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
240
241template<> SparcFaultBase::FaultVals
242    SparcFault<DevMondo>::vals =
243    {"dev_mondo", 0x07D, 1611, {P, P, SH}};
244
245template<> SparcFaultBase::FaultVals
246    SparcFault<ResumableError>::vals =
247    {"resume_error", 0x07E, 3330, {P, P, SH}};
248
249template<> SparcFaultBase::FaultVals
250    SparcFault<SpillNNormal>::vals =
251    {"spill_n_normal", 0x080, 900, {P, P, H}};
252
253template<> SparcFaultBase::FaultVals
254    SparcFault<SpillNOther>::vals =
255    {"spill_n_other", 0x0A0, 900, {P, P, H}};
256
257template<> SparcFaultBase::FaultVals
258    SparcFault<FillNNormal>::vals =
259    {"fill_n_normal", 0x0C0, 900, {P, P, H}};
260
261template<> SparcFaultBase::FaultVals
262    SparcFault<FillNOther>::vals =
263    {"fill_n_other", 0x0E0, 900, {P, P, H}};
264
265template<> SparcFaultBase::FaultVals
266    SparcFault<TrapInstruction>::vals =
267    {"trap_instruction", 0x100, 1602, {P, P, H}};
268
269/**
270 * This causes the thread context to enter RED state. This causes the side
271 * effects which go with entering RED state because of a trap.
272 */
273
274void
275enterREDState(ThreadContext *tc)
276{
277    //@todo Disable the mmu?
278    //@todo Disable watchpoints?
279    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
280    // HPSTATE.red = 1
281    HPSTATE |= (1 << 5);
282    // HPSTATE.hpriv = 1
283    HPSTATE |= (1 << 2);
284    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
285    // PSTATE.priv is set to 1 here. The manual says it should be 0, but
286    // Legion sets it to 1.
287    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
288    PSTATE |= (1 << 2);
289    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
290}
291
292/**
293 * This sets everything up for a RED state trap except for actually jumping to
294 * the handler.
295 */
296
297void
298doREDFault(ThreadContext *tc, TrapType tt)
299{
300    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
301    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
302    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
303    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
304    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
305    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
306    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
307    MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
308    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
309    PCState pc = tc->pcState();
310
311    TL++;
312
313    Addr pcMask = bits(PSTATE, 3) ? mask(32) : mask(64);
314
315    // set TSTATE.gl to gl
316    replaceBits(TSTATE, 42, 40, GL);
317    // set TSTATE.ccr to ccr
318    replaceBits(TSTATE, 39, 32, CCR);
319    // set TSTATE.asi to asi
320    replaceBits(TSTATE, 31, 24, ASI);
321    // set TSTATE.pstate to pstate
322    replaceBits(TSTATE, 20, 8, PSTATE);
323    // set TSTATE.cwp to cwp
324    replaceBits(TSTATE, 4, 0, CWP);
325
326    // Write back TSTATE
327    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
328
329    // set TPC to PC
330    tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
331    // set TNPC to NPC
332    tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
333
334    // set HTSTATE.hpstate to hpstate
335    tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
336
337    // TT = trap type;
338    tc->setMiscRegNoEffect(MISCREG_TT, tt);
339
340    // Update GL
341    tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
342
343    PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
344    PSTATE |= (1 << 4); // set PSTATE.pef to 1
345    tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
346
347    // set HPSTATE.red to 1
348    HPSTATE |= (1 << 5);
349    // set HPSTATE.hpriv to 1
350    HPSTATE |= (1 << 2);
351    // set HPSTATE.ibe to 0
352    HPSTATE &= ~(1 << 10);
353    // set HPSTATE.tlz to 0
354    HPSTATE &= ~(1 << 0);
355    tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
356
357    bool changedCWP = true;
358    if (tt == 0x24)
359        CWP++;
360    else if (0x80 <= tt && tt <= 0xbf)
361        CWP += (CANSAVE + 2);
362    else if (0xc0 <= tt && tt <= 0xff)
363        CWP--;
364    else
365        changedCWP = false;
366
367    if (changedCWP) {
368        CWP = (CWP + NWindows) % NWindows;
369        tc->setMiscReg(MISCREG_CWP, CWP);
370    }
371}
372
373/**
374 * This sets everything up for a normal trap except for actually jumping to
375 * the handler.
376 */
377
378void
379doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
380{
381    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
382    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
383    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
384    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
385    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
386    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
387    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
388    MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
389    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
390    PCState pc = tc->pcState();
391
392    // Increment the trap level
393    TL++;
394    tc->setMiscRegNoEffect(MISCREG_TL, TL);
395
396    Addr pcMask = bits(PSTATE, 3) ? mask(32) : mask(64);
397
398    // Save off state
399
400    // set TSTATE.gl to gl
401    replaceBits(TSTATE, 42, 40, GL);
402    // set TSTATE.ccr to ccr
403    replaceBits(TSTATE, 39, 32, CCR);
404    // set TSTATE.asi to asi
405    replaceBits(TSTATE, 31, 24, ASI);
406    // set TSTATE.pstate to pstate
407    replaceBits(TSTATE, 20, 8, PSTATE);
408    // set TSTATE.cwp to cwp
409    replaceBits(TSTATE, 4, 0, CWP);
410
411    // Write back TSTATE
412    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
413
414    // set TPC to PC
415    tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
416    // set TNPC to NPC
417    tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
418
419    // set HTSTATE.hpstate to hpstate
420    tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
421
422    // TT = trap type;
423    tc->setMiscRegNoEffect(MISCREG_TT, tt);
424
425    // Update the global register level
426    if (!gotoHpriv)
427        tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxPGL));
428    else
429        tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL));
430
431    // PSTATE.mm is unchanged
432    PSTATE |= (1 << 4); // PSTATE.pef = whether or not an fpu is present
433    PSTATE &= ~(1 << 3); // PSTATE.am = 0
434    PSTATE &= ~(1 << 1); // PSTATE.ie = 0
435    // PSTATE.tle is unchanged
436    // PSTATE.tct = 0
437
438    if (gotoHpriv) {
439        PSTATE &= ~(1 << 9); // PSTATE.cle = 0
440        // The manual says PSTATE.priv should be 0, but Legion leaves it alone
441        HPSTATE &= ~(1 << 5); // HPSTATE.red = 0
442        HPSTATE |= (1 << 2); // HPSTATE.hpriv = 1
443        HPSTATE &= ~(1 << 10); // HPSTATE.ibe = 0
444        // HPSTATE.tlz is unchanged
445        tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
446    } else { // we are going to priv
447        PSTATE |= (1 << 2); // PSTATE.priv = 1
448        replaceBits(PSTATE, 9, 9, PSTATE >> 8); // PSTATE.cle = PSTATE.tle
449    }
450    tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
451
452
453    bool changedCWP = true;
454    if (tt == 0x24)
455        CWP++;
456    else if (0x80 <= tt && tt <= 0xbf)
457        CWP += (CANSAVE + 2);
458    else if (0xc0 <= tt && tt <= 0xff)
459        CWP--;
460    else
461        changedCWP = false;
462
463    if (changedCWP) {
464        CWP = (CWP + NWindows) % NWindows;
465        tc->setMiscReg(MISCREG_CWP, CWP);
466    }
467}
468
469void
470getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
471{
472    //XXX The following constant might belong in a header file.
473    const Addr RSTVAddr = 0xFFF0000000ULL;
474    PC = RSTVAddr | ((TT << 5) & 0xFF);
475    NPC = PC + sizeof(MachInst);
476}
477
478void
479getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT)
480{
481    Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
482    PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
483    NPC = PC + sizeof(MachInst);
484}
485
486void
487getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
488{
489    Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
490    PC = (TBA & ~mask(15)) |
491        (TL > 1 ? (1 << 14) : 0) |
492        ((TT << 5) & mask(14));
493    NPC = PC + sizeof(MachInst);
494}
495
496void
497SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
498{
499    FaultBase::invoke(tc);
500    if (!FullSystem)
501        return;
502
503    countStat()++;
504
505    // We can refer to this to see what the trap level -was-, but something
506    // in the middle could change it in the regfile out from under us.
507    MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
508    MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
509    MiscReg pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
510    MiscReg hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
511
512    Addr PC, NPC;
513
514    PrivilegeLevel current;
515    if (hpstate & HPSTATE::hpriv)
516        current = Hyperprivileged;
517    else if (pstate & PSTATE::priv)
518        current = Privileged;
519    else
520        current = User;
521
522    PrivilegeLevel level = getNextLevel(current);
523
524    if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) {
525        getREDVector(5, PC, NPC);
526        doREDFault(tc, tt);
527        // This changes the hpstate and pstate, so we need to make sure we
528        // save the old version on the trap stack in doREDFault.
529        enterREDState(tc);
530    } else if (tl == MaxTL) {
531        panic("Should go to error state here.. crap\n");
532        // Do error_state somehow?
533        // Probably inject a WDR fault using the interrupt mechanism.
534        // What should the PC and NPC be set to?
535    } else if (tl > MaxPTL && level == Privileged) {
536        // guest_watchdog fault
537        doNormalFault(tc, trapType(), true);
538        getHyperVector(tc, PC, NPC, 2);
539    } else if (level == Hyperprivileged ||
540               (level == Privileged && trapType() >= 384)) {
541        doNormalFault(tc, trapType(), true);
542        getHyperVector(tc, PC, NPC, trapType());
543    } else {
544        doNormalFault(tc, trapType(), false);
545        getPrivVector(tc, PC, NPC, trapType(), tl + 1);
546    }
547
548    PCState pc;
549    pc.pc(PC);
550    pc.npc(NPC);
551    pc.nnpc(NPC + sizeof(MachInst));
552    pc.upc(0);
553    pc.nupc(1);
554    tc->pcState(pc);
555}
556
557void
558PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
559{
560    // For SPARC, when a system is first started, there is a power
561    // on reset Trap which sets the processor into the following state.
562    // Bits that aren't set aren't defined on startup.
563
564    tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
565    tc->setMiscRegNoEffect(MISCREG_TT, trapType());
566    tc->setMiscReg(MISCREG_GL, MaxGL);
567
568    // Turn on pef and priv, set everything else to 0
569    tc->setMiscRegNoEffect(MISCREG_PSTATE, (1 << 4) | (1 << 2));
570
571    // Turn on red and hpriv, set everything else to 0
572    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
573    // HPSTATE.red = 1
574    HPSTATE |= (1 << 5);
575    // HPSTATE.hpriv = 1
576    HPSTATE |= (1 << 2);
577    // HPSTATE.ibe = 0
578    HPSTATE &= ~(1 << 10);
579    // HPSTATE.tlz = 0
580    HPSTATE &= ~(1 << 0);
581    tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
582
583    // The tick register is unreadable by nonprivileged software
584    tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
585
586    // Enter RED state. We do this last so that the actual state preserved in
587    // the trap stack is the state from before this fault.
588    enterREDState(tc);
589
590    Addr PC, NPC;
591    getREDVector(trapType(), PC, NPC);
592
593    PCState pc;
594    pc.pc(PC);
595    pc.npc(NPC);
596    pc.nnpc(NPC + sizeof(MachInst));
597    pc.upc(0);
598    pc.nupc(1);
599    tc->pcState(pc);
600
601    // These registers are specified as "undefined" after a POR, and they
602    // should have reasonable values after the miscregfile is reset
603    /*
604    // Clear all the soft interrupt bits
605    softint = 0;
606    // disable timer compare interrupts, reset tick_cmpr
607    tc->setMiscRegNoEffect(MISCREG_
608    tick_cmprFields.int_dis = 1;
609    tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
610    stickFields.npt = 1; // The TICK register is unreadable by by !priv
611    stick_cmprFields.int_dis = 1; // disable timer compare interrupts
612    stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
613
614    tt[tl] = _trapType;
615
616    hintp = 0; // no interrupts pending
617    hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
618    hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
619    */
620}
621
622void
623FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
624{
625    if (FullSystem) {
626        SparcFaultBase::invoke(tc, inst);
627        return;
628    }
629
630    Process *p = tc->getProcessPtr();
631    TlbEntry entry;
632    bool success = p->pTable->lookup(vaddr, entry);
633    if (!success) {
634        panic("Tried to execute unmapped address %#x.\n", vaddr);
635    } else {
636        Addr alignedVaddr = p->pTable->pageAlign(vaddr);
637        tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
638                p->M5_pid /*context id*/, false, entry.pte);
639    }
640}
641
642void
643FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
644{
645    if (FullSystem) {
646        SparcFaultBase::invoke(tc, inst);
647        return;
648    }
649
650    Process *p = tc->getProcessPtr();
651    TlbEntry entry;
652    bool success = p->pTable->lookup(vaddr, entry);
653    if (!success) {
654        if (p->fixupStackFault(vaddr))
655            success = p->pTable->lookup(vaddr, entry);
656    }
657    if (!success) {
658        panic("Tried to access unmapped address %#x.\n", vaddr);
659    } else {
660        Addr alignedVaddr = p->pTable->pageAlign(vaddr);
661        tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
662                p->M5_pid /*context id*/, false, entry.pte);
663    }
664}
665
666void
667SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
668{
669    if (FullSystem) {
670        SparcFaultBase::invoke(tc, inst);
671        return;
672    }
673
674    doNormalFault(tc, trapType(), false);
675
676    Process *p = tc->getProcessPtr();
677
678    //XXX This will only work in faults from a SparcLiveProcess
679    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
680    assert(lp);
681
682    // Then adjust the PC and NPC
683    tc->pcState(lp->readSpillStart());
684}
685
686void
687FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
688{
689    if (FullSystem) {
690        SparcFaultBase::invoke(tc, inst);
691        return;
692    }
693
694    doNormalFault(tc, trapType(), false);
695
696    Process *p = tc->getProcessPtr();
697
698    //XXX This will only work in faults from a SparcLiveProcess
699    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
700    assert(lp);
701
702    // Then adjust the PC and NPC
703    tc->pcState(lp->readFillStart());
704}
705
706void
707TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
708{
709    if (FullSystem) {
710        SparcFaultBase::invoke(tc, inst);
711        return;
712    }
713
714    // In SE, this mechanism is how the process requests a service from
715    // the operating system. We'll get the process object from the thread
716    // context and let it service the request.
717
718    Process *p = tc->getProcessPtr();
719
720    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
721    assert(lp);
722
723    lp->handleTrap(_n, tc);
724
725    // We need to explicitly advance the pc, since that's not done for us
726    // on a faulting instruction
727    PCState pc = tc->pcState();
728    pc.advance();
729    tc->pcState(pc);
730}
731
732} // namespace SparcISA
733
734