faults.cc revision 3890:5530906ab80a 
111723Sar4jc@virginia.edu/*
211723Sar4jc@virginia.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan
311723Sar4jc@virginia.edu * All rights reserved.
411723Sar4jc@virginia.edu *
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611723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are
711723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright
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911723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright
1011723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the
1111723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution;
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1411723Sar4jc@virginia.edu * this software without specific prior written permission.
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1611723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1711723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1811723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1911723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2011723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2111723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2211723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2311723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2411723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2511723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2611723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2711723Sar4jc@virginia.edu *
2811723Sar4jc@virginia.edu * Authors: Gabe Black
2911723Sar4jc@virginia.edu *          Kevin Lim
3011723Sar4jc@virginia.edu */
3111723Sar4jc@virginia.edu
3211723Sar4jc@virginia.edu#include <algorithm>
3311723Sar4jc@virginia.edu
3411723Sar4jc@virginia.edu#include "arch/sparc/faults.hh"
3511723Sar4jc@virginia.edu#include "arch/sparc/isa_traits.hh"
3611723Sar4jc@virginia.edu#include "arch/sparc/types.hh"
3711723Sar4jc@virginia.edu#include "base/bitfield.hh"
3811723Sar4jc@virginia.edu#include "base/trace.hh"
3911723Sar4jc@virginia.edu#include "config/full_system.hh"
4011723Sar4jc@virginia.edu#include "cpu/base.hh"
4111723Sar4jc@virginia.edu#include "cpu/thread_context.hh"
4211723Sar4jc@virginia.edu#if !FULL_SYSTEM
4311723Sar4jc@virginia.edu#include "arch/sparc/process.hh"
4411723Sar4jc@virginia.edu#include "mem/page_table.hh"
4511723Sar4jc@virginia.edu#include "sim/process.hh"
4611723Sar4jc@virginia.edu#endif
4711723Sar4jc@virginia.edu
4811723Sar4jc@virginia.eduusing namespace std;
4911723Sar4jc@virginia.edu
5011723Sar4jc@virginia.edunamespace SparcISA
5111723Sar4jc@virginia.edu{
5211723Sar4jc@virginia.edu
5311723Sar4jc@virginia.edutemplate<> SparcFaultBase::FaultVals
5411723Sar4jc@virginia.edu    SparcFault<PowerOnReset>::vals =
5511723Sar4jc@virginia.edu    {"power_on_reset", 0x001, 0, {H, H, H}};
5611723Sar4jc@virginia.edu
5711723Sar4jc@virginia.edutemplate<> SparcFaultBase::FaultVals
5811723Sar4jc@virginia.edu    SparcFault<WatchDogReset>::vals =
5911723Sar4jc@virginia.edu    {"watch_dog_reset", 0x002, 120, {H, H, H}};
6011723Sar4jc@virginia.edu
6111723Sar4jc@virginia.edutemplate<> SparcFaultBase::FaultVals
6211723Sar4jc@virginia.edu    SparcFault<ExternallyInitiatedReset>::vals =
6311723Sar4jc@virginia.edu    {"externally_initiated_reset", 0x003, 110, {H, H, H}};
6411723Sar4jc@virginia.edu
6511723Sar4jc@virginia.edutemplate<> SparcFaultBase::FaultVals
6611723Sar4jc@virginia.edu    SparcFault<SoftwareInitiatedReset>::vals =
6711723Sar4jc@virginia.edu    {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
6811723Sar4jc@virginia.edu
6911723Sar4jc@virginia.edutemplate<> SparcFaultBase::FaultVals
7011723Sar4jc@virginia.edu    SparcFault<REDStateException>::vals =
7111723Sar4jc@virginia.edu    {"RED_state_exception", 0x005, 1, {H, H, H}};
72
73template<> SparcFaultBase::FaultVals
74    SparcFault<StoreError>::vals =
75    {"store_error", 0x007, 201, {H, H, H}};
76
77template<> SparcFaultBase::FaultVals
78    SparcFault<InstructionAccessException>::vals =
79    {"instruction_access_exception", 0x008, 300, {H, H, H}};
80
81//XXX This trap is apparently dropped from ua2005
82/*template<> SparcFaultBase::FaultVals
83    SparcFault<InstructionAccessMMUMiss>::vals =
84    {"inst_mmu", 0x009, 2, {H, H, H}};*/
85
86template<> SparcFaultBase::FaultVals
87    SparcFault<InstructionAccessError>::vals =
88    {"instruction_access_error", 0x00A, 400, {H, H, H}};
89
90template<> SparcFaultBase::FaultVals
91    SparcFault<IllegalInstruction>::vals =
92    {"illegal_instruction", 0x010, 620, {H, H, H}};
93
94template<> SparcFaultBase::FaultVals
95    SparcFault<PrivilegedOpcode>::vals =
96    {"privileged_opcode", 0x011, 700, {P, SH, SH}};
97
98//XXX This trap is apparently dropped from ua2005
99/*template<> SparcFaultBase::FaultVals
100    SparcFault<UnimplementedLDD>::vals =
101    {"unimp_ldd", 0x012, 6, {H, H, H}};*/
102
103//XXX This trap is apparently dropped from ua2005
104/*template<> SparcFaultBase::FaultVals
105    SparcFault<UnimplementedSTD>::vals =
106    {"unimp_std", 0x013, 6, {H, H, H}};*/
107
108template<> SparcFaultBase::FaultVals
109    SparcFault<FpDisabled>::vals =
110    {"fp_disabled", 0x020, 800, {P, P, H}};
111
112template<> SparcFaultBase::FaultVals
113    SparcFault<FpExceptionIEEE754>::vals =
114    {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
115
116template<> SparcFaultBase::FaultVals
117    SparcFault<FpExceptionOther>::vals =
118    {"fp_exception_other", 0x022, 1110, {P, P, H}};
119
120template<> SparcFaultBase::FaultVals
121    SparcFault<TagOverflow>::vals =
122    {"tag_overflow", 0x023, 1400, {P, P, H}};
123
124template<> SparcFaultBase::FaultVals
125    SparcFault<CleanWindow>::vals =
126    {"clean_window", 0x024, 1010, {P, P, H}};
127
128template<> SparcFaultBase::FaultVals
129    SparcFault<DivisionByZero>::vals =
130    {"division_by_zero", 0x028, 1500, {P, P, H}};
131
132template<> SparcFaultBase::FaultVals
133    SparcFault<InternalProcessorError>::vals =
134    {"internal_processor_error", 0x029, 4, {H, H, H}};
135
136template<> SparcFaultBase::FaultVals
137    SparcFault<InstructionInvalidTSBEntry>::vals =
138    {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
139
140template<> SparcFaultBase::FaultVals
141    SparcFault<DataInvalidTSBEntry>::vals =
142    {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
143
144template<> SparcFaultBase::FaultVals
145    SparcFault<DataAccessException>::vals =
146    {"data_access_exception", 0x030, 1201, {H, H, H}};
147
148//XXX This trap is apparently dropped from ua2005
149/*template<> SparcFaultBase::FaultVals
150    SparcFault<DataAccessMMUMiss>::vals =
151    {"data_mmu", 0x031, 12, {H, H, H}};*/
152
153template<> SparcFaultBase::FaultVals
154    SparcFault<DataAccessError>::vals =
155    {"data_access_error", 0x032, 1210, {H, H, H}};
156
157template<> SparcFaultBase::FaultVals
158    SparcFault<DataAccessProtection>::vals =
159    {"data_access_protection", 0x033, 1207, {H, H, H}};
160
161template<> SparcFaultBase::FaultVals
162    SparcFault<MemAddressNotAligned>::vals =
163    {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
164
165template<> SparcFaultBase::FaultVals
166    SparcFault<LDDFMemAddressNotAligned>::vals =
167    {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
168
169template<> SparcFaultBase::FaultVals
170    SparcFault<STDFMemAddressNotAligned>::vals =
171    {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
172
173template<> SparcFaultBase::FaultVals
174    SparcFault<PrivilegedAction>::vals =
175    {"privileged_action", 0x037, 1110, {H, H, SH}};
176
177template<> SparcFaultBase::FaultVals
178    SparcFault<LDQFMemAddressNotAligned>::vals =
179    {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
180
181template<> SparcFaultBase::FaultVals
182    SparcFault<STQFMemAddressNotAligned>::vals =
183    {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
184
185template<> SparcFaultBase::FaultVals
186    SparcFault<InstructionRealTranslationMiss>::vals =
187    {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
188
189template<> SparcFaultBase::FaultVals
190    SparcFault<DataRealTranslationMiss>::vals =
191    {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
192
193//XXX This trap is apparently dropped from ua2005
194/*template<> SparcFaultBase::FaultVals
195    SparcFault<AsyncDataError>::vals =
196    {"async_data", 0x040, 2, {H, H, H}};*/
197
198template<> SparcFaultBase::FaultVals
199    SparcFault<InterruptLevelN>::vals =
200    {"interrupt_level_n", 0x040, 0, {P, P, SH}};
201
202template<> SparcFaultBase::FaultVals
203    SparcFault<HstickMatch>::vals =
204    {"hstick_match", 0x05E, 1601, {H, H, H}};
205
206template<> SparcFaultBase::FaultVals
207    SparcFault<TrapLevelZero>::vals =
208    {"trap_level_zero", 0x05F, 202, {H, H, SH}};
209
210template<> SparcFaultBase::FaultVals
211    SparcFault<PAWatchpoint>::vals =
212    {"PA_watchpoint", 0x061, 1209, {H, H, H}};
213
214template<> SparcFaultBase::FaultVals
215    SparcFault<VAWatchpoint>::vals =
216    {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
217
218template<> SparcFaultBase::FaultVals
219    SparcFault<FastInstructionAccessMMUMiss>::vals =
220    {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
221
222template<> SparcFaultBase::FaultVals
223    SparcFault<FastDataAccessMMUMiss>::vals =
224    {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
225
226template<> SparcFaultBase::FaultVals
227    SparcFault<FastDataAccessProtection>::vals =
228    {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
229
230template<> SparcFaultBase::FaultVals
231    SparcFault<InstructionBreakpoint>::vals =
232    {"instruction_break", 0x076, 610, {H, H, H}};
233
234template<> SparcFaultBase::FaultVals
235    SparcFault<CpuMondo>::vals =
236    {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
237
238template<> SparcFaultBase::FaultVals
239    SparcFault<DevMondo>::vals =
240    {"dev_mondo", 0x07D, 1611, {P, P, SH}};
241
242template<> SparcFaultBase::FaultVals
243    SparcFault<ResumeableError>::vals =
244    {"resume_error", 0x07E, 3330, {P, P, SH}};
245
246template<> SparcFaultBase::FaultVals
247    SparcFault<SpillNNormal>::vals =
248    {"spill_n_normal", 0x080, 900, {P, P, H}};
249
250template<> SparcFaultBase::FaultVals
251    SparcFault<SpillNOther>::vals =
252    {"spill_n_other", 0x0A0, 900, {P, P, H}};
253
254template<> SparcFaultBase::FaultVals
255    SparcFault<FillNNormal>::vals =
256    {"fill_n_normal", 0x0C0, 900, {P, P, H}};
257
258template<> SparcFaultBase::FaultVals
259    SparcFault<FillNOther>::vals =
260    {"fill_n_other", 0x0E0, 900, {P, P, H}};
261
262template<> SparcFaultBase::FaultVals
263    SparcFault<TrapInstruction>::vals =
264    {"trap_instruction", 0x100, 1602, {P, P, H}};
265
266#if !FULL_SYSTEM
267template<> SparcFaultBase::FaultVals
268    SparcFault<PageTableFault>::vals =
269    {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
270#endif
271
272/**
273 * This causes the thread context to enter RED state. This causes the side
274 * effects which go with entering RED state because of a trap.
275 */
276
277void enterREDState(ThreadContext *tc)
278{
279    //@todo Disable the mmu?
280    //@todo Disable watchpoints?
281    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
282    //HPSTATE.red = 1
283    HPSTATE |= (1 << 5);
284    //HPSTATE.hpriv = 1
285    HPSTATE |= (1 << 2);
286    tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
287    //PSTATE.priv is set to 1 here. The manual says it should be 0, but
288    //Legion sets it to 1.
289    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
290    PSTATE |= (1 << 2);
291    tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE);
292}
293
294/**
295 * This sets everything up for a RED state trap except for actually jumping to
296 * the handler.
297 */
298
299void doREDFault(ThreadContext *tc, TrapType tt)
300{
301    MiscReg TL = tc->readMiscReg(MISCREG_TL);
302    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
303    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
304    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
305    MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
306    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
307    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
308    MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
309    MiscReg GL = tc->readMiscReg(MISCREG_GL);
310    MiscReg PC = tc->readPC();
311    MiscReg NPC = tc->readNextPC();
312
313    TL++;
314
315    //set TSTATE.gl to gl
316    replaceBits(TSTATE, 42, 40, GL);
317    //set TSTATE.ccr to ccr
318    replaceBits(TSTATE, 39, 32, CCR);
319    //set TSTATE.asi to asi
320    replaceBits(TSTATE, 31, 24, ASI);
321    //set TSTATE.pstate to pstate
322    replaceBits(TSTATE, 20, 8, PSTATE);
323    //set TSTATE.cwp to cwp
324    replaceBits(TSTATE, 4, 0, CWP);
325
326    //Write back TSTATE
327    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
328
329    //set TPC to PC
330    tc->setMiscReg(MISCREG_TPC, PC);
331    //set TNPC to NPC
332    tc->setMiscReg(MISCREG_TNPC, NPC);
333
334    //set HTSTATE.hpstate to hpstate
335    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
336
337    //TT = trap type;
338    tc->setMiscReg(MISCREG_TT, tt);
339
340    //Update GL
341    tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
342
343    //set PSTATE.mm to 00
344    //set PSTATE.pef to 1
345    PSTATE |= (1 << 4);
346    //set PSTATE.am to 0
347    PSTATE &= ~(1 << 3);
348/*    //set PSTATE.priv to 0
349    PSTATE &= ~(1 << 2);*/
350    //set PSTATE.ie to 0
351    //PSTATE.priv is set to 1 here. The manual says it should be 0, but
352    //Legion sets it to 1.
353    PSTATE |= (1 << 2);
354    //set PSTATE.cle to 0
355    PSTATE &= ~(1 << 9);
356    //PSTATE.tle is unchanged
357    //XXX Where is the tct bit?
358    //set PSTATE.tct to 0
359    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
360
361    //set HPSTATE.red to 1
362    HPSTATE |= (1 << 5);
363    //set HPSTATE.hpriv to 1
364    HPSTATE |= (1 << 2);
365    //set HPSTATE.ibe to 0
366    HPSTATE &= ~(1 << 10);
367    //set HPSTATE.tlz to 0
368    HPSTATE &= ~(1 << 0);
369    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
370
371    bool changedCWP = true;
372    if(tt == 0x24)
373        CWP++;
374    else if(0x80 <= tt && tt <= 0xbf)
375        CWP += (CANSAVE + 2);
376    else if(0xc0 <= tt && tt <= 0xff)
377        CWP--;
378    else
379        changedCWP = false;
380
381    if(changedCWP)
382    {
383        CWP = (CWP + NWindows) % NWindows;
384        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
385    }
386}
387
388/**
389 * This sets everything up for a normal trap except for actually jumping to
390 * the handler.
391 */
392
393void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
394{
395    MiscReg TL = tc->readMiscReg(MISCREG_TL);
396    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
397    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
398    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
399    MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
400    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
401    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
402    MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
403    MiscReg GL = tc->readMiscReg(MISCREG_GL);
404    MiscReg PC = tc->readPC();
405    MiscReg NPC = tc->readNextPC();
406
407    //Increment the trap level
408    TL++;
409    tc->setMiscReg(MISCREG_TL, TL);
410
411    //Save off state
412
413    //set TSTATE.gl to gl
414    replaceBits(TSTATE, 42, 40, GL);
415    //set TSTATE.ccr to ccr
416    replaceBits(TSTATE, 39, 32, CCR);
417    //set TSTATE.asi to asi
418    replaceBits(TSTATE, 31, 24, ASI);
419    //set TSTATE.pstate to pstate
420    replaceBits(TSTATE, 20, 8, PSTATE);
421    //set TSTATE.cwp to cwp
422    replaceBits(TSTATE, 4, 0, CWP);
423
424    //Write back TSTATE
425    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
426
427    //set TPC to PC
428    tc->setMiscReg(MISCREG_TPC, PC);
429    //set TNPC to NPC
430    tc->setMiscReg(MISCREG_TNPC, NPC);
431
432    //set HTSTATE.hpstate to hpstate
433    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
434
435    //TT = trap type;
436    tc->setMiscReg(MISCREG_TT, tt);
437
438    //Update the global register level
439    if(!gotoHpriv)
440        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
441    else
442        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
443
444    //PSTATE.mm is unchanged
445    //PSTATE.pef = whether or not an fpu is present
446    //XXX We'll say there's one present, even though there aren't
447    //implementations for a decent number of the instructions
448    PSTATE |= (1 << 4);
449    //PSTATE.am = 0
450    PSTATE &= ~(1 << 3);
451    if(!gotoHpriv)
452    {
453        //PSTATE.priv = 1
454        PSTATE |= (1 << 2);
455        //PSTATE.cle = PSTATE.tle
456        replaceBits(PSTATE, 9, 9, PSTATE >> 8);
457    }
458    else
459    {
460        //PSTATE.priv = 0
461        //PSTATE.priv is set to 1 here. The manual says it should be 0, but
462        //Legion sets it to 1.
463        PSTATE |= (1 << 2);
464        //PSTATE.cle = 0
465        PSTATE &= ~(1 << 9);
466    }
467    //PSTATE.ie = 0
468    PSTATE &= ~(1 << 1);
469    //PSTATE.tle is unchanged
470    //PSTATE.tct = 0
471    //XXX Where exactly is this field?
472    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
473
474    if(gotoHpriv)
475    {
476        //HPSTATE.red = 0
477        HPSTATE &= ~(1 << 5);
478        //HPSTATE.hpriv = 1
479        HPSTATE |= (1 << 2);
480        //HPSTATE.ibe = 0
481        HPSTATE &= ~(1 << 10);
482        //HPSTATE.tlz is unchanged
483        tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
484    }
485
486    bool changedCWP = true;
487    if(tt == 0x24)
488        CWP++;
489    else if(0x80 <= tt && tt <= 0xbf)
490        CWP += (CANSAVE + 2);
491    else if(0xc0 <= tt && tt <= 0xff)
492        CWP--;
493    else
494        changedCWP = false;
495
496    if(changedCWP)
497    {
498        CWP = (CWP + NWindows) % NWindows;
499        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
500    }
501}
502
503void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
504{
505    //XXX The following constant might belong in a header file.
506    const Addr RSTVAddr = 0xFFF0000000ULL;
507    PC = RSTVAddr | ((TT << 5) & 0xFF);
508    NPC = PC + sizeof(MachInst);
509}
510
511void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
512{
513    Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
514    PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
515    NPC = PC + sizeof(MachInst);
516}
517
518void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
519{
520    Addr TBA = tc->readMiscReg(MISCREG_TBA);
521    PC = (TBA & ~mask(15)) |
522        (TL > 1 ? (1 << 14) : 0) |
523        ((TT << 5) & mask(14));
524    NPC = PC + sizeof(MachInst);
525}
526
527#if FULL_SYSTEM
528
529void SparcFaultBase::invoke(ThreadContext * tc)
530{
531    //panic("Invoking a second fault!\n");
532    FaultBase::invoke(tc);
533    countStat()++;
534
535    //We can refer to this to see what the trap level -was-, but something
536    //in the middle could change it in the regfile out from under us.
537    MiscReg TL = tc->readMiscReg(MISCREG_TL);
538    MiscReg TT = tc->readMiscReg(MISCREG_TT);
539    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
540    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
541
542    Addr PC, NPC;
543
544    PrivilegeLevel current;
545    if(HPSTATE & (1 << 2))
546        current = Hyperprivileged;
547    else if(PSTATE & (1 << 2))
548        current = Privileged;
549    else
550        current = User;
551
552    PrivilegeLevel level = getNextLevel(current);
553
554    if(HPSTATE & (1 << 5) || TL == MaxTL - 1) {
555        getREDVector(5, PC, NPC);
556        doREDFault(tc, TT);
557        //This changes the hpstate and pstate, so we need to make sure we
558        //save the old version on the trap stack in doREDFault.
559        enterREDState(tc);
560    } else if(TL == MaxTL) {
561        panic("Should go to error state here.. crap\n");
562        //Do error_state somehow?
563        //Probably inject a WDR fault using the interrupt mechanism.
564        //What should the PC and NPC be set to?
565    } else if(TL > MaxPTL && level == Privileged) {
566        //guest_watchdog fault
567        doNormalFault(tc, trapType(), true);
568        getHyperVector(tc, PC, NPC, 2);
569    } else if(level == Hyperprivileged ||
570            level == Privileged && trapType() >= 384) {
571        doNormalFault(tc, trapType(), true);
572        getHyperVector(tc, PC, NPC, trapType());
573    } else {
574        doNormalFault(tc, trapType(), false);
575        getPrivVector(tc, PC, NPC, trapType(), TL+1);
576    }
577
578    tc->setPC(PC);
579    tc->setNextPC(NPC);
580    tc->setNextNPC(NPC + sizeof(MachInst));
581}
582
583void PowerOnReset::invoke(ThreadContext * tc)
584{
585    //For SPARC, when a system is first started, there is a power
586    //on reset Trap which sets the processor into the following state.
587    //Bits that aren't set aren't defined on startup.
588
589    tc->setMiscReg(MISCREG_TL, MaxTL);
590    tc->setMiscReg(MISCREG_TT, trapType());
591    tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
592
593    //Turn on pef and priv, set everything else to 0
594    tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2));
595
596    //Turn on red and hpriv, set everything else to 0
597    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
598    //HPSTATE.red = 1
599    HPSTATE |= (1 << 5);
600    //HPSTATE.hpriv = 1
601    HPSTATE |= (1 << 2);
602    //HPSTATE.ibe = 0
603    HPSTATE &= ~(1 << 10);
604    //HPSTATE.tlz = 0
605    HPSTATE &= ~(1 << 0);
606    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
607
608    //The tick register is unreadable by nonprivileged software
609    tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
610
611    //Enter RED state. We do this last so that the actual state preserved in
612    //the trap stack is the state from before this fault.
613    enterREDState(tc);
614
615    Addr PC, NPC;
616    getREDVector(trapType(), PC, NPC);
617    tc->setPC(PC);
618    tc->setNextPC(NPC);
619    tc->setNextNPC(NPC + sizeof(MachInst));
620
621    //These registers are specified as "undefined" after a POR, and they
622    //should have reasonable values after the miscregfile is reset
623    /*
624    // Clear all the soft interrupt bits
625    softint = 0;
626    // disable timer compare interrupts, reset tick_cmpr
627    tc->setMiscReg(MISCREG_
628    tick_cmprFields.int_dis = 1;
629    tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
630    stickFields.npt = 1; //The TICK register is unreadable by by !priv
631    stick_cmprFields.int_dis = 1; // disable timer compare interrupts
632    stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
633
634    tt[tl] = _trapType;
635
636    hintp = 0; // no interrupts pending
637    hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
638    hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
639    */
640}
641
642#else // !FULL_SYSTEM
643
644void SpillNNormal::invoke(ThreadContext *tc)
645{
646    doNormalFault(tc, trapType(), false);
647
648    Process *p = tc->getProcessPtr();
649
650    //XXX This will only work in faults from a SparcLiveProcess
651    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
652    assert(lp);
653
654    //Then adjust the PC and NPC
655    Addr spillStart = lp->readSpillStart();
656    tc->setPC(spillStart);
657    tc->setNextPC(spillStart + sizeof(MachInst));
658    tc->setNextNPC(spillStart + 2*sizeof(MachInst));
659}
660
661void FillNNormal::invoke(ThreadContext *tc)
662{
663    doNormalFault(tc, trapType(), false);
664
665    Process * p = tc->getProcessPtr();
666
667    //XXX This will only work in faults from a SparcLiveProcess
668    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
669    assert(lp);
670
671    //Then adjust the PC and NPC
672    Addr fillStart = lp->readFillStart();
673    tc->setPC(fillStart);
674    tc->setNextPC(fillStart + sizeof(MachInst));
675    tc->setNextNPC(fillStart + 2*sizeof(MachInst));
676}
677
678void PageTableFault::invoke(ThreadContext *tc)
679{
680    Process *p = tc->getProcessPtr();
681
682    // address is higher than the stack region or in the current stack region
683    if (vaddr > p->stack_base || vaddr > p->stack_min)
684        FaultBase::invoke(tc);
685
686    // We've accessed the next page
687    if (vaddr > p->stack_min - PageBytes) {
688        p->stack_min -= PageBytes;
689        if (p->stack_base - p->stack_min > 8*1024*1024)
690            fatal("Over max stack size for one thread\n");
691        p->pTable->allocate(p->stack_min, PageBytes);
692        warn("Increasing stack size by one page.");
693    } else {
694        FaultBase::invoke(tc);
695    }
696}
697
698#endif
699
700} // namespace SparcISA
701
702