faults.cc revision 3746:c55a63fb4cf3
112837Sgabeblack@google.com/* 212837Sgabeblack@google.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 312837Sgabeblack@google.com * All rights reserved. 412837Sgabeblack@google.com * 512837Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 612837Sgabeblack@google.com * modification, are permitted provided that the following conditions are 712837Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 812837Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 912837Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1012837Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1112837Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1212837Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1312837Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1412837Sgabeblack@google.com * this software without specific prior written permission. 1512837Sgabeblack@google.com * 1612837Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712837Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812837Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912837Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012837Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112837Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212837Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312837Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412837Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512837Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612837Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712837Sgabeblack@google.com * 2812837Sgabeblack@google.com * Authors: Gabe Black 2912837Sgabeblack@google.com * Kevin Lim 3012837Sgabeblack@google.com */ 3112982Sgabeblack@google.com 3212982Sgabeblack@google.com#include <algorithm> 3313059Sgabeblack@google.com 3412982Sgabeblack@google.com#include "arch/sparc/faults.hh" 3513207Sgabeblack@google.com#include "arch/sparc/isa_traits.hh" 3613403Sgabeblack@google.com#include "arch/sparc/types.hh" 3712953Sgabeblack@google.com#include "base/bitfield.hh" 3812837Sgabeblack@google.com#include "base/trace.hh" 3912982Sgabeblack@google.com#include "config/full_system.hh" 4012837Sgabeblack@google.com#include "cpu/base.hh" 4112837Sgabeblack@google.com#include "cpu/thread_context.hh" 4212990Sgabeblack@google.com#if !FULL_SYSTEM 4312990Sgabeblack@google.com#include "arch/sparc/process.hh" 4412990Sgabeblack@google.com#include "mem/page_table.hh" 4512990Sgabeblack@google.com#include "sim/process.hh" 4612990Sgabeblack@google.com#endif 4712990Sgabeblack@google.com 4812990Sgabeblack@google.comusing namespace std; 4912990Sgabeblack@google.com 5012990Sgabeblack@google.comnamespace SparcISA 5112990Sgabeblack@google.com{ 5212990Sgabeblack@google.com 5312990Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 5412990Sgabeblack@google.com SparcFault<PowerOnReset>::vals = 5512990Sgabeblack@google.com {"power_on_reset", 0x001, 0, {H, H, H}}; 5612990Sgabeblack@google.com 5712990Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 5812990Sgabeblack@google.com SparcFault<WatchDogReset>::vals = 5912954Sgabeblack@google.com {"watch_dog_reset", 0x002, 120, {H, H, H}}; 6013042Sgabeblack@google.com 6113042Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 6213042Sgabeblack@google.com SparcFault<ExternallyInitiatedReset>::vals = 6313042Sgabeblack@google.com {"externally_initiated_reset", 0x003, 110, {H, H, H}}; 6413042Sgabeblack@google.com 6512982Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 6612982Sgabeblack@google.com SparcFault<SoftwareInitiatedReset>::vals = 6712982Sgabeblack@google.com {"software_initiated_reset", 0x004, 130, {SH, SH, H}}; 6812982Sgabeblack@google.com 6913403Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 7013077Sgabeblack@google.com SparcFault<REDStateException>::vals = 7113077Sgabeblack@google.com {"RED_state_exception", 0x005, 1, {H, H, H}}; 7213094Sgabeblack@google.com 7313094Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 7413094Sgabeblack@google.com SparcFault<StoreError>::vals = 7512990Sgabeblack@google.com {"store_error", 0x007, 201, {H, H, H}}; 7613207Sgabeblack@google.com 7713207Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 7813191Sgabeblack@google.com SparcFault<InstructionAccessException>::vals = 7913191Sgabeblack@google.com {"instruction_access_exception", 0x008, 300, {H, H, H}}; 8013059Sgabeblack@google.com 8113059Sgabeblack@google.com//XXX This trap is apparently dropped from ua2005 8213281Sgabeblack@google.com/*template<> SparcFaultBase::FaultVals 8313281Sgabeblack@google.com SparcFault<InstructionAccessMMUMiss>::vals = 8412982Sgabeblack@google.com {"inst_mmu", 0x009, 2, {H, H, H}};*/ 8512982Sgabeblack@google.com 8612982Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 8712982Sgabeblack@google.com SparcFault<InstructionAccessError>::vals = 8812982Sgabeblack@google.com {"instruction_access_error", 0x00A, 400, {H, H, H}}; 8913403Sgabeblack@google.com 9013077Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 9113077Sgabeblack@google.com SparcFault<IllegalInstruction>::vals = 9213188Sgabeblack@google.com {"illegal_instruction", 0x010, 620, {H, H, H}}; 9313207Sgabeblack@google.com 9413207Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 9513273Sgabeblack@google.com SparcFault<PrivilegedOpcode>::vals = 9613273Sgabeblack@google.com {"privileged_opcode", 0x011, 700, {P, SH, SH}}; 9713053Sgabeblack@google.com 9813188Sgabeblack@google.com//XXX This trap is apparently dropped from ua2005 9913207Sgabeblack@google.com/*template<> SparcFaultBase::FaultVals 10013207Sgabeblack@google.com SparcFault<UnimplementedLDD>::vals = 10113191Sgabeblack@google.com {"unimp_ldd", 0x012, 6, {H, H, H}};*/ 10213191Sgabeblack@google.com 10313188Sgabeblack@google.com//XXX This trap is apparently dropped from ua2005 10413188Sgabeblack@google.com/*template<> SparcFaultBase::FaultVals 10513188Sgabeblack@google.com SparcFault<UnimplementedSTD>::vals = 10613701Sgabeblack@google.com {"unimp_std", 0x013, 6, {H, H, H}};*/ 10713059Sgabeblack@google.com 10812982Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 10912953Sgabeblack@google.com SparcFault<FpDisabled>::vals = 11012953Sgabeblack@google.com {"fp_disabled", 0x020, 800, {P, P, H}}; 11112953Sgabeblack@google.com 11212837Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 11313403Sgabeblack@google.com SparcFault<FpExceptionIEEE754>::vals = 11413077Sgabeblack@google.com {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}}; 11513077Sgabeblack@google.com 11613156Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 11713156Sgabeblack@google.com SparcFault<FpExceptionOther>::vals = 11813156Sgabeblack@google.com {"fp_exception_other", 0x022, 1110, {P, P, H}}; 11913156Sgabeblack@google.com 12013156Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 12113188Sgabeblack@google.com SparcFault<TagOverflow>::vals = 12213188Sgabeblack@google.com {"tag_overflow", 0x023, 1400, {P, P, H}}; 12313207Sgabeblack@google.com 12413207Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 12513191Sgabeblack@google.com SparcFault<CleanWindow>::vals = 12613191Sgabeblack@google.com {"clean_window", 0x024, 1010, {P, P, H}}; 12713188Sgabeblack@google.com 12813188Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 12913188Sgabeblack@google.com SparcFault<DivisionByZero>::vals = 13013701Sgabeblack@google.com {"division_by_zero", 0x028, 1500, {P, P, H}}; 13113059Sgabeblack@google.com 13212982Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 13312990Sgabeblack@google.com SparcFault<InternalProcessorError>::vals = 13412982Sgabeblack@google.com {"internal_processor_error", 0x029, 4, {H, H, H}}; 13512990Sgabeblack@google.com 13612982Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 13712982Sgabeblack@google.com SparcFault<InstructionInvalidTSBEntry>::vals = 13812982Sgabeblack@google.com {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}}; 13912953Sgabeblack@google.com 14012953Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 14112953Sgabeblack@google.com SparcFault<DataInvalidTSBEntry>::vals = 14212982Sgabeblack@google.com {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}}; 14312982Sgabeblack@google.com 14412982Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 14512990Sgabeblack@google.com SparcFault<DataAccessException>::vals = 14612982Sgabeblack@google.com {"data_access_exception", 0x030, 1201, {H, H, H}}; 14712982Sgabeblack@google.com 14812982Sgabeblack@google.com//XXX This trap is apparently dropped from ua2005 14912982Sgabeblack@google.com/*template<> SparcFaultBase::FaultVals 15012982Sgabeblack@google.com SparcFault<DataAccessMMUMiss>::vals = 15112982Sgabeblack@google.com {"data_mmu", 0x031, 12, {H, H, H}};*/ 15212982Sgabeblack@google.com 15312990Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 15413188Sgabeblack@google.com SparcFault<DataAccessError>::vals = 15513207Sgabeblack@google.com {"data_access_error", 0x032, 1210, {H, H, H}}; 15613207Sgabeblack@google.com 15713191Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 15813191Sgabeblack@google.com SparcFault<DataAccessProtection>::vals = 15913188Sgabeblack@google.com {"data_access_protection", 0x033, 1207, {H, H, H}}; 16013188Sgabeblack@google.com 16113188Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 16213701Sgabeblack@google.com SparcFault<MemAddressNotAligned>::vals = 16313059Sgabeblack@google.com {"mem_address_not_aligned", 0x034, 1020, {H, H, H}}; 16412982Sgabeblack@google.com 16512990Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 16612982Sgabeblack@google.com SparcFault<LDDFMemAddressNotAligned>::vals = 16712990Sgabeblack@google.com {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}}; 16812982Sgabeblack@google.com 16912982Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 17012982Sgabeblack@google.com SparcFault<STDFMemAddressNotAligned>::vals = 17112953Sgabeblack@google.com {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}}; 17212953Sgabeblack@google.com 17313156Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 17413156Sgabeblack@google.com SparcFault<PrivilegedAction>::vals = 17513156Sgabeblack@google.com {"privileged_action", 0x037, 1110, {H, H, SH}}; 17613156Sgabeblack@google.com 17713156Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 17813156Sgabeblack@google.com SparcFault<LDQFMemAddressNotAligned>::vals = 17913156Sgabeblack@google.com {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}}; 18013156Sgabeblack@google.com 18112837Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 18212837Sgabeblack@google.com SparcFault<STQFMemAddressNotAligned>::vals = 18312982Sgabeblack@google.com {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}}; 18412837Sgabeblack@google.com 18512982Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 18612982Sgabeblack@google.com SparcFault<InstructionRealTranslationMiss>::vals = 18712982Sgabeblack@google.com {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}}; 18812837Sgabeblack@google.com 18912837Sgabeblack@google.comtemplate<> SparcFaultBase::FaultVals 19012982Sgabeblack@google.com SparcFault<DataRealTranslationMiss>::vals = 19112982Sgabeblack@google.com {"data_real_translation_miss", 0x03F, 1203, {H, H, H}}; 19212982Sgabeblack@google.com 19312982Sgabeblack@google.com//XXX This trap is apparently dropped from ua2005 19412837Sgabeblack@google.com/*template<> SparcFaultBase::FaultVals 195 SparcFault<AsyncDataError>::vals = 196 {"async_data", 0x040, 2, {H, H, H}};*/ 197 198template<> SparcFaultBase::FaultVals 199 SparcFault<InterruptLevelN>::vals = 200 {"interrupt_level_n", 0x041, 0, {P, P, SH}}; 201 202template<> SparcFaultBase::FaultVals 203 SparcFault<HstickMatch>::vals = 204 {"hstick_match", 0x05E, 1601, {H, H, H}}; 205 206template<> SparcFaultBase::FaultVals 207 SparcFault<TrapLevelZero>::vals = 208 {"trap_level_zero", 0x05F, 202, {H, H, SH}}; 209 210template<> SparcFaultBase::FaultVals 211 SparcFault<PAWatchpoint>::vals = 212 {"PA_watchpoint", 0x061, 1209, {H, H, H}}; 213 214template<> SparcFaultBase::FaultVals 215 SparcFault<VAWatchpoint>::vals = 216 {"VA_watchpoint", 0x062, 1120, {P, P, SH}}; 217 218template<> SparcFaultBase::FaultVals 219 SparcFault<FastInstructionAccessMMUMiss>::vals = 220 {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}}; 221 222template<> SparcFaultBase::FaultVals 223 SparcFault<FastDataAccessMMUMiss>::vals = 224 {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}}; 225 226template<> SparcFaultBase::FaultVals 227 SparcFault<FastDataAccessProtection>::vals = 228 {"fast_data_access_protection", 0x06C, 1207, {H, H, H}}; 229 230template<> SparcFaultBase::FaultVals 231 SparcFault<InstructionBreakpoint>::vals = 232 {"instruction_break", 0x076, 610, {H, H, H}}; 233 234template<> SparcFaultBase::FaultVals 235 SparcFault<CpuMondo>::vals = 236 {"cpu_mondo", 0x07C, 1608, {P, P, SH}}; 237 238template<> SparcFaultBase::FaultVals 239 SparcFault<DevMondo>::vals = 240 {"dev_mondo", 0x07D, 1611, {P, P, SH}}; 241 242template<> SparcFaultBase::FaultVals 243 SparcFault<ResumeableError>::vals = 244 {"resume_error", 0x07E, 3330, {P, P, SH}}; 245 246template<> SparcFaultBase::FaultVals 247 SparcFault<SpillNNormal>::vals = 248 {"spill_n_normal", 0x080, 900, {P, P, H}}; 249 250template<> SparcFaultBase::FaultVals 251 SparcFault<SpillNOther>::vals = 252 {"spill_n_other", 0x0A0, 900, {P, P, H}}; 253 254template<> SparcFaultBase::FaultVals 255 SparcFault<FillNNormal>::vals = 256 {"fill_n_normal", 0x0C0, 900, {P, P, H}}; 257 258template<> SparcFaultBase::FaultVals 259 SparcFault<FillNOther>::vals = 260 {"fill_n_other", 0x0E0, 900, {P, P, H}}; 261 262template<> SparcFaultBase::FaultVals 263 SparcFault<TrapInstruction>::vals = 264 {"trap_instruction", 0x100, 1602, {P, P, H}}; 265 266#if !FULL_SYSTEM 267template<> SparcFaultBase::FaultVals 268 SparcFault<PageTableFault>::vals = 269 {"page_table_fault", 0x0000, 0, {SH, SH, SH}}; 270#endif 271 272/** 273 * This causes the thread context to enter RED state. This causes the side 274 * effects which go with entering RED state because of a trap. 275 */ 276 277void enterREDState(ThreadContext *tc) 278{ 279 //@todo Disable the mmu? 280 //@todo Disable watchpoints? 281 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); 282 //HPSTATE.red = 1 283 HPSTATE |= (1 << 5); 284 //HPSTATE.hpriv = 1 285 HPSTATE |= (1 << 2); 286 tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE); 287 //PSTATE.priv is set to 1 here. The manual says it should be 0, but 288 //Legion sets it to 1. 289 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); 290 PSTATE |= (1 << 2); 291 tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE); 292} 293 294/** 295 * This sets everything up for a RED state trap except for actually jumping to 296 * the handler. 297 */ 298 299void doREDFault(ThreadContext *tc, TrapType tt) 300{ 301 MiscReg TL = tc->readMiscReg(MISCREG_TL); 302 MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE); 303 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); 304 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); 305 MiscReg CCR = tc->readMiscReg(MISCREG_CCR); 306 MiscReg ASI = tc->readMiscReg(MISCREG_ASI); 307 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 308 MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE); 309 MiscReg GL = tc->readMiscReg(MISCREG_GL); 310 MiscReg PC = tc->readPC(); 311 MiscReg NPC = tc->readNextPC(); 312 313 TL++; 314 315 //set TSTATE.gl to gl 316 replaceBits(TSTATE, 42, 40, GL); 317 //set TSTATE.ccr to ccr 318 replaceBits(TSTATE, 39, 32, CCR); 319 //set TSTATE.asi to asi 320 replaceBits(TSTATE, 31, 24, ASI); 321 //set TSTATE.pstate to pstate 322 replaceBits(TSTATE, 20, 8, PSTATE); 323 //set TSTATE.cwp to cwp 324 replaceBits(TSTATE, 4, 0, CWP); 325 326 //Write back TSTATE 327 tc->setMiscReg(MISCREG_TSTATE, TSTATE); 328 329 //set TPC to PC 330 tc->setMiscReg(MISCREG_TPC, PC); 331 //set TNPC to NPC 332 tc->setMiscReg(MISCREG_TNPC, NPC); 333 334 //set HTSTATE.hpstate to hpstate 335 tc->setMiscReg(MISCREG_HTSTATE, HPSTATE); 336 337 //TT = trap type; 338 tc->setMiscReg(MISCREG_TT, tt); 339 340 //Update GL 341 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL)); 342 343 //set PSTATE.mm to 00 344 //set PSTATE.pef to 1 345 PSTATE |= (1 << 4); 346 //set PSTATE.am to 0 347 PSTATE &= ~(1 << 3); 348/* //set PSTATE.priv to 0 349 PSTATE &= ~(1 << 2);*/ 350 //set PSTATE.ie to 0 351 //PSTATE.priv is set to 1 here. The manual says it should be 0, but 352 //Legion sets it to 1. 353 PSTATE |= (1 << 2); 354 //set PSTATE.cle to 0 355 PSTATE &= ~(1 << 9); 356 //PSTATE.tle is unchanged 357 //XXX Where is the tct bit? 358 //set PSTATE.tct to 0 359 tc->setMiscReg(MISCREG_PSTATE, PSTATE); 360 361 //set HPSTATE.red to 1 362 HPSTATE |= (1 << 5); 363 //set HPSTATE.hpriv to 1 364 HPSTATE |= (1 << 2); 365 //set HPSTATE.ibe to 0 366 HPSTATE &= ~(1 << 10); 367 //set HPSTATE.tlz to 0 368 HPSTATE &= ~(1 << 0); 369 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); 370 371 bool changedCWP = true; 372 if(tt == 0x24) 373 CWP++; 374 else if(0x80 <= tt && tt <= 0xbf) 375 CWP += (CANSAVE + 2); 376 else if(0xc0 <= tt && tt <= 0xff) 377 CWP--; 378 else 379 changedCWP = false; 380 381 if(changedCWP) 382 { 383 CWP = (CWP + NWindows) % NWindows; 384 tc->setMiscRegWithEffect(MISCREG_CWP, CWP); 385 } 386} 387 388/** 389 * This sets everything up for a normal trap except for actually jumping to 390 * the handler. 391 */ 392 393void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) 394{ 395 MiscReg TL = tc->readMiscReg(MISCREG_TL); 396 MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE); 397 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); 398 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); 399 MiscReg CCR = tc->readMiscReg(MISCREG_CCR); 400 MiscReg ASI = tc->readMiscReg(MISCREG_ASI); 401 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 402 MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE); 403 MiscReg GL = tc->readMiscReg(MISCREG_GL); 404 MiscReg PC = tc->readPC(); 405 MiscReg NPC = tc->readNextPC(); 406 407 //Increment the trap level 408 TL++; 409 tc->setMiscReg(MISCREG_TL, TL); 410 411 //Save off state 412 413 //set TSTATE.gl to gl 414 replaceBits(TSTATE, 42, 40, GL); 415 //set TSTATE.ccr to ccr 416 replaceBits(TSTATE, 39, 32, CCR); 417 //set TSTATE.asi to asi 418 replaceBits(TSTATE, 31, 24, ASI); 419 //set TSTATE.pstate to pstate 420 replaceBits(TSTATE, 20, 8, PSTATE); 421 //set TSTATE.cwp to cwp 422 replaceBits(TSTATE, 4, 0, CWP); 423 424 //Write back TSTATE 425 tc->setMiscReg(MISCREG_TSTATE, TSTATE); 426 427 //set TPC to PC 428 tc->setMiscReg(MISCREG_TPC, PC); 429 //set TNPC to NPC 430 tc->setMiscReg(MISCREG_TNPC, NPC); 431 432 //set HTSTATE.hpstate to hpstate 433 tc->setMiscReg(MISCREG_HTSTATE, HPSTATE); 434 435 //TT = trap type; 436 tc->setMiscReg(MISCREG_TT, tt); 437 438 //Update the global register level 439 if(!gotoHpriv) 440 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL)); 441 else 442 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL)); 443 444 //PSTATE.mm is unchanged 445 //PSTATE.pef = whether or not an fpu is present 446 //XXX We'll say there's one present, even though there aren't 447 //implementations for a decent number of the instructions 448 PSTATE |= (1 << 4); 449 //PSTATE.am = 0 450 PSTATE &= ~(1 << 3); 451 if(!gotoHpriv) 452 { 453 //PSTATE.priv = 1 454 PSTATE |= (1 << 2); 455 //PSTATE.cle = PSTATE.tle 456 replaceBits(PSTATE, 9, 9, PSTATE >> 8); 457 } 458 else 459 { 460 //PSTATE.priv = 0 461 //PSTATE.priv is set to 1 here. The manual says it should be 0, but 462 //Legion sets it to 1. 463 PSTATE |= (1 << 2); 464 //PSTATE.cle = 0 465 PSTATE &= ~(1 << 9); 466 } 467 //PSTATE.ie = 0 468 PSTATE &= ~(1 << 1); 469 //PSTATE.tle is unchanged 470 //PSTATE.tct = 0 471 //XXX Where exactly is this field? 472 tc->setMiscReg(MISCREG_PSTATE, PSTATE); 473 474 if(gotoHpriv) 475 { 476 //HPSTATE.red = 0 477 HPSTATE &= ~(1 << 5); 478 //HPSTATE.hpriv = 1 479 HPSTATE |= (1 << 2); 480 //HPSTATE.ibe = 0 481 HPSTATE &= ~(1 << 10); 482 //HPSTATE.tlz is unchanged 483 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); 484 } 485 486 bool changedCWP = true; 487 if(tt == 0x24) 488 CWP++; 489 else if(0x80 <= tt && tt <= 0xbf) 490 CWP += (CANSAVE + 2); 491 else if(0xc0 <= tt && tt <= 0xff) 492 CWP--; 493 else 494 changedCWP = false; 495 496 if(changedCWP) 497 { 498 CWP = (CWP + NWindows) % NWindows; 499 tc->setMiscRegWithEffect(MISCREG_CWP, CWP); 500 } 501} 502 503void getREDVector(MiscReg TT, Addr & PC, Addr & NPC) 504{ 505 //XXX The following constant might belong in a header file. 506 const Addr RSTVAddr = 0xFFF0000000ULL; 507 PC = RSTVAddr | ((TT << 5) & 0xFF); 508 NPC = PC + sizeof(MachInst); 509} 510 511void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT) 512{ 513 Addr HTBA = tc->readMiscReg(MISCREG_HTBA); 514 PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14)); 515 NPC = PC + sizeof(MachInst); 516} 517 518void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL) 519{ 520 Addr TBA = tc->readMiscReg(MISCREG_TBA); 521 PC = (TBA & ~mask(15)) | 522 (TL > 1 ? (1 << 14) : 0) | 523 ((TT << 5) & mask(14)); 524 NPC = PC + sizeof(MachInst); 525} 526 527#if FULL_SYSTEM 528 529void SparcFaultBase::invoke(ThreadContext * tc) 530{ 531 panic("Invoking a second fault!\n"); 532 FaultBase::invoke(tc); 533 countStat()++; 534 535 //We can refer to this to see what the trap level -was-, but something 536 //in the middle could change it in the regfile out from under us. 537 MiscReg TL = tc->readMiscReg(MISCREG_TL); 538 MiscReg TT = tc->readMiscReg(MISCREG_TT); 539 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); 540 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); 541 542 Addr PC, NPC; 543 544 PrivilegeLevel current; 545 if(HPSTATE & (1 << 2)) 546 current = Hyperprivileged; 547 else if(PSTATE & (1 << 2)) 548 current = Privileged; 549 else 550 current = User; 551 552 PrivilegeLevel level = getNextLevel(current); 553 554 if(HPSTATE & (1 << 5) || TL == MaxTL - 1) 555 { 556 getREDVector(5, PC, NPC); 557 doREDFault(tc, TT); 558 //This changes the hpstate and pstate, so we need to make sure we 559 //save the old version on the trap stack in doREDFault. 560 enterREDState(tc); 561 } 562 else if(TL == MaxTL) 563 { 564 //Do error_state somehow? 565 //Probably inject a WDR fault using the interrupt mechanism. 566 //What should the PC and NPC be set to? 567 } 568 else if(TL > MaxPTL && level == Privileged) 569 { 570 //guest_watchdog fault 571 doNormalFault(tc, trapType(), true); 572 getHyperVector(tc, PC, NPC, 2); 573 } 574 else if(level == Hyperprivileged) 575 { 576 doNormalFault(tc, trapType(), true); 577 getHyperVector(tc, PC, NPC, trapType()); 578 } 579 else 580 { 581 doNormalFault(tc, trapType(), false); 582 getPrivVector(tc, PC, NPC, trapType(), TL+1); 583 } 584 585 tc->setPC(PC); 586 tc->setNextPC(NPC); 587 tc->setNextNPC(NPC + sizeof(MachInst)); 588} 589 590void PowerOnReset::invoke(ThreadContext * tc) 591{ 592 //For SPARC, when a system is first started, there is a power 593 //on reset Trap which sets the processor into the following state. 594 //Bits that aren't set aren't defined on startup. 595 596 tc->setMiscReg(MISCREG_TL, MaxTL); 597 tc->setMiscReg(MISCREG_TT, trapType()); 598 tc->setMiscRegWithEffect(MISCREG_GL, MaxGL); 599 600 //Turn on pef and priv, set everything else to 0 601 tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2)); 602 603 //Turn on red and hpriv, set everything else to 0 604 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); 605 //HPSTATE.red = 1 606 HPSTATE |= (1 << 5); 607 //HPSTATE.hpriv = 1 608 HPSTATE |= (1 << 2); 609 //HPSTATE.ibe = 0 610 HPSTATE &= ~(1 << 10); 611 //HPSTATE.tlz = 0 612 HPSTATE &= ~(1 << 0); 613 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); 614 615 //The tick register is unreadable by nonprivileged software 616 tc->setMiscReg(MISCREG_TICK, 1ULL << 63); 617 618 //Enter RED state. We do this last so that the actual state preserved in 619 //the trap stack is the state from before this fault. 620 enterREDState(tc); 621 622 Addr PC, NPC; 623 getREDVector(trapType(), PC, NPC); 624 tc->setPC(PC); 625 tc->setNextPC(NPC); 626 tc->setNextNPC(NPC + sizeof(MachInst)); 627 628 //These registers are specified as "undefined" after a POR, and they 629 //should have reasonable values after the miscregfile is reset 630 /* 631 // Clear all the soft interrupt bits 632 softint = 0; 633 // disable timer compare interrupts, reset tick_cmpr 634 tc->setMiscReg(MISCREG_ 635 tick_cmprFields.int_dis = 1; 636 tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 637 stickFields.npt = 1; //The TICK register is unreadable by by !priv 638 stick_cmprFields.int_dis = 1; // disable timer compare interrupts 639 stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 640 641 tt[tl] = _trapType; 642 643 hintp = 0; // no interrupts pending 644 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts 645 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 646 */ 647} 648 649#else // !FULL_SYSTEM 650 651void SpillNNormal::invoke(ThreadContext *tc) 652{ 653 doNormalFault(tc, trapType(), false); 654 655 Process *p = tc->getProcessPtr(); 656 657 //XXX This will only work in faults from a SparcLiveProcess 658 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 659 assert(lp); 660 661 //Then adjust the PC and NPC 662 Addr spillStart = lp->readSpillStart(); 663 tc->setPC(spillStart); 664 tc->setNextPC(spillStart + sizeof(MachInst)); 665 tc->setNextNPC(spillStart + 2*sizeof(MachInst)); 666} 667 668void FillNNormal::invoke(ThreadContext *tc) 669{ 670 doNormalFault(tc, trapType(), false); 671 672 Process * p = tc->getProcessPtr(); 673 674 //XXX This will only work in faults from a SparcLiveProcess 675 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 676 assert(lp); 677 678 //Then adjust the PC and NPC 679 Addr fillStart = lp->readFillStart(); 680 tc->setPC(fillStart); 681 tc->setNextPC(fillStart + sizeof(MachInst)); 682 tc->setNextNPC(fillStart + 2*sizeof(MachInst)); 683} 684 685void PageTableFault::invoke(ThreadContext *tc) 686{ 687 Process *p = tc->getProcessPtr(); 688 689 // address is higher than the stack region or in the current stack region 690 if (vaddr > p->stack_base || vaddr > p->stack_min) 691 FaultBase::invoke(tc); 692 693 // We've accessed the next page 694 if (vaddr > p->stack_min - PageBytes) { 695 p->stack_min -= PageBytes; 696 if (p->stack_base - p->stack_min > 8*1024*1024) 697 fatal("Over max stack size for one thread\n"); 698 p->pTable->allocate(p->stack_min, PageBytes); 699 warn("Increasing stack size by one page."); 700 } else { 701 FaultBase::invoke(tc); 702 } 703} 704 705#endif 706 707} // namespace SparcISA 708 709