faults.cc revision 3578 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#include <algorithm>
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/types.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/thread_context.hh"
42#if !FULL_SYSTEM
43#include "arch/sparc/process.hh"
44#include "mem/page_table.hh"
45#include "sim/process.hh"
46#endif
47
48using namespace std;
49
50namespace SparcISA
51{
52
53template<> SparcFaultBase::FaultVals
54    SparcFault<PowerOnReset>::vals =
55    {"power_on_reset", 0x001, 0, {H, H, H}};
56
57template<> SparcFaultBase::FaultVals
58    SparcFault<WatchDogReset>::vals =
59    {"watch_dog_reset", 0x002, 120, {H, H, H}};
60
61template<> SparcFaultBase::FaultVals
62    SparcFault<ExternallyInitiatedReset>::vals =
63    {"externally_initiated_reset", 0x003, 110, {H, H, H}};
64
65template<> SparcFaultBase::FaultVals
66    SparcFault<SoftwareInitiatedReset>::vals =
67    {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
68
69template<> SparcFaultBase::FaultVals
70    SparcFault<REDStateException>::vals =
71    {"RED_state_exception", 0x005, 1, {H, H, H}};
72
73template<> SparcFaultBase::FaultVals
74    SparcFault<StoreError>::vals =
75    {"store_error", 0x007, 201, {H, H, H}};
76
77template<> SparcFaultBase::FaultVals
78    SparcFault<InstructionAccessException>::vals =
79    {"instruction_access_exception", 0x008, 300, {H, H, H}};
80
81//XXX This trap is apparently dropped from ua2005
82/*template<> SparcFaultBase::FaultVals
83    SparcFault<InstructionAccessMMUMiss>::vals =
84    {"inst_mmu", 0x009, 2, {H, H, H}};*/
85
86template<> SparcFaultBase::FaultVals
87    SparcFault<InstructionAccessError>::vals =
88    {"instruction_access_error", 0x00A, 400, {H, H, H}};
89
90template<> SparcFaultBase::FaultVals
91    SparcFault<IllegalInstruction>::vals =
92    {"illegal_instruction", 0x010, 620, {H, H, H}};
93
94template<> SparcFaultBase::FaultVals
95    SparcFault<PrivilegedOpcode>::vals =
96    {"privileged_opcode", 0x011, 700, {P, SH, SH}};
97
98//XXX This trap is apparently dropped from ua2005
99/*template<> SparcFaultBase::FaultVals
100    SparcFault<UnimplementedLDD>::vals =
101    {"unimp_ldd", 0x012, 6, {H, H, H}};*/
102
103//XXX This trap is apparently dropped from ua2005
104/*template<> SparcFaultBase::FaultVals
105    SparcFault<UnimplementedSTD>::vals =
106    {"unimp_std", 0x013, 6, {H, H, H}};*/
107
108template<> SparcFaultBase::FaultVals
109    SparcFault<FpDisabled>::vals =
110    {"fp_disabled", 0x020, 800, {P, P, H}};
111
112template<> SparcFaultBase::FaultVals
113    SparcFault<FpExceptionIEEE754>::vals =
114    {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
115
116template<> SparcFaultBase::FaultVals
117    SparcFault<FpExceptionOther>::vals =
118    {"fp_exception_other", 0x022, 1110, {P, P, H}};
119
120template<> SparcFaultBase::FaultVals
121    SparcFault<TagOverflow>::vals =
122    {"tag_overflow", 0x023, 1400, {P, P, H}};
123
124template<> SparcFaultBase::FaultVals
125    SparcFault<CleanWindow>::vals =
126    {"clean_window", 0x024, 1010, {P, P, H}};
127
128template<> SparcFaultBase::FaultVals
129    SparcFault<DivisionByZero>::vals =
130    {"division_by_zero", 0x028, 1500, {P, P, H}};
131
132template<> SparcFaultBase::FaultVals
133    SparcFault<InternalProcessorError>::vals =
134    {"internal_processor_error", 0x029, 4, {H, H, H}};
135
136template<> SparcFaultBase::FaultVals
137    SparcFault<InstructionInvalidTSBEntry>::vals =
138    {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
139
140template<> SparcFaultBase::FaultVals
141    SparcFault<DataInvalidTSBEntry>::vals =
142    {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
143
144template<> SparcFaultBase::FaultVals
145    SparcFault<DataAccessException>::vals =
146    {"data_access_exception", 0x030, 1201, {H, H, H}};
147
148//XXX This trap is apparently dropped from ua2005
149/*template<> SparcFaultBase::FaultVals
150    SparcFault<DataAccessMMUMiss>::vals =
151    {"data_mmu", 0x031, 12, {H, H, H}};*/
152
153template<> SparcFaultBase::FaultVals
154    SparcFault<DataAccessError>::vals =
155    {"data_access_error", 0x032, 1210, {H, H, H}};
156
157template<> SparcFaultBase::FaultVals
158    SparcFault<DataAccessProtection>::vals =
159    {"data_access_protection", 0x033, 1207, {H, H, H}};
160
161template<> SparcFaultBase::FaultVals
162    SparcFault<MemAddressNotAligned>::vals =
163    {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
164
165template<> SparcFaultBase::FaultVals
166    SparcFault<LDDFMemAddressNotAligned>::vals =
167    {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
168
169template<> SparcFaultBase::FaultVals
170    SparcFault<STDFMemAddressNotAligned>::vals =
171    {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
172
173template<> SparcFaultBase::FaultVals
174    SparcFault<PrivilegedAction>::vals =
175    {"privileged_action", 0x037, 1110, {H, H, SH}};
176
177template<> SparcFaultBase::FaultVals
178    SparcFault<LDQFMemAddressNotAligned>::vals =
179    {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
180
181template<> SparcFaultBase::FaultVals
182    SparcFault<STQFMemAddressNotAligned>::vals =
183    {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
184
185template<> SparcFaultBase::FaultVals
186    SparcFault<InstructionRealTranslationMiss>::vals =
187    {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
188
189template<> SparcFaultBase::FaultVals
190    SparcFault<DataRealTranslationMiss>::vals =
191    {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
192
193//XXX This trap is apparently dropped from ua2005
194/*template<> SparcFaultBase::FaultVals
195    SparcFault<AsyncDataError>::vals =
196    {"async_data", 0x040, 2, {H, H, H}};*/
197
198template<> SparcFaultBase::FaultVals
199    SparcFault<InterruptLevelN>::vals =
200    {"interrupt_level_n", 0x041, 0, {P, P, SH}};
201
202template<> SparcFaultBase::FaultVals
203    SparcFault<HstickMatch>::vals =
204    {"hstick_match", 0x05E, 1601, {H, H, H}};
205
206template<> SparcFaultBase::FaultVals
207    SparcFault<TrapLevelZero>::vals =
208    {"trap_level_zero", 0x05F, 202, {H, H, SH}};
209
210template<> SparcFaultBase::FaultVals
211    SparcFault<PAWatchpoint>::vals =
212    {"PA_watchpoint", 0x061, 1209, {H, H, H}};
213
214template<> SparcFaultBase::FaultVals
215    SparcFault<VAWatchpoint>::vals =
216    {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
217
218template<> SparcFaultBase::FaultVals
219    SparcFault<FastInstructionAccessMMUMiss>::vals =
220    {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
221
222template<> SparcFaultBase::FaultVals
223    SparcFault<FastDataAccessMMUMiss>::vals =
224    {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
225
226template<> SparcFaultBase::FaultVals
227    SparcFault<FastDataAccessProtection>::vals =
228    {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
229
230template<> SparcFaultBase::FaultVals
231    SparcFault<InstructionBreakpoint>::vals =
232    {"instruction_break", 0x076, 610, {H, H, H}};
233
234template<> SparcFaultBase::FaultVals
235    SparcFault<CpuMondo>::vals =
236    {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
237
238template<> SparcFaultBase::FaultVals
239    SparcFault<DevMondo>::vals =
240    {"dev_mondo", 0x07D, 1611, {P, P, SH}};
241
242template<> SparcFaultBase::FaultVals
243    SparcFault<ResumeableError>::vals =
244    {"resume_error", 0x07E, 3330, {P, P, SH}};
245
246template<> SparcFaultBase::FaultVals
247    SparcFault<SpillNNormal>::vals =
248    {"spill_n_normal", 0x080, 900, {P, P, H}};
249
250template<> SparcFaultBase::FaultVals
251    SparcFault<SpillNOther>::vals =
252    {"spill_n_other", 0x0A0, 900, {P, P, H}};
253
254template<> SparcFaultBase::FaultVals
255    SparcFault<FillNNormal>::vals =
256    {"fill_n_normal", 0x0C0, 900, {P, P, H}};
257
258template<> SparcFaultBase::FaultVals
259    SparcFault<FillNOther>::vals =
260    {"fill_n_other", 0x0E0, 900, {P, P, H}};
261
262template<> SparcFaultBase::FaultVals
263    SparcFault<TrapInstruction>::vals =
264    {"trap_instruction", 0x100, 1602, {P, P, H}};
265
266#if !FULL_SYSTEM
267template<> SparcFaultBase::FaultVals
268    SparcFault<PageTableFault>::vals =
269    {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
270#endif
271
272/**
273 * This causes the thread context to enter RED state. This causes the side
274 * effects which go with entering RED state because of a trap.
275 */
276
277void enterREDState(ThreadContext *tc)
278{
279    //@todo Disable the mmu?
280    //@todo Disable watchpoints?
281    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
282    //HPSTATE.red = 1
283    HPSTATE |= (1 << 5);
284    //HPSTATE.hpriv = 1
285    HPSTATE |= (1 << 2);
286    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
287}
288
289/**
290 * This sets everything up for a RED state trap except for actually jumping to
291 * the handler.
292 */
293
294void doREDFault(ThreadContext *tc, TrapType tt)
295{
296    MiscReg TL = tc->readMiscReg(MISCREG_TL);
297    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
298    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
299    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
300    MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
301    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
302    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
303    MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
304    MiscReg GL = tc->readMiscReg(MISCREG_GL);
305    MiscReg PC = tc->readPC();
306    MiscReg NPC = tc->readNextPC();
307
308    TL++;
309
310    //set TSTATE.gl to gl
311    replaceBits(TSTATE, 42, 40, GL);
312    //set TSTATE.ccr to ccr
313    replaceBits(TSTATE, 39, 32, CCR);
314    //set TSTATE.asi to asi
315    replaceBits(TSTATE, 31, 24, ASI);
316    //set TSTATE.pstate to pstate
317    replaceBits(TSTATE, 20, 8, PSTATE);
318    //set TSTATE.cwp to cwp
319    replaceBits(TSTATE, 4, 0, CWP);
320
321    //Write back TSTATE
322    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
323
324    //set TPC to PC
325    tc->setMiscReg(MISCREG_TPC, PC);
326    //set TNPC to NPC
327    tc->setMiscReg(MISCREG_TNPC, NPC);
328
329    //set HTSTATE.hpstate to hpstate
330    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
331
332    //TT = trap type;
333    tc->setMiscReg(MISCREG_TT, tt);
334
335    //Update GL
336    tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
337
338    //set PSTATE.mm to 00
339    //set PSTATE.pef to 1
340    PSTATE |= (1 << 4);
341    //set PSTATE.am to 0
342    PSTATE &= ~(1 << 3);
343    //set PSTATE.priv to 0
344    PSTATE &= ~(1 << 2);
345    //set PSTATE.ie to 0
346    PSTATE &= ~(1 << 1);
347    //set PSTATE.cle to 0
348    PSTATE &= ~(1 << 9);
349    //PSTATE.tle is unchanged
350    //XXX Where is the tct bit?
351    //set PSTATE.tct to 0
352    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
353
354    //set HPSTATE.red to 1
355    HPSTATE |= (1 << 5);
356    //set HPSTATE.hpriv to 1
357    HPSTATE |= (1 << 2);
358    //set HPSTATE.ibe to 0
359    HPSTATE &= ~(1 << 10);
360    //set HPSTATE.tlz to 0
361    HPSTATE &= ~(1 << 0);
362    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
363
364    bool changedCWP = true;
365    if(tt == 0x24)
366        CWP++;
367    else if(0x80 <= tt && tt <= 0xbf)
368        CWP += (CANSAVE + 2);
369    else if(0xc0 <= tt && tt <= 0xff)
370        CWP--;
371    else
372        changedCWP = false;
373
374    if(changedCWP)
375    {
376        CWP = (CWP + NWindows) % NWindows;
377        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
378    }
379}
380
381/**
382 * This sets everything up for a normal trap except for actually jumping to
383 * the handler.
384 */
385
386void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
387{
388    MiscReg TL = tc->readMiscReg(MISCREG_TL);
389    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
390    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
391    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
392    MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
393    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
394    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
395    MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
396    MiscReg GL = tc->readMiscReg(MISCREG_GL);
397    MiscReg PC = tc->readPC();
398    MiscReg NPC = tc->readNextPC();
399
400    //Increment the trap level
401    TL++;
402    tc->setMiscReg(MISCREG_TL, TL);
403
404    //Save off state
405
406    //set TSTATE.gl to gl
407    replaceBits(TSTATE, 42, 40, GL);
408    //set TSTATE.ccr to ccr
409    replaceBits(TSTATE, 39, 32, CCR);
410    //set TSTATE.asi to asi
411    replaceBits(TSTATE, 31, 24, ASI);
412    //set TSTATE.pstate to pstate
413    replaceBits(TSTATE, 20, 8, PSTATE);
414    //set TSTATE.cwp to cwp
415    replaceBits(TSTATE, 4, 0, CWP);
416
417    //Write back TSTATE
418    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
419
420    //set TPC to PC
421    tc->setMiscReg(MISCREG_TPC, PC);
422    //set TNPC to NPC
423    tc->setMiscReg(MISCREG_TNPC, NPC);
424
425    //set HTSTATE.hpstate to hpstate
426    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
427
428    //TT = trap type;
429    tc->setMiscReg(MISCREG_TT, tt);
430
431    //Update the global register level
432    if(!gotoHpriv)
433        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
434    else
435        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
436
437    //PSTATE.mm is unchanged
438    //PSTATE.pef = whether or not an fpu is present
439    //XXX We'll say there's one present, even though there aren't
440    //implementations for a decent number of the instructions
441    PSTATE |= (1 << 4);
442    //PSTATE.am = 0
443    PSTATE &= ~(1 << 3);
444    if(!gotoHpriv)
445    {
446        //PSTATE.priv = 1
447        PSTATE |= (1 << 2);
448        //PSTATE.cle = PSTATE.tle
449        replaceBits(PSTATE, 9, 9, PSTATE >> 8);
450    }
451    else
452    {
453        //PSTATE.priv = 0
454        PSTATE &= ~(1 << 2);
455        //PSTATE.cle = 0
456        PSTATE &= ~(1 << 9);
457    }
458    //PSTATE.ie = 0
459    PSTATE &= ~(1 << 1);
460    //PSTATE.tle is unchanged
461    //PSTATE.tct = 0
462    //XXX Where exactly is this field?
463    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
464
465    if(gotoHpriv)
466    {
467        //HPSTATE.red = 0
468        HPSTATE &= ~(1 << 5);
469        //HPSTATE.hpriv = 1
470        HPSTATE |= (1 << 2);
471        //HPSTATE.ibe = 0
472        HPSTATE &= ~(1 << 10);
473        //HPSTATE.tlz is unchanged
474        tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
475    }
476
477    bool changedCWP = true;
478    if(tt == 0x24)
479        CWP++;
480    else if(0x80 <= tt && tt <= 0xbf)
481        CWP += (CANSAVE + 2);
482    else if(0xc0 <= tt && tt <= 0xff)
483        CWP--;
484    else
485        changedCWP = false;
486
487    if(changedCWP)
488    {
489        CWP = (CWP + NWindows) % NWindows;
490        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
491    }
492}
493
494void getREDVector(Addr & PC, Addr & NPC)
495{
496    const Addr RSTVAddr = 0xFFFFFFFFF0000000ULL;
497    PC = RSTVAddr | 0xA0;
498    NPC = PC + sizeof(MachInst);
499}
500
501void getHyperVector(Addr & PC, Addr & NPC, MiscReg TT)
502{
503    Addr HTBA ;
504    PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
505    NPC = PC + sizeof(MachInst);
506}
507
508void getPrivVector(Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
509{
510    Addr TBA ;
511    PC = (TBA & ~mask(15)) |
512        (TL > 1 ? (1 << 14) : 0) |
513        ((TT << 5) & mask(14));
514    NPC = PC + sizeof(MachInst);
515}
516
517#if FULL_SYSTEM
518
519void SparcFaultBase::invoke(ThreadContext * tc)
520{
521    FaultBase::invoke(tc);
522    countStat()++;
523
524    //We can refer to this to see what the trap level -was-, but something
525    //in the middle could change it in the regfile out from under us.
526    MiscReg TL = tc->readMiscReg(MISCREG_TL);
527    MiscReg TT = tc->readMiscReg(MISCREG_TT);
528    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
529    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
530
531    Addr PC, NPC;
532
533    PrivilegeLevel current;
534    if(!(PSTATE & (1 << 2)))
535        current = User;
536    else if(!(HPSTATE & (1 << 2)))
537        current = Privileged;
538    else
539        current = Hyperprivileged;
540
541    PrivilegeLevel level = getNextLevel(current);
542
543    if(HPSTATE & (1 << 5) || TL == MaxTL - 1)
544    {
545        getREDVector(PC, NPC);
546        enterREDState(tc);
547        doREDFault(tc, TT);
548    }
549    else if(TL == MaxTL)
550    {
551        //Do error_state somehow?
552        //Probably inject a WDR fault using the interrupt mechanism.
553        //What should the PC and NPC be set to?
554    }
555    else if(TL > MaxPTL && level == Privileged)
556    {
557        //guest_watchdog fault
558        doNormalFault(tc, trapType(), true);
559        getHyperVector(PC, NPC, 2);
560    }
561    else if(level == Hyperprivileged)
562    {
563        doNormalFault(tc, trapType(), true);
564        getHyperVector(PC, NPC, trapType());
565    }
566    else
567    {
568        doNormalFault(tc, trapType(), false);
569        getPrivVector(PC, NPC, trapType(), TL+1);
570    }
571
572    tc->setPC(PC);
573    tc->setNextPC(NPC);
574    tc->setNextNPC(NPC + sizeof(MachInst));
575}
576
577void PowerOnReset::invoke(ThreadContext * tc)
578{
579    //First, enter RED state.
580    enterREDState(tc);
581
582    //For SPARC, when a system is first started, there is a power
583    //on reset Trap which sets the processor into the following state.
584    //Bits that aren't set aren't defined on startup.
585    /*
586    tl = MaxTL;
587    gl = MaxGL;
588
589    tickFields.counter = 0; //The TICK register is unreadable bya
590    tickFields.npt = 1; //The TICK register is unreadable by by !priv
591
592    softint = 0; // Clear all the soft interrupt bits
593    tick_cmprFields.int_dis = 1; // disable timer compare interrupts
594    tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
595    stickFields.npt = 1; //The TICK register is unreadable by by !priv
596    stick_cmprFields.int_dis = 1; // disable timer compare interrupts
597    stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
598
599    tt[tl] = _trapType;
600    pstate = 0; // fields 0 but pef
601    pstateFields.pef = 1;
602
603    hpstate = 0;
604    hpstateFields.red = 1;
605    hpstateFields.hpriv = 1;
606    hpstateFields.tlz = 0; // this is a guess
607    hintp = 0; // no interrupts pending
608    hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
609    hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
610    */
611}
612
613#else // !FULL_SYSTEM
614
615void SpillNNormal::invoke(ThreadContext *tc)
616{
617    doNormalFault(tc, trapType(), false);
618
619    Process *p = tc->getProcessPtr();
620
621    //XXX This will only work in faults from a SparcLiveProcess
622    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
623    assert(lp);
624
625    //Then adjust the PC and NPC
626    Addr spillStart = lp->readSpillStart();
627    tc->setPC(spillStart);
628    tc->setNextPC(spillStart + sizeof(MachInst));
629    tc->setNextNPC(spillStart + 2*sizeof(MachInst));
630}
631
632void FillNNormal::invoke(ThreadContext *tc)
633{
634    doNormalFault(tc, trapType(), false);
635
636    Process * p = tc->getProcessPtr();
637
638    //XXX This will only work in faults from a SparcLiveProcess
639    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
640    assert(lp);
641
642    //Then adjust the PC and NPC
643    Addr fillStart = lp->readFillStart();
644    tc->setPC(fillStart);
645    tc->setNextPC(fillStart + sizeof(MachInst));
646    tc->setNextNPC(fillStart + 2*sizeof(MachInst));
647}
648
649void PageTableFault::invoke(ThreadContext *tc)
650{
651    Process *p = tc->getProcessPtr();
652
653    // address is higher than the stack region or in the current stack region
654    if (vaddr > p->stack_base || vaddr > p->stack_min)
655        FaultBase::invoke(tc);
656
657    // We've accessed the next page
658    if (vaddr > p->stack_min - PageBytes) {
659        p->stack_min -= PageBytes;
660        if (p->stack_base - p->stack_min > 8*1024*1024)
661            fatal("Over max stack size for one thread\n");
662        p->pTable->allocate(p->stack_min, PageBytes);
663        warn("Increasing stack size by one page.");
664    } else {
665        FaultBase::invoke(tc);
666    }
667}
668
669#endif
670
671} // namespace SparcISA
672
673