faults.cc revision 12455 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#include "arch/sparc/faults.hh"
33
34#include <algorithm>
35
36#include "arch/sparc/isa_traits.hh"
37#include "arch/sparc/process.hh"
38#include "arch/sparc/types.hh"
39#include "base/bitfield.hh"
40#include "base/trace.hh"
41#include "cpu/base.hh"
42#include "cpu/thread_context.hh"
43#include "mem/page_table.hh"
44#include "sim/full_system.hh"
45#include "sim/process.hh"
46
47using namespace std;
48
49namespace SparcISA
50{
51
52template<> SparcFaultBase::FaultVals
53    SparcFault<PowerOnReset>::vals =
54{"power_on_reset", 0x001, 0, {H, H, H}, FaultStat()};
55
56template<> SparcFaultBase::FaultVals
57    SparcFault<WatchDogReset>::vals =
58{"watch_dog_reset", 0x002, 120, {H, H, H}, FaultStat()};
59
60template<> SparcFaultBase::FaultVals
61    SparcFault<ExternallyInitiatedReset>::vals =
62{"externally_initiated_reset", 0x003, 110, {H, H, H}, FaultStat()};
63
64template<> SparcFaultBase::FaultVals
65    SparcFault<SoftwareInitiatedReset>::vals =
66{"software_initiated_reset", 0x004, 130, {SH, SH, H}, FaultStat()};
67
68template<> SparcFaultBase::FaultVals
69    SparcFault<REDStateException>::vals =
70{"RED_state_exception", 0x005, 1, {H, H, H}, FaultStat()};
71
72template<> SparcFaultBase::FaultVals
73    SparcFault<StoreError>::vals =
74{"store_error", 0x007, 201, {H, H, H}, FaultStat()};
75
76template<> SparcFaultBase::FaultVals
77    SparcFault<InstructionAccessException>::vals =
78{"instruction_access_exception", 0x008, 300, {H, H, H}, FaultStat()};
79
80//XXX This trap is apparently dropped from ua2005
81/*template<> SparcFaultBase::FaultVals
82    SparcFault<InstructionAccessMMUMiss>::vals =
83    {"inst_mmu", 0x009, 2, {H, H, H}};*/
84
85template<> SparcFaultBase::FaultVals
86    SparcFault<InstructionAccessError>::vals =
87{"instruction_access_error", 0x00A, 400, {H, H, H}, FaultStat()};
88
89template<> SparcFaultBase::FaultVals
90    SparcFault<IllegalInstruction>::vals =
91{"illegal_instruction", 0x010, 620, {H, H, H}, FaultStat()};
92
93template<> SparcFaultBase::FaultVals
94    SparcFault<PrivilegedOpcode>::vals =
95{"privileged_opcode", 0x011, 700, {P, SH, SH}, FaultStat()};
96
97//XXX This trap is apparently dropped from ua2005
98/*template<> SparcFaultBase::FaultVals
99    SparcFault<UnimplementedLDD>::vals =
100    {"unimp_ldd", 0x012, 6, {H, H, H}};*/
101
102//XXX This trap is apparently dropped from ua2005
103/*template<> SparcFaultBase::FaultVals
104    SparcFault<UnimplementedSTD>::vals =
105    {"unimp_std", 0x013, 6, {H, H, H}};*/
106
107template<> SparcFaultBase::FaultVals
108    SparcFault<FpDisabled>::vals =
109{"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()};
110
111/* SPARCv8 and SPARCv9 define just fp_disabled trap. SIMD is not contemplated
112 * as a separate part. Therefore, we use the same code and TT */
113template<> SparcFaultBase::FaultVals
114    SparcFault<VecDisabled>::vals =
115{"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()};
116
117template<> SparcFaultBase::FaultVals
118    SparcFault<FpExceptionIEEE754>::vals =
119{"fp_exception_ieee_754", 0x021, 1110, {P, P, H}, FaultStat()};
120
121template<> SparcFaultBase::FaultVals
122    SparcFault<FpExceptionOther>::vals =
123{"fp_exception_other", 0x022, 1110, {P, P, H}, FaultStat()};
124
125template<> SparcFaultBase::FaultVals
126    SparcFault<TagOverflow>::vals =
127{"tag_overflow", 0x023, 1400, {P, P, H}, FaultStat()};
128
129template<> SparcFaultBase::FaultVals
130    SparcFault<CleanWindow>::vals =
131{"clean_window", 0x024, 1010, {P, P, H}, FaultStat()};
132
133template<> SparcFaultBase::FaultVals
134    SparcFault<DivisionByZero>::vals =
135{"division_by_zero", 0x028, 1500, {P, P, H}, FaultStat()};
136
137template<> SparcFaultBase::FaultVals
138    SparcFault<InternalProcessorError>::vals =
139{"internal_processor_error", 0x029, 4, {H, H, H}, FaultStat()};
140
141template<> SparcFaultBase::FaultVals
142    SparcFault<InstructionInvalidTSBEntry>::vals =
143{"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}, FaultStat()};
144
145template<> SparcFaultBase::FaultVals
146    SparcFault<DataInvalidTSBEntry>::vals =
147{"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}, FaultStat()};
148
149template<> SparcFaultBase::FaultVals
150    SparcFault<DataAccessException>::vals =
151{"data_access_exception", 0x030, 1201, {H, H, H}, FaultStat()};
152
153//XXX This trap is apparently dropped from ua2005
154/*template<> SparcFaultBase::FaultVals
155    SparcFault<DataAccessMMUMiss>::vals =
156    {"data_mmu", 0x031, 12, {H, H, H}};*/
157
158template<> SparcFaultBase::FaultVals
159    SparcFault<DataAccessError>::vals =
160{"data_access_error", 0x032, 1210, {H, H, H}, FaultStat()};
161
162template<> SparcFaultBase::FaultVals
163    SparcFault<DataAccessProtection>::vals =
164{"data_access_protection", 0x033, 1207, {H, H, H}, FaultStat()};
165
166template<> SparcFaultBase::FaultVals
167    SparcFault<MemAddressNotAligned>::vals =
168{"mem_address_not_aligned", 0x034, 1020, {H, H, H}, FaultStat()};
169
170template<> SparcFaultBase::FaultVals
171    SparcFault<LDDFMemAddressNotAligned>::vals =
172{"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}, FaultStat()};
173
174template<> SparcFaultBase::FaultVals
175    SparcFault<STDFMemAddressNotAligned>::vals =
176{"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}, FaultStat()};
177
178template<> SparcFaultBase::FaultVals
179    SparcFault<PrivilegedAction>::vals =
180{"privileged_action", 0x037, 1110, {H, H, SH}, FaultStat()};
181
182template<> SparcFaultBase::FaultVals
183    SparcFault<LDQFMemAddressNotAligned>::vals =
184{"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}, FaultStat()};
185
186template<> SparcFaultBase::FaultVals
187    SparcFault<STQFMemAddressNotAligned>::vals =
188{"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}, FaultStat()};
189
190template<> SparcFaultBase::FaultVals
191    SparcFault<InstructionRealTranslationMiss>::vals =
192{"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}, FaultStat()};
193
194template<> SparcFaultBase::FaultVals
195    SparcFault<DataRealTranslationMiss>::vals =
196{"data_real_translation_miss", 0x03F, 1203, {H, H, H}, FaultStat()};
197
198//XXX This trap is apparently dropped from ua2005
199/*template<> SparcFaultBase::FaultVals
200    SparcFault<AsyncDataError>::vals =
201    {"async_data", 0x040, 2, {H, H, H}};*/
202
203template<> SparcFaultBase::FaultVals
204    SparcFault<InterruptLevelN>::vals =
205{"interrupt_level_n", 0x040, 0, {P, P, SH}, FaultStat()};
206
207template<> SparcFaultBase::FaultVals
208    SparcFault<HstickMatch>::vals =
209{"hstick_match", 0x05E, 1601, {H, H, H}, FaultStat()};
210
211template<> SparcFaultBase::FaultVals
212    SparcFault<TrapLevelZero>::vals =
213{"trap_level_zero", 0x05F, 202, {H, H, SH}, FaultStat()};
214
215template<> SparcFaultBase::FaultVals
216    SparcFault<InterruptVector>::vals =
217{"interrupt_vector", 0x060, 2630, {H, H, H}, FaultStat()};
218
219template<> SparcFaultBase::FaultVals
220    SparcFault<PAWatchpoint>::vals =
221{"PA_watchpoint", 0x061, 1209, {H, H, H}, FaultStat()};
222
223template<> SparcFaultBase::FaultVals
224    SparcFault<VAWatchpoint>::vals =
225{"VA_watchpoint", 0x062, 1120, {P, P, SH}, FaultStat()};
226
227template<> SparcFaultBase::FaultVals
228    SparcFault<FastInstructionAccessMMUMiss>::vals =
229{"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}, FaultStat()};
230
231template<> SparcFaultBase::FaultVals
232    SparcFault<FastDataAccessMMUMiss>::vals =
233{"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}, FaultStat()};
234
235template<> SparcFaultBase::FaultVals
236    SparcFault<FastDataAccessProtection>::vals =
237{"fast_data_access_protection", 0x06C, 1207, {H, H, H}, FaultStat()};
238
239template<> SparcFaultBase::FaultVals
240    SparcFault<InstructionBreakpoint>::vals =
241{"instruction_break", 0x076, 610, {H, H, H}, FaultStat()};
242
243template<> SparcFaultBase::FaultVals
244    SparcFault<CpuMondo>::vals =
245{"cpu_mondo", 0x07C, 1608, {P, P, SH}, FaultStat()};
246
247template<> SparcFaultBase::FaultVals
248    SparcFault<DevMondo>::vals =
249{"dev_mondo", 0x07D, 1611, {P, P, SH}, FaultStat()};
250
251template<> SparcFaultBase::FaultVals
252    SparcFault<ResumableError>::vals =
253{"resume_error", 0x07E, 3330, {P, P, SH}, FaultStat()};
254
255template<> SparcFaultBase::FaultVals
256    SparcFault<SpillNNormal>::vals =
257{"spill_n_normal", 0x080, 900, {P, P, H}, FaultStat()};
258
259template<> SparcFaultBase::FaultVals
260    SparcFault<SpillNOther>::vals =
261{"spill_n_other", 0x0A0, 900, {P, P, H}, FaultStat()};
262
263template<> SparcFaultBase::FaultVals
264    SparcFault<FillNNormal>::vals =
265{"fill_n_normal", 0x0C0, 900, {P, P, H}, FaultStat()};
266
267template<> SparcFaultBase::FaultVals
268    SparcFault<FillNOther>::vals =
269{"fill_n_other", 0x0E0, 900, {P, P, H}, FaultStat()};
270
271template<> SparcFaultBase::FaultVals
272    SparcFault<TrapInstruction>::vals =
273{"trap_instruction", 0x100, 1602, {P, P, H}, FaultStat()};
274
275/**
276 * This causes the thread context to enter RED state. This causes the side
277 * effects which go with entering RED state because of a trap.
278 */
279
280void
281enterREDState(ThreadContext *tc)
282{
283    //@todo Disable the mmu?
284    //@todo Disable watchpoints?
285    HPSTATE hpstate= tc->readMiscRegNoEffect(MISCREG_HPSTATE);
286    hpstate.red = 1;
287    hpstate.hpriv = 1;
288    tc->setMiscReg(MISCREG_HPSTATE, hpstate);
289    // PSTATE.priv is set to 1 here. The manual says it should be 0, but
290    // Legion sets it to 1.
291    PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
292    pstate.priv = 1;
293    tc->setMiscReg(MISCREG_PSTATE, pstate);
294}
295
296/**
297 * This sets everything up for a RED state trap except for actually jumping to
298 * the handler.
299 */
300
301void
302doREDFault(ThreadContext *tc, TrapType tt)
303{
304    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
305    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
306    PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
307    HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
308    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
309    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
310    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
311    MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
312    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
313    PCState pc = tc->pcState();
314
315    TL++;
316
317    Addr pcMask = pstate.am ? mask(32) : mask(64);
318
319    // set TSTATE.gl to gl
320    replaceBits(TSTATE, 42, 40, GL);
321    // set TSTATE.ccr to ccr
322    replaceBits(TSTATE, 39, 32, CCR);
323    // set TSTATE.asi to asi
324    replaceBits(TSTATE, 31, 24, ASI);
325    // set TSTATE.pstate to pstate
326    replaceBits(TSTATE, 20, 8, pstate);
327    // set TSTATE.cwp to cwp
328    replaceBits(TSTATE, 4, 0, CWP);
329
330    // Write back TSTATE
331    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
332
333    // set TPC to PC
334    tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
335    // set TNPC to NPC
336    tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
337
338    // set HTSTATE.hpstate to hpstate
339    tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
340
341    // TT = trap type;
342    tc->setMiscRegNoEffect(MISCREG_TT, tt);
343
344    // Update GL
345    tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
346
347    bool priv = pstate.priv; // just save the priv bit
348    pstate = 0;
349    pstate.priv = priv;
350    pstate.pef = 1;
351    tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
352
353    hpstate.red = 1;
354    hpstate.hpriv = 1;
355    hpstate.ibe = 0;
356    hpstate.tlz = 0;
357    tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
358
359    bool changedCWP = true;
360    if (tt == 0x24)
361        CWP++;
362    else if (0x80 <= tt && tt <= 0xbf)
363        CWP += (CANSAVE + 2);
364    else if (0xc0 <= tt && tt <= 0xff)
365        CWP--;
366    else
367        changedCWP = false;
368
369    if (changedCWP) {
370        CWP = (CWP + NWindows) % NWindows;
371        tc->setMiscReg(MISCREG_CWP, CWP);
372    }
373}
374
375/**
376 * This sets everything up for a normal trap except for actually jumping to
377 * the handler.
378 */
379
380void
381doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
382{
383    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
384    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
385    PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
386    HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
387    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
388    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
389    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
390    MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
391    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
392    PCState pc = tc->pcState();
393
394    // Increment the trap level
395    TL++;
396    tc->setMiscRegNoEffect(MISCREG_TL, TL);
397
398    Addr pcMask = pstate.am ? mask(32) : mask(64);
399
400    // Save off state
401
402    // set TSTATE.gl to gl
403    replaceBits(TSTATE, 42, 40, GL);
404    // set TSTATE.ccr to ccr
405    replaceBits(TSTATE, 39, 32, CCR);
406    // set TSTATE.asi to asi
407    replaceBits(TSTATE, 31, 24, ASI);
408    // set TSTATE.pstate to pstate
409    replaceBits(TSTATE, 20, 8, pstate);
410    // set TSTATE.cwp to cwp
411    replaceBits(TSTATE, 4, 0, CWP);
412
413    // Write back TSTATE
414    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
415
416    // set TPC to PC
417    tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
418    // set TNPC to NPC
419    tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
420
421    // set HTSTATE.hpstate to hpstate
422    tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
423
424    // TT = trap type;
425    tc->setMiscRegNoEffect(MISCREG_TT, tt);
426
427    // Update the global register level
428    if (!gotoHpriv)
429        tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxPGL));
430    else
431        tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL));
432
433    // pstate.mm is unchanged
434    pstate.pef = 1; // PSTATE.pef = whether or not an fpu is present
435    pstate.am = 0;
436    pstate.ie = 0;
437    // pstate.tle is unchanged
438    // pstate.tct = 0
439
440    if (gotoHpriv) {
441        pstate.cle = 0;
442        // The manual says PSTATE.priv should be 0, but Legion leaves it alone
443        hpstate.red = 0;
444        hpstate.hpriv = 1;
445        hpstate.ibe = 0;
446        // hpstate.tlz is unchanged
447        tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
448    } else { // we are going to priv
449        pstate.priv = 1;
450        pstate.cle = pstate.tle;
451    }
452    tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
453
454
455    bool changedCWP = true;
456    if (tt == 0x24)
457        CWP++;
458    else if (0x80 <= tt && tt <= 0xbf)
459        CWP += (CANSAVE + 2);
460    else if (0xc0 <= tt && tt <= 0xff)
461        CWP--;
462    else
463        changedCWP = false;
464
465    if (changedCWP) {
466        CWP = (CWP + NWindows) % NWindows;
467        tc->setMiscReg(MISCREG_CWP, CWP);
468    }
469}
470
471void
472getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
473{
474    //XXX The following constant might belong in a header file.
475    const Addr RSTVAddr = 0xFFF0000000ULL;
476    PC = RSTVAddr | ((TT << 5) & 0xFF);
477    NPC = PC + sizeof(MachInst);
478}
479
480void
481getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT)
482{
483    Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
484    PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
485    NPC = PC + sizeof(MachInst);
486}
487
488void
489getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
490{
491    Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
492    PC = (TBA & ~mask(15)) |
493        (TL > 1 ? (1 << 14) : 0) |
494        ((TT << 5) & mask(14));
495    NPC = PC + sizeof(MachInst);
496}
497
498void
499SparcFaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
500{
501    FaultBase::invoke(tc);
502    if (!FullSystem)
503        return;
504
505    countStat()++;
506
507    // We can refer to this to see what the trap level -was-, but something
508    // in the middle could change it in the regfile out from under us.
509    MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
510    MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
511    PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
512    HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
513
514    Addr PC, NPC;
515
516    PrivilegeLevel current;
517    if (hpstate.hpriv)
518        current = Hyperprivileged;
519    else if (pstate.priv)
520        current = Privileged;
521    else
522        current = User;
523
524    PrivilegeLevel level = getNextLevel(current);
525
526    if (hpstate.red || (tl == MaxTL - 1)) {
527        getREDVector(5, PC, NPC);
528        doREDFault(tc, tt);
529        // This changes the hpstate and pstate, so we need to make sure we
530        // save the old version on the trap stack in doREDFault.
531        enterREDState(tc);
532    } else if (tl == MaxTL) {
533        panic("Should go to error state here.. crap\n");
534        // Do error_state somehow?
535        // Probably inject a WDR fault using the interrupt mechanism.
536        // What should the PC and NPC be set to?
537    } else if (tl > MaxPTL && level == Privileged) {
538        // guest_watchdog fault
539        doNormalFault(tc, trapType(), true);
540        getHyperVector(tc, PC, NPC, 2);
541    } else if (level == Hyperprivileged ||
542               (level == Privileged && trapType() >= 384)) {
543        doNormalFault(tc, trapType(), true);
544        getHyperVector(tc, PC, NPC, trapType());
545    } else {
546        doNormalFault(tc, trapType(), false);
547        getPrivVector(tc, PC, NPC, trapType(), tl + 1);
548    }
549
550    PCState pc;
551    pc.pc(PC);
552    pc.npc(NPC);
553    pc.nnpc(NPC + sizeof(MachInst));
554    pc.upc(0);
555    pc.nupc(1);
556    tc->pcState(pc);
557}
558
559void
560PowerOnReset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
561{
562    // For SPARC, when a system is first started, there is a power
563    // on reset Trap which sets the processor into the following state.
564    // Bits that aren't set aren't defined on startup.
565
566    tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
567    tc->setMiscRegNoEffect(MISCREG_TT, trapType());
568    tc->setMiscReg(MISCREG_GL, MaxGL);
569
570    PSTATE pstate = 0;
571    pstate.pef = 1;
572    pstate.priv = 1;
573    tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
574
575    // Turn on red and hpriv, set everything else to 0
576    HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
577    hpstate.red = 1;
578    hpstate.hpriv = 1;
579    hpstate.ibe = 0;
580    hpstate.tlz = 0;
581    tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
582
583    // The tick register is unreadable by nonprivileged software
584    tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
585
586    // Enter RED state. We do this last so that the actual state preserved in
587    // the trap stack is the state from before this fault.
588    enterREDState(tc);
589
590    Addr PC, NPC;
591    getREDVector(trapType(), PC, NPC);
592
593    PCState pc;
594    pc.pc(PC);
595    pc.npc(NPC);
596    pc.nnpc(NPC + sizeof(MachInst));
597    pc.upc(0);
598    pc.nupc(1);
599    tc->pcState(pc);
600
601    // These registers are specified as "undefined" after a POR, and they
602    // should have reasonable values after the miscregfile is reset
603    /*
604    // Clear all the soft interrupt bits
605    softint = 0;
606    // disable timer compare interrupts, reset tick_cmpr
607    tc->setMiscRegNoEffect(MISCREG_
608    tick_cmprFields.int_dis = 1;
609    tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
610    stickFields.npt = 1; // The TICK register is unreadable by by !priv
611    stick_cmprFields.int_dis = 1; // disable timer compare interrupts
612    stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
613
614    tt[tl] = _trapType;
615
616    hintp = 0; // no interrupts pending
617    hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
618    hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
619    */
620}
621
622void
623FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
624                                     const StaticInstPtr &inst)
625{
626    if (FullSystem) {
627        SparcFaultBase::invoke(tc, inst);
628        return;
629    }
630
631    Process *p = tc->getProcessPtr();
632    TlbEntry *entry = p->pTable->lookup(vaddr);
633    panic_if(!entry, "Tried to execute unmapped address %#x.\n", vaddr);
634
635    Addr alignedvaddr = p->pTable->pageAlign(vaddr);
636
637    // Grab fields used during instruction translation to figure out
638    // which context to use.
639    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
640
641    // Inside a VM, a real address is the address that guest OS would
642    // interpret to be a physical address. To map to the physical address,
643    // it still needs to undergo a translation. The instruction
644    // translation code in the SPARC ITLB code assumes that the context is
645    // zero (kernel-level) if real addressing is being used.
646    bool is_real_address = !bits(tlbdata, 4);
647
648    // The SPARC ITLB code assumes that traps are executed in context
649    // zero so we carry that assumption through here.
650    bool trapped = bits(tlbdata, 18, 16) > 0;
651
652    // The primary context acts as a PASID. It allows the MMU to
653    // distinguish between virtual addresses that would alias to the
654    // same physical address (if two or more processes shared the same
655    // virtual address mapping).
656    int primary_context = bits(tlbdata, 47, 32);
657
658    // The partition id distinguishes between virtualized environments.
659    int const partition_id = 0;
660
661    // Given the assumptions in the translateInst code in the SPARC ITLB,
662    // the logic works out to the following for the context.
663    int context_id = (is_real_address || trapped) ? 0 : primary_context;
664
665    // Insert the TLB entry.
666    // The entry specifying whether the address is "real" is set to
667    // false for syscall emulation mode regardless of whether the
668    // address is real in preceding code. Not sure sure that this is
669    // correct, but also not sure if it matters at all.
670    dynamic_cast<TLB *>(tc->getITBPtr())->
671        insert(alignedvaddr, partition_id, context_id, false, entry->pte);
672}
673
674void
675FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
676{
677    if (FullSystem) {
678        SparcFaultBase::invoke(tc, inst);
679        return;
680    }
681
682    Process *p = tc->getProcessPtr();
683    TlbEntry *entry = p->pTable->lookup(vaddr);
684    if (!entry && p->fixupStackFault(vaddr))
685        entry = p->pTable->lookup(vaddr);
686    panic_if(!entry, "Tried to access unmapped address %#x.\n", vaddr);
687
688    Addr alignedvaddr = p->pTable->pageAlign(vaddr);
689
690    // Grab fields used during data translation to figure out
691    // which context to use.
692    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
693
694    // The primary context acts as a PASID. It allows the MMU to
695    // distinguish between virtual addresses that would alias to the
696    // same physical address (if two or more processes shared the same
697    // virtual address mapping). There's a secondary context used in the
698    // DTLB translation code, but it should __probably__ be zero for
699    // syscall emulation code. (The secondary context is used by Solaris
700    // to allow kernel privilege code to access user space code:
701    // [ISBN 0-13-022496-0]:PG199.)
702    int primary_context = bits(tlbdata, 47, 32);
703
704    // "Hyper-Privileged Mode" is in use. There are three main modes of
705    // operation for Sparc: Hyper-Privileged Mode, Privileged Mode, and
706    // User Mode.
707    int hpriv = bits(tlbdata, 0);
708
709    // Reset, Error and Debug state is in use. Something horrible has
710    // happened or the system is operating in Reset Mode.
711    int red = bits(tlbdata, 1);
712
713    // Inside a VM, a real address is the address that guest OS would
714    // interpret to be a physical address. To map to the physical address,
715    // it still needs to undergo a translation. The instruction
716    // translation code in the SPARC ITLB code assumes that the context is
717    // zero (kernel-level) if real addressing is being used.
718    int is_real_address = !bits(tlbdata, 5);
719
720    // Grab the address space identifier register from the thread context.
721    // XXX: Inspecting how setMiscReg and setMiscRegNoEffect behave for
722    // MISCREG_ASI causes me to think that the ASI register implementation
723    // might be bugged. The NoEffect variant changes the ASI register
724    // value in the architectural state while the normal variant changes
725    // the context field in the thread context's currently decoded request
726    // but does not directly affect the ASI register value in the
727    // architectural state. The ASI values and the context field in the
728    // request packet seem to have completely different uses.
729    MiscReg reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI);
730    ASI asi = static_cast<ASI>(reg_asi);
731
732    // The SPARC DTLB code assumes that traps are executed in context
733    // zero if the asi value is ASI_IMPLICIT (which is 0x0). There's also
734    // an assumption that the nucleus address space is being used, but
735    // the context is the relevant issue since we need to pass it to TLB.
736    bool trapped = bits(tlbdata, 18, 16) > 0;
737
738    // Given the assumptions in the translateData code in the SPARC DTLB,
739    // the logic works out to the following for the context.
740    int context_id = ((!hpriv && !red && is_real_address) ||
741                      asiIsReal(asi) ||
742                      (trapped && asi == ASI_IMPLICIT))
743                     ? 0 : primary_context;
744
745    // The partition id distinguishes between virtualized environments.
746    int const partition_id = 0;
747
748    // Insert the TLB entry.
749    // The entry specifying whether the address is "real" is set to
750    // false for syscall emulation mode regardless of whether the
751    // address is real in preceding code. Not sure sure that this is
752    // correct, but also not sure if it matters at all.
753    dynamic_cast<TLB *>(tc->getDTBPtr())->
754        insert(alignedvaddr, partition_id, context_id, false, entry->pte);
755}
756
757void
758SpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
759{
760    if (FullSystem) {
761        SparcFaultBase::invoke(tc, inst);
762        return;
763    }
764
765    doNormalFault(tc, trapType(), false);
766
767    Process *p = tc->getProcessPtr();
768
769    SparcProcess *sp = dynamic_cast<SparcProcess *>(p);
770    assert(sp);
771
772    // Then adjust the PC and NPC
773    tc->pcState(sp->readSpillStart());
774}
775
776void
777FillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
778{
779    if (FullSystem) {
780        SparcFaultBase::invoke(tc, inst);
781        return;
782    }
783
784    doNormalFault(tc, trapType(), false);
785
786    Process *p = tc->getProcessPtr();
787
788    SparcProcess *sp = dynamic_cast<SparcProcess *>(p);
789    assert(sp);
790
791    // Then adjust the PC and NPC
792    tc->pcState(sp->readFillStart());
793}
794
795void
796TrapInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
797{
798    if (FullSystem) {
799        SparcFaultBase::invoke(tc, inst);
800        return;
801    }
802
803    // In SE, this mechanism is how the process requests a service from
804    // the operating system. We'll get the process object from the thread
805    // context and let it service the request.
806
807    Process *p = tc->getProcessPtr();
808
809    SparcProcess *sp = dynamic_cast<SparcProcess *>(p);
810    assert(sp);
811
812    Fault fault;
813    sp->handleTrap(_n, tc, &fault);
814
815    // We need to explicitly advance the pc, since that's not done for us
816    // on a faulting instruction
817    PCState pc = tc->pcState();
818    pc.advance();
819    tc->pcState(pc);
820}
821
822} // namespace SparcISA
823
824