faults.cc revision 7720
12221SN/A/* 22221SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32221SN/A * All rights reserved. 42221SN/A * 52221SN/A * Redistribution and use in source and binary forms, with or without 62221SN/A * modification, are permitted provided that the following conditions are 72221SN/A * met: redistributions of source code must retain the above copyright 82221SN/A * notice, this list of conditions and the following disclaimer; 92221SN/A * redistributions in binary form must reproduce the above copyright 102221SN/A * notice, this list of conditions and the following disclaimer in the 112221SN/A * documentation and/or other materials provided with the distribution; 122221SN/A * neither the name of the copyright holders nor the names of its 132221SN/A * contributors may be used to endorse or promote products derived from 142221SN/A * this software without specific prior written permission. 152221SN/A * 162221SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172221SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182221SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192221SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202221SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212221SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222221SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232221SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242221SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252221SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262221SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Kevin Lim 302221SN/A */ 312221SN/A 323415Sgblack@eecs.umich.edu#include <algorithm> 333415Sgblack@eecs.umich.edu 342223SN/A#include "arch/sparc/faults.hh" 353415Sgblack@eecs.umich.edu#include "arch/sparc/isa_traits.hh" 363578Sgblack@eecs.umich.edu#include "arch/sparc/types.hh" 373415Sgblack@eecs.umich.edu#include "base/bitfield.hh" 383415Sgblack@eecs.umich.edu#include "base/trace.hh" 393523Sgblack@eecs.umich.edu#include "config/full_system.hh" 403415Sgblack@eecs.umich.edu#include "cpu/base.hh" 412680Sktlim@umich.edu#include "cpu/thread_context.hh" 422800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM 433523Sgblack@eecs.umich.edu#include "arch/sparc/process.hh" 443415Sgblack@eecs.umich.edu#include "mem/page_table.hh" 452800Ssaidi@eecs.umich.edu#include "sim/process.hh" 462800Ssaidi@eecs.umich.edu#endif 472221SN/A 483415Sgblack@eecs.umich.eduusing namespace std; 493415Sgblack@eecs.umich.edu 502223SN/Anamespace SparcISA 512221SN/A{ 522221SN/A 533573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 543576Sgblack@eecs.umich.edu SparcFault<PowerOnReset>::vals = 553576Sgblack@eecs.umich.edu {"power_on_reset", 0x001, 0, {H, H, H}}; 562221SN/A 573573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 583576Sgblack@eecs.umich.edu SparcFault<WatchDogReset>::vals = 593576Sgblack@eecs.umich.edu {"watch_dog_reset", 0x002, 120, {H, H, H}}; 602221SN/A 613573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 623576Sgblack@eecs.umich.edu SparcFault<ExternallyInitiatedReset>::vals = 633576Sgblack@eecs.umich.edu {"externally_initiated_reset", 0x003, 110, {H, H, H}}; 642221SN/A 653573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 663576Sgblack@eecs.umich.edu SparcFault<SoftwareInitiatedReset>::vals = 673576Sgblack@eecs.umich.edu {"software_initiated_reset", 0x004, 130, {SH, SH, H}}; 682221SN/A 693573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 703576Sgblack@eecs.umich.edu SparcFault<REDStateException>::vals = 713576Sgblack@eecs.umich.edu {"RED_state_exception", 0x005, 1, {H, H, H}}; 722221SN/A 733573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 743576Sgblack@eecs.umich.edu SparcFault<StoreError>::vals = 753576Sgblack@eecs.umich.edu {"store_error", 0x007, 201, {H, H, H}}; 762221SN/A 773573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 783576Sgblack@eecs.umich.edu SparcFault<InstructionAccessException>::vals = 793576Sgblack@eecs.umich.edu {"instruction_access_exception", 0x008, 300, {H, H, H}}; 803576Sgblack@eecs.umich.edu 813576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005 823576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals 833576Sgblack@eecs.umich.edu SparcFault<InstructionAccessMMUMiss>::vals = 843576Sgblack@eecs.umich.edu {"inst_mmu", 0x009, 2, {H, H, H}};*/ 852221SN/A 863573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 873576Sgblack@eecs.umich.edu SparcFault<InstructionAccessError>::vals = 883576Sgblack@eecs.umich.edu {"instruction_access_error", 0x00A, 400, {H, H, H}}; 892221SN/A 903573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 913576Sgblack@eecs.umich.edu SparcFault<IllegalInstruction>::vals = 923576Sgblack@eecs.umich.edu {"illegal_instruction", 0x010, 620, {H, H, H}}; 932221SN/A 943573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 953576Sgblack@eecs.umich.edu SparcFault<PrivilegedOpcode>::vals = 963576Sgblack@eecs.umich.edu {"privileged_opcode", 0x011, 700, {P, SH, SH}}; 973576Sgblack@eecs.umich.edu 983576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005 993576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals 1003576Sgblack@eecs.umich.edu SparcFault<UnimplementedLDD>::vals = 1013576Sgblack@eecs.umich.edu {"unimp_ldd", 0x012, 6, {H, H, H}};*/ 1023576Sgblack@eecs.umich.edu 1033576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005 1043576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals 1053576Sgblack@eecs.umich.edu SparcFault<UnimplementedSTD>::vals = 1063576Sgblack@eecs.umich.edu {"unimp_std", 0x013, 6, {H, H, H}};*/ 1072221SN/A 1083573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1093576Sgblack@eecs.umich.edu SparcFault<FpDisabled>::vals = 1103576Sgblack@eecs.umich.edu {"fp_disabled", 0x020, 800, {P, P, H}}; 1112221SN/A 1123573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1133576Sgblack@eecs.umich.edu SparcFault<FpExceptionIEEE754>::vals = 1143576Sgblack@eecs.umich.edu {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}}; 1152221SN/A 1163573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1173576Sgblack@eecs.umich.edu SparcFault<FpExceptionOther>::vals = 1183576Sgblack@eecs.umich.edu {"fp_exception_other", 0x022, 1110, {P, P, H}}; 1192221SN/A 1203573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1213576Sgblack@eecs.umich.edu SparcFault<TagOverflow>::vals = 1223576Sgblack@eecs.umich.edu {"tag_overflow", 0x023, 1400, {P, P, H}}; 1232221SN/A 1243573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1253576Sgblack@eecs.umich.edu SparcFault<CleanWindow>::vals = 1263576Sgblack@eecs.umich.edu {"clean_window", 0x024, 1010, {P, P, H}}; 1272221SN/A 1283573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1293576Sgblack@eecs.umich.edu SparcFault<DivisionByZero>::vals = 1303576Sgblack@eecs.umich.edu {"division_by_zero", 0x028, 1500, {P, P, H}}; 1312223SN/A 1323573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1333576Sgblack@eecs.umich.edu SparcFault<InternalProcessorError>::vals = 1343576Sgblack@eecs.umich.edu {"internal_processor_error", 0x029, 4, {H, H, H}}; 1352223SN/A 1363573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1373576Sgblack@eecs.umich.edu SparcFault<InstructionInvalidTSBEntry>::vals = 1383576Sgblack@eecs.umich.edu {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}}; 1392223SN/A 1403573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1413576Sgblack@eecs.umich.edu SparcFault<DataInvalidTSBEntry>::vals = 1423576Sgblack@eecs.umich.edu {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}}; 1432223SN/A 1443573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1453576Sgblack@eecs.umich.edu SparcFault<DataAccessException>::vals = 1463576Sgblack@eecs.umich.edu {"data_access_exception", 0x030, 1201, {H, H, H}}; 1473576Sgblack@eecs.umich.edu 1483576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005 1493576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals 1503576Sgblack@eecs.umich.edu SparcFault<DataAccessMMUMiss>::vals = 1513576Sgblack@eecs.umich.edu {"data_mmu", 0x031, 12, {H, H, H}};*/ 1522223SN/A 1533573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1543576Sgblack@eecs.umich.edu SparcFault<DataAccessError>::vals = 1553576Sgblack@eecs.umich.edu {"data_access_error", 0x032, 1210, {H, H, H}}; 1562223SN/A 1573573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1583576Sgblack@eecs.umich.edu SparcFault<DataAccessProtection>::vals = 1593576Sgblack@eecs.umich.edu {"data_access_protection", 0x033, 1207, {H, H, H}}; 1602223SN/A 1613573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1623576Sgblack@eecs.umich.edu SparcFault<MemAddressNotAligned>::vals = 1633576Sgblack@eecs.umich.edu {"mem_address_not_aligned", 0x034, 1020, {H, H, H}}; 1642223SN/A 1653573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1663576Sgblack@eecs.umich.edu SparcFault<LDDFMemAddressNotAligned>::vals = 1673576Sgblack@eecs.umich.edu {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}}; 1682223SN/A 1693573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1703576Sgblack@eecs.umich.edu SparcFault<STDFMemAddressNotAligned>::vals = 1713576Sgblack@eecs.umich.edu {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}}; 1722223SN/A 1733573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1743576Sgblack@eecs.umich.edu SparcFault<PrivilegedAction>::vals = 1753576Sgblack@eecs.umich.edu {"privileged_action", 0x037, 1110, {H, H, SH}}; 1762223SN/A 1773573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1783576Sgblack@eecs.umich.edu SparcFault<LDQFMemAddressNotAligned>::vals = 1793576Sgblack@eecs.umich.edu {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}}; 1802223SN/A 1813573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1823576Sgblack@eecs.umich.edu SparcFault<STQFMemAddressNotAligned>::vals = 1833576Sgblack@eecs.umich.edu {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}}; 1842223SN/A 1853573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1863576Sgblack@eecs.umich.edu SparcFault<InstructionRealTranslationMiss>::vals = 1873576Sgblack@eecs.umich.edu {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}}; 1882223SN/A 1893573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1903576Sgblack@eecs.umich.edu SparcFault<DataRealTranslationMiss>::vals = 1913576Sgblack@eecs.umich.edu {"data_real_translation_miss", 0x03F, 1203, {H, H, H}}; 1922223SN/A 1933576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005 1943576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals 1953576Sgblack@eecs.umich.edu SparcFault<AsyncDataError>::vals = 1963576Sgblack@eecs.umich.edu {"async_data", 0x040, 2, {H, H, H}};*/ 1972527SN/A 1983573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1993576Sgblack@eecs.umich.edu SparcFault<InterruptLevelN>::vals = 2003890Ssaidi@eecs.umich.edu {"interrupt_level_n", 0x040, 0, {P, P, SH}}; 2012223SN/A 2023573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2033576Sgblack@eecs.umich.edu SparcFault<HstickMatch>::vals = 2043576Sgblack@eecs.umich.edu {"hstick_match", 0x05E, 1601, {H, H, H}}; 2052223SN/A 2063573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2073576Sgblack@eecs.umich.edu SparcFault<TrapLevelZero>::vals = 2083576Sgblack@eecs.umich.edu {"trap_level_zero", 0x05F, 202, {H, H, SH}}; 2092223SN/A 2103573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2114103Ssaidi@eecs.umich.edu SparcFault<InterruptVector>::vals = 2124103Ssaidi@eecs.umich.edu {"interrupt_vector", 0x060, 2630, {H, H, H}}; 2134103Ssaidi@eecs.umich.edu 2144103Ssaidi@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2153576Sgblack@eecs.umich.edu SparcFault<PAWatchpoint>::vals = 2163576Sgblack@eecs.umich.edu {"PA_watchpoint", 0x061, 1209, {H, H, H}}; 2172223SN/A 2183573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2193576Sgblack@eecs.umich.edu SparcFault<VAWatchpoint>::vals = 2203576Sgblack@eecs.umich.edu {"VA_watchpoint", 0x062, 1120, {P, P, SH}}; 2212223SN/A 2223573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2233576Sgblack@eecs.umich.edu SparcFault<FastInstructionAccessMMUMiss>::vals = 2243576Sgblack@eecs.umich.edu {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}}; 2253576Sgblack@eecs.umich.edu 2263576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2273576Sgblack@eecs.umich.edu SparcFault<FastDataAccessMMUMiss>::vals = 2283576Sgblack@eecs.umich.edu {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}}; 2293576Sgblack@eecs.umich.edu 2303576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2313576Sgblack@eecs.umich.edu SparcFault<FastDataAccessProtection>::vals = 2323576Sgblack@eecs.umich.edu {"fast_data_access_protection", 0x06C, 1207, {H, H, H}}; 2333576Sgblack@eecs.umich.edu 2343576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2353576Sgblack@eecs.umich.edu SparcFault<InstructionBreakpoint>::vals = 2363576Sgblack@eecs.umich.edu {"instruction_break", 0x076, 610, {H, H, H}}; 2373576Sgblack@eecs.umich.edu 2383576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2393576Sgblack@eecs.umich.edu SparcFault<CpuMondo>::vals = 2403576Sgblack@eecs.umich.edu {"cpu_mondo", 0x07C, 1608, {P, P, SH}}; 2413576Sgblack@eecs.umich.edu 2423576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2433576Sgblack@eecs.umich.edu SparcFault<DevMondo>::vals = 2443576Sgblack@eecs.umich.edu {"dev_mondo", 0x07D, 1611, {P, P, SH}}; 2453576Sgblack@eecs.umich.edu 2463576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2473893Shsul@eecs.umich.edu SparcFault<ResumableError>::vals = 2483576Sgblack@eecs.umich.edu {"resume_error", 0x07E, 3330, {P, P, SH}}; 2493576Sgblack@eecs.umich.edu 2503576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2513576Sgblack@eecs.umich.edu SparcFault<SpillNNormal>::vals = 2523576Sgblack@eecs.umich.edu {"spill_n_normal", 0x080, 900, {P, P, H}}; 2533576Sgblack@eecs.umich.edu 2543576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2553576Sgblack@eecs.umich.edu SparcFault<SpillNOther>::vals = 2563576Sgblack@eecs.umich.edu {"spill_n_other", 0x0A0, 900, {P, P, H}}; 2573576Sgblack@eecs.umich.edu 2583576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2593576Sgblack@eecs.umich.edu SparcFault<FillNNormal>::vals = 2603576Sgblack@eecs.umich.edu {"fill_n_normal", 0x0C0, 900, {P, P, H}}; 2613576Sgblack@eecs.umich.edu 2623576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2633576Sgblack@eecs.umich.edu SparcFault<FillNOther>::vals = 2643576Sgblack@eecs.umich.edu {"fill_n_other", 0x0E0, 900, {P, P, H}}; 2653576Sgblack@eecs.umich.edu 2663576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2673576Sgblack@eecs.umich.edu SparcFault<TrapInstruction>::vals = 2683576Sgblack@eecs.umich.edu {"trap_instruction", 0x100, 1602, {P, P, H}}; 2692223SN/A 2703415Sgblack@eecs.umich.edu/** 2713578Sgblack@eecs.umich.edu * This causes the thread context to enter RED state. This causes the side 2723578Sgblack@eecs.umich.edu * effects which go with entering RED state because of a trap. 2733415Sgblack@eecs.umich.edu */ 2743415Sgblack@eecs.umich.edu 2753578Sgblack@eecs.umich.eduvoid enterREDState(ThreadContext *tc) 2763415Sgblack@eecs.umich.edu{ 2773578Sgblack@eecs.umich.edu //@todo Disable the mmu? 2783578Sgblack@eecs.umich.edu //@todo Disable watchpoints? 2794172Ssaidi@eecs.umich.edu MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 2803578Sgblack@eecs.umich.edu //HPSTATE.red = 1 2813578Sgblack@eecs.umich.edu HPSTATE |= (1 << 5); 2823578Sgblack@eecs.umich.edu //HPSTATE.hpriv = 1 2833578Sgblack@eecs.umich.edu HPSTATE |= (1 << 2); 2844172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); 2853746Sgblack@eecs.umich.edu //PSTATE.priv is set to 1 here. The manual says it should be 0, but 2863746Sgblack@eecs.umich.edu //Legion sets it to 1. 2874172Ssaidi@eecs.umich.edu MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE); 2883746Sgblack@eecs.umich.edu PSTATE |= (1 << 2); 2894172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_PSTATE, PSTATE); 2903578Sgblack@eecs.umich.edu} 2913578Sgblack@eecs.umich.edu 2923578Sgblack@eecs.umich.edu/** 2933578Sgblack@eecs.umich.edu * This sets everything up for a RED state trap except for actually jumping to 2943578Sgblack@eecs.umich.edu * the handler. 2953578Sgblack@eecs.umich.edu */ 2963578Sgblack@eecs.umich.edu 2973578Sgblack@eecs.umich.eduvoid doREDFault(ThreadContext *tc, TrapType tt) 2983578Sgblack@eecs.umich.edu{ 2994172Ssaidi@eecs.umich.edu MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL); 3004172Ssaidi@eecs.umich.edu MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE); 3014172Ssaidi@eecs.umich.edu MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE); 3024172Ssaidi@eecs.umich.edu MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 3034172Ssaidi@eecs.umich.edu //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR); 3043761Sgblack@eecs.umich.edu MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2); 3054172Ssaidi@eecs.umich.edu MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI); 3064172Ssaidi@eecs.umich.edu MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP); 3074172Ssaidi@eecs.umich.edu //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE); 3084172Ssaidi@eecs.umich.edu MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3); 3094172Ssaidi@eecs.umich.edu MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL); 3107720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 3113578Sgblack@eecs.umich.edu 3123578Sgblack@eecs.umich.edu TL++; 3133578Sgblack@eecs.umich.edu 3147720Sgblack@eecs.umich.edu Addr pcMask = bits(PSTATE, 3) ? mask(32) : mask(64); 3153928Ssaidi@eecs.umich.edu 3163578Sgblack@eecs.umich.edu //set TSTATE.gl to gl 3173578Sgblack@eecs.umich.edu replaceBits(TSTATE, 42, 40, GL); 3183578Sgblack@eecs.umich.edu //set TSTATE.ccr to ccr 3193578Sgblack@eecs.umich.edu replaceBits(TSTATE, 39, 32, CCR); 3203578Sgblack@eecs.umich.edu //set TSTATE.asi to asi 3213578Sgblack@eecs.umich.edu replaceBits(TSTATE, 31, 24, ASI); 3223578Sgblack@eecs.umich.edu //set TSTATE.pstate to pstate 3233578Sgblack@eecs.umich.edu replaceBits(TSTATE, 20, 8, PSTATE); 3243578Sgblack@eecs.umich.edu //set TSTATE.cwp to cwp 3253578Sgblack@eecs.umich.edu replaceBits(TSTATE, 4, 0, CWP); 3263578Sgblack@eecs.umich.edu 3273578Sgblack@eecs.umich.edu //Write back TSTATE 3284172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE); 3293578Sgblack@eecs.umich.edu 3303578Sgblack@eecs.umich.edu //set TPC to PC 3317720Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask); 3323578Sgblack@eecs.umich.edu //set TNPC to NPC 3337720Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask); 3343578Sgblack@eecs.umich.edu 3353578Sgblack@eecs.umich.edu //set HTSTATE.hpstate to hpstate 3364172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE); 3373578Sgblack@eecs.umich.edu 3383578Sgblack@eecs.umich.edu //TT = trap type; 3394172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TT, tt); 3403578Sgblack@eecs.umich.edu 3413578Sgblack@eecs.umich.edu //Update GL 3424172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL)); 3433578Sgblack@eecs.umich.edu 3443926Ssaidi@eecs.umich.edu PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit 3453926Ssaidi@eecs.umich.edu PSTATE |= (1 << 4); //set PSTATE.pef to 1 3464172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE); 3473578Sgblack@eecs.umich.edu 3483578Sgblack@eecs.umich.edu //set HPSTATE.red to 1 3493578Sgblack@eecs.umich.edu HPSTATE |= (1 << 5); 3503578Sgblack@eecs.umich.edu //set HPSTATE.hpriv to 1 3513578Sgblack@eecs.umich.edu HPSTATE |= (1 << 2); 3523578Sgblack@eecs.umich.edu //set HPSTATE.ibe to 0 3533578Sgblack@eecs.umich.edu HPSTATE &= ~(1 << 10); 3543578Sgblack@eecs.umich.edu //set HPSTATE.tlz to 0 3553578Sgblack@eecs.umich.edu HPSTATE &= ~(1 << 0); 3564172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE); 3573578Sgblack@eecs.umich.edu 3583578Sgblack@eecs.umich.edu bool changedCWP = true; 3593578Sgblack@eecs.umich.edu if(tt == 0x24) 3603578Sgblack@eecs.umich.edu CWP++; 3613578Sgblack@eecs.umich.edu else if(0x80 <= tt && tt <= 0xbf) 3623578Sgblack@eecs.umich.edu CWP += (CANSAVE + 2); 3633578Sgblack@eecs.umich.edu else if(0xc0 <= tt && tt <= 0xff) 3643578Sgblack@eecs.umich.edu CWP--; 3653578Sgblack@eecs.umich.edu else 3663578Sgblack@eecs.umich.edu changedCWP = false; 3673578Sgblack@eecs.umich.edu 3683578Sgblack@eecs.umich.edu if(changedCWP) 3693578Sgblack@eecs.umich.edu { 3703578Sgblack@eecs.umich.edu CWP = (CWP + NWindows) % NWindows; 3714172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 3723578Sgblack@eecs.umich.edu } 3733578Sgblack@eecs.umich.edu} 3743578Sgblack@eecs.umich.edu 3753578Sgblack@eecs.umich.edu/** 3763578Sgblack@eecs.umich.edu * This sets everything up for a normal trap except for actually jumping to 3773578Sgblack@eecs.umich.edu * the handler. 3783578Sgblack@eecs.umich.edu */ 3793578Sgblack@eecs.umich.edu 3803578Sgblack@eecs.umich.eduvoid doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) 3813578Sgblack@eecs.umich.edu{ 3824172Ssaidi@eecs.umich.edu MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL); 3834172Ssaidi@eecs.umich.edu MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE); 3844172Ssaidi@eecs.umich.edu MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE); 3854172Ssaidi@eecs.umich.edu MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 3864172Ssaidi@eecs.umich.edu //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR); 3873761Sgblack@eecs.umich.edu MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2); 3884172Ssaidi@eecs.umich.edu MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI); 3894172Ssaidi@eecs.umich.edu MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP); 3904172Ssaidi@eecs.umich.edu //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE); 3913761Sgblack@eecs.umich.edu MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3); 3924172Ssaidi@eecs.umich.edu MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL); 3937720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 3943928Ssaidi@eecs.umich.edu 3953415Sgblack@eecs.umich.edu //Increment the trap level 3963415Sgblack@eecs.umich.edu TL++; 3974172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TL, TL); 3983415Sgblack@eecs.umich.edu 3997720Sgblack@eecs.umich.edu Addr pcMask = bits(PSTATE, 3) ? mask(32) : mask(64); 4007720Sgblack@eecs.umich.edu 4013415Sgblack@eecs.umich.edu //Save off state 4023415Sgblack@eecs.umich.edu 4033415Sgblack@eecs.umich.edu //set TSTATE.gl to gl 4043415Sgblack@eecs.umich.edu replaceBits(TSTATE, 42, 40, GL); 4053415Sgblack@eecs.umich.edu //set TSTATE.ccr to ccr 4063415Sgblack@eecs.umich.edu replaceBits(TSTATE, 39, 32, CCR); 4073415Sgblack@eecs.umich.edu //set TSTATE.asi to asi 4083415Sgblack@eecs.umich.edu replaceBits(TSTATE, 31, 24, ASI); 4093415Sgblack@eecs.umich.edu //set TSTATE.pstate to pstate 4103415Sgblack@eecs.umich.edu replaceBits(TSTATE, 20, 8, PSTATE); 4113415Sgblack@eecs.umich.edu //set TSTATE.cwp to cwp 4123415Sgblack@eecs.umich.edu replaceBits(TSTATE, 4, 0, CWP); 4133415Sgblack@eecs.umich.edu 4143415Sgblack@eecs.umich.edu //Write back TSTATE 4154172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE); 4163415Sgblack@eecs.umich.edu 4173415Sgblack@eecs.umich.edu //set TPC to PC 4187720Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask); 4193415Sgblack@eecs.umich.edu //set TNPC to NPC 4207720Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask); 4213415Sgblack@eecs.umich.edu 4223415Sgblack@eecs.umich.edu //set HTSTATE.hpstate to hpstate 4234172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE); 4243415Sgblack@eecs.umich.edu 4253415Sgblack@eecs.umich.edu //TT = trap type; 4264172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TT, tt); 4273415Sgblack@eecs.umich.edu 4283415Sgblack@eecs.umich.edu //Update the global register level 4293893Shsul@eecs.umich.edu if (!gotoHpriv) 4304172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxPGL)); 4313415Sgblack@eecs.umich.edu else 4324172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL)); 4333415Sgblack@eecs.umich.edu 4343415Sgblack@eecs.umich.edu //PSTATE.mm is unchanged 4353926Ssaidi@eecs.umich.edu PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present 4363926Ssaidi@eecs.umich.edu PSTATE &= ~(1 << 3); //PSTATE.am = 0 4373926Ssaidi@eecs.umich.edu PSTATE &= ~(1 << 1); //PSTATE.ie = 0 4383415Sgblack@eecs.umich.edu //PSTATE.tle is unchanged 4393415Sgblack@eecs.umich.edu //PSTATE.tct = 0 4403415Sgblack@eecs.umich.edu 4413893Shsul@eecs.umich.edu if (gotoHpriv) 4423415Sgblack@eecs.umich.edu { 4433926Ssaidi@eecs.umich.edu PSTATE &= ~(1 << 9); // PSTATE.cle = 0 4443926Ssaidi@eecs.umich.edu //The manual says PSTATE.priv should be 0, but Legion leaves it alone 4453926Ssaidi@eecs.umich.edu HPSTATE &= ~(1 << 5); //HPSTATE.red = 0 4463926Ssaidi@eecs.umich.edu HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1 4473926Ssaidi@eecs.umich.edu HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0 4483415Sgblack@eecs.umich.edu //HPSTATE.tlz is unchanged 4494172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE); 4503926Ssaidi@eecs.umich.edu } else { // we are going to priv 4513926Ssaidi@eecs.umich.edu PSTATE |= (1 << 2); //PSTATE.priv = 1 4523926Ssaidi@eecs.umich.edu replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle 4533415Sgblack@eecs.umich.edu } 4544172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE); 4553926Ssaidi@eecs.umich.edu 4563415Sgblack@eecs.umich.edu 4573415Sgblack@eecs.umich.edu bool changedCWP = true; 4583893Shsul@eecs.umich.edu if (tt == 0x24) 4593415Sgblack@eecs.umich.edu CWP++; 4603893Shsul@eecs.umich.edu else if (0x80 <= tt && tt <= 0xbf) 4613415Sgblack@eecs.umich.edu CWP += (CANSAVE + 2); 4623893Shsul@eecs.umich.edu else if (0xc0 <= tt && tt <= 0xff) 4633415Sgblack@eecs.umich.edu CWP--; 4643415Sgblack@eecs.umich.edu else 4653415Sgblack@eecs.umich.edu changedCWP = false; 4663420Sgblack@eecs.umich.edu 4673893Shsul@eecs.umich.edu if (changedCWP) 4683415Sgblack@eecs.umich.edu { 4693415Sgblack@eecs.umich.edu CWP = (CWP + NWindows) % NWindows; 4704172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4713415Sgblack@eecs.umich.edu } 4723415Sgblack@eecs.umich.edu} 4733415Sgblack@eecs.umich.edu 4747720Sgblack@eecs.umich.eduvoid getREDVector(MiscReg TT, Addr &PC, Addr &NPC) 4753578Sgblack@eecs.umich.edu{ 4763585Sgblack@eecs.umich.edu //XXX The following constant might belong in a header file. 4773603Ssaidi@eecs.umich.edu const Addr RSTVAddr = 0xFFF0000000ULL; 4783595Sgblack@eecs.umich.edu PC = RSTVAddr | ((TT << 5) & 0xFF); 4793578Sgblack@eecs.umich.edu NPC = PC + sizeof(MachInst); 4803578Sgblack@eecs.umich.edu} 4813578Sgblack@eecs.umich.edu 4823585Sgblack@eecs.umich.eduvoid getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT) 4833578Sgblack@eecs.umich.edu{ 4844172Ssaidi@eecs.umich.edu Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA); 4853578Sgblack@eecs.umich.edu PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14)); 4863578Sgblack@eecs.umich.edu NPC = PC + sizeof(MachInst); 4873578Sgblack@eecs.umich.edu} 4883578Sgblack@eecs.umich.edu 4893585Sgblack@eecs.umich.eduvoid getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL) 4903578Sgblack@eecs.umich.edu{ 4914172Ssaidi@eecs.umich.edu Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA); 4923578Sgblack@eecs.umich.edu PC = (TBA & ~mask(15)) | 4933578Sgblack@eecs.umich.edu (TL > 1 ? (1 << 14) : 0) | 4943578Sgblack@eecs.umich.edu ((TT << 5) & mask(14)); 4953578Sgblack@eecs.umich.edu NPC = PC + sizeof(MachInst); 4963578Sgblack@eecs.umich.edu} 4973578Sgblack@eecs.umich.edu 4982221SN/A#if FULL_SYSTEM 4992221SN/A 5007678Sgblack@eecs.umich.eduvoid SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst) 5012221SN/A{ 5023825Ssaidi@eecs.umich.edu //panic("Invoking a second fault!\n"); 5032680Sktlim@umich.edu FaultBase::invoke(tc); 5042223SN/A countStat()++; 5052221SN/A 5063578Sgblack@eecs.umich.edu //We can refer to this to see what the trap level -was-, but something 5073578Sgblack@eecs.umich.edu //in the middle could change it in the regfile out from under us. 5084172Ssaidi@eecs.umich.edu MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL); 5094172Ssaidi@eecs.umich.edu MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT); 5104172Ssaidi@eecs.umich.edu MiscReg pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 5114172Ssaidi@eecs.umich.edu MiscReg hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 5123578Sgblack@eecs.umich.edu 5133578Sgblack@eecs.umich.edu Addr PC, NPC; 5143578Sgblack@eecs.umich.edu 5153578Sgblack@eecs.umich.edu PrivilegeLevel current; 5163893Shsul@eecs.umich.edu if (hpstate & HPSTATE::hpriv) 5173746Sgblack@eecs.umich.edu current = Hyperprivileged; 5183893Shsul@eecs.umich.edu else if (pstate & PSTATE::priv) 5193578Sgblack@eecs.umich.edu current = Privileged; 5203578Sgblack@eecs.umich.edu else 5213746Sgblack@eecs.umich.edu current = User; 5223578Sgblack@eecs.umich.edu 5233578Sgblack@eecs.umich.edu PrivilegeLevel level = getNextLevel(current); 5243578Sgblack@eecs.umich.edu 5253893Shsul@eecs.umich.edu if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) { 5263595Sgblack@eecs.umich.edu getREDVector(5, PC, NPC); 5273893Shsul@eecs.umich.edu doREDFault(tc, tt); 5283746Sgblack@eecs.umich.edu //This changes the hpstate and pstate, so we need to make sure we 5293746Sgblack@eecs.umich.edu //save the old version on the trap stack in doREDFault. 5303578Sgblack@eecs.umich.edu enterREDState(tc); 5313893Shsul@eecs.umich.edu } else if (tl == MaxTL) { 5323825Ssaidi@eecs.umich.edu panic("Should go to error state here.. crap\n"); 5333578Sgblack@eecs.umich.edu //Do error_state somehow? 5343578Sgblack@eecs.umich.edu //Probably inject a WDR fault using the interrupt mechanism. 5353578Sgblack@eecs.umich.edu //What should the PC and NPC be set to? 5363893Shsul@eecs.umich.edu } else if (tl > MaxPTL && level == Privileged) { 5373578Sgblack@eecs.umich.edu //guest_watchdog fault 5383578Sgblack@eecs.umich.edu doNormalFault(tc, trapType(), true); 5393585Sgblack@eecs.umich.edu getHyperVector(tc, PC, NPC, 2); 5403893Shsul@eecs.umich.edu } else if (level == Hyperprivileged || 5415570Snate@binkert.org (level == Privileged && trapType() >= 384)) { 5423578Sgblack@eecs.umich.edu doNormalFault(tc, trapType(), true); 5433585Sgblack@eecs.umich.edu getHyperVector(tc, PC, NPC, trapType()); 5443826Ssaidi@eecs.umich.edu } else { 5453578Sgblack@eecs.umich.edu doNormalFault(tc, trapType(), false); 5463893Shsul@eecs.umich.edu getPrivVector(tc, PC, NPC, trapType(), tl+1); 5473578Sgblack@eecs.umich.edu } 5483578Sgblack@eecs.umich.edu 5497720Sgblack@eecs.umich.edu PCState pc; 5507720Sgblack@eecs.umich.edu pc.pc(PC); 5517720Sgblack@eecs.umich.edu pc.npc(NPC); 5527720Sgblack@eecs.umich.edu pc.nnpc(NPC + sizeof(MachInst)); 5537720Sgblack@eecs.umich.edu pc.upc(0); 5547720Sgblack@eecs.umich.edu pc.nupc(1); 5557720Sgblack@eecs.umich.edu tc->pcState(pc); 5563420Sgblack@eecs.umich.edu} 5572221SN/A 5587678Sgblack@eecs.umich.eduvoid PowerOnReset::invoke(ThreadContext * tc, StaticInstPtr inst) 5593523Sgblack@eecs.umich.edu{ 5603523Sgblack@eecs.umich.edu //For SPARC, when a system is first started, there is a power 5613523Sgblack@eecs.umich.edu //on reset Trap which sets the processor into the following state. 5623523Sgblack@eecs.umich.edu //Bits that aren't set aren't defined on startup. 5633595Sgblack@eecs.umich.edu 5644172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TL, MaxTL); 5654172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TT, trapType()); 5664172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_GL, MaxGL); 5673595Sgblack@eecs.umich.edu 5683746Sgblack@eecs.umich.edu //Turn on pef and priv, set everything else to 0 5694172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_PSTATE, (1 << 4) | (1 << 2)); 5703595Sgblack@eecs.umich.edu 5713595Sgblack@eecs.umich.edu //Turn on red and hpriv, set everything else to 0 5724172Ssaidi@eecs.umich.edu MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 5733628Sgblack@eecs.umich.edu //HPSTATE.red = 1 5743628Sgblack@eecs.umich.edu HPSTATE |= (1 << 5); 5753628Sgblack@eecs.umich.edu //HPSTATE.hpriv = 1 5763628Sgblack@eecs.umich.edu HPSTATE |= (1 << 2); 5773628Sgblack@eecs.umich.edu //HPSTATE.ibe = 0 5783628Sgblack@eecs.umich.edu HPSTATE &= ~(1 << 10); 5793628Sgblack@eecs.umich.edu //HPSTATE.tlz = 0 5803628Sgblack@eecs.umich.edu HPSTATE &= ~(1 << 0); 5814172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE); 5823595Sgblack@eecs.umich.edu 5833595Sgblack@eecs.umich.edu //The tick register is unreadable by nonprivileged software 5844172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63); 5853595Sgblack@eecs.umich.edu 5863746Sgblack@eecs.umich.edu //Enter RED state. We do this last so that the actual state preserved in 5873746Sgblack@eecs.umich.edu //the trap stack is the state from before this fault. 5883746Sgblack@eecs.umich.edu enterREDState(tc); 5893746Sgblack@eecs.umich.edu 5903595Sgblack@eecs.umich.edu Addr PC, NPC; 5913595Sgblack@eecs.umich.edu getREDVector(trapType(), PC, NPC); 5927720Sgblack@eecs.umich.edu 5937720Sgblack@eecs.umich.edu PCState pc; 5947720Sgblack@eecs.umich.edu pc.pc(PC); 5957720Sgblack@eecs.umich.edu pc.npc(NPC); 5967720Sgblack@eecs.umich.edu pc.nnpc(NPC + sizeof(MachInst)); 5977720Sgblack@eecs.umich.edu pc.upc(0); 5987720Sgblack@eecs.umich.edu pc.nupc(1); 5997720Sgblack@eecs.umich.edu tc->pcState(pc); 6003595Sgblack@eecs.umich.edu 6013595Sgblack@eecs.umich.edu //These registers are specified as "undefined" after a POR, and they 6023595Sgblack@eecs.umich.edu //should have reasonable values after the miscregfile is reset 6033523Sgblack@eecs.umich.edu /* 6043595Sgblack@eecs.umich.edu // Clear all the soft interrupt bits 6053595Sgblack@eecs.umich.edu softint = 0; 6063595Sgblack@eecs.umich.edu // disable timer compare interrupts, reset tick_cmpr 6074172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ 6083595Sgblack@eecs.umich.edu tick_cmprFields.int_dis = 1; 6093523Sgblack@eecs.umich.edu tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 6103523Sgblack@eecs.umich.edu stickFields.npt = 1; //The TICK register is unreadable by by !priv 6113523Sgblack@eecs.umich.edu stick_cmprFields.int_dis = 1; // disable timer compare interrupts 6123523Sgblack@eecs.umich.edu stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 6133523Sgblack@eecs.umich.edu 6143523Sgblack@eecs.umich.edu tt[tl] = _trapType; 6153523Sgblack@eecs.umich.edu 6163523Sgblack@eecs.umich.edu hintp = 0; // no interrupts pending 6173523Sgblack@eecs.umich.edu hstick_cmprFields.int_dis = 1; // disable timer compare interrupts 6183523Sgblack@eecs.umich.edu hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 6193523Sgblack@eecs.umich.edu */ 6202221SN/A} 6212221SN/A 6223578Sgblack@eecs.umich.edu#else // !FULL_SYSTEM 6232612SN/A 6247678Sgblack@eecs.umich.eduvoid FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, 6257678Sgblack@eecs.umich.edu StaticInstPtr inst) 6264997Sgblack@eecs.umich.edu{ 6274997Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 6285184Sgblack@eecs.umich.edu TlbEntry entry; 6295184Sgblack@eecs.umich.edu bool success = p->pTable->lookup(vaddr, entry); 6304997Sgblack@eecs.umich.edu if(!success) { 6314997Sgblack@eecs.umich.edu panic("Tried to execute unmapped address %#x.\n", vaddr); 6324997Sgblack@eecs.umich.edu } else { 6334997Sgblack@eecs.umich.edu Addr alignedVaddr = p->pTable->pageAlign(vaddr); 6344997Sgblack@eecs.umich.edu tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/, 6355184Sgblack@eecs.umich.edu p->M5_pid /*context id*/, false, entry.pte); 6364997Sgblack@eecs.umich.edu } 6374997Sgblack@eecs.umich.edu} 6384997Sgblack@eecs.umich.edu 6397678Sgblack@eecs.umich.eduvoid FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst) 6404997Sgblack@eecs.umich.edu{ 6414997Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 6425184Sgblack@eecs.umich.edu TlbEntry entry; 6435184Sgblack@eecs.umich.edu bool success = p->pTable->lookup(vaddr, entry); 6444997Sgblack@eecs.umich.edu if(!success) { 6454997Sgblack@eecs.umich.edu p->checkAndAllocNextPage(vaddr); 6465184Sgblack@eecs.umich.edu success = p->pTable->lookup(vaddr, entry); 6474997Sgblack@eecs.umich.edu } 6484997Sgblack@eecs.umich.edu if(!success) { 6494997Sgblack@eecs.umich.edu panic("Tried to access unmapped address %#x.\n", vaddr); 6504997Sgblack@eecs.umich.edu } else { 6514997Sgblack@eecs.umich.edu Addr alignedVaddr = p->pTable->pageAlign(vaddr); 6524997Sgblack@eecs.umich.edu tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/, 6535184Sgblack@eecs.umich.edu p->M5_pid /*context id*/, false, entry.pte); 6544997Sgblack@eecs.umich.edu } 6554997Sgblack@eecs.umich.edu} 6564997Sgblack@eecs.umich.edu 6577678Sgblack@eecs.umich.eduvoid SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) 6583415Sgblack@eecs.umich.edu{ 6593578Sgblack@eecs.umich.edu doNormalFault(tc, trapType(), false); 6603415Sgblack@eecs.umich.edu 6613415Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 6623415Sgblack@eecs.umich.edu 6633578Sgblack@eecs.umich.edu //XXX This will only work in faults from a SparcLiveProcess 6643415Sgblack@eecs.umich.edu SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 6653415Sgblack@eecs.umich.edu assert(lp); 6663415Sgblack@eecs.umich.edu 6673415Sgblack@eecs.umich.edu //Then adjust the PC and NPC 6687720Sgblack@eecs.umich.edu tc->pcState(lp->readSpillStart()); 6693415Sgblack@eecs.umich.edu} 6703415Sgblack@eecs.umich.edu 6717678Sgblack@eecs.umich.eduvoid FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) 6723415Sgblack@eecs.umich.edu{ 6733578Sgblack@eecs.umich.edu doNormalFault(tc, trapType(), false); 6743415Sgblack@eecs.umich.edu 6753415Sgblack@eecs.umich.edu Process * p = tc->getProcessPtr(); 6763415Sgblack@eecs.umich.edu 6773578Sgblack@eecs.umich.edu //XXX This will only work in faults from a SparcLiveProcess 6783415Sgblack@eecs.umich.edu SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 6793415Sgblack@eecs.umich.edu assert(lp); 6803415Sgblack@eecs.umich.edu 6813578Sgblack@eecs.umich.edu //Then adjust the PC and NPC 6827720Sgblack@eecs.umich.edu tc->pcState(lp->readFillStart()); 6833415Sgblack@eecs.umich.edu} 6843415Sgblack@eecs.umich.edu 6857678Sgblack@eecs.umich.eduvoid TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) 6864111Sgblack@eecs.umich.edu{ 6874111Sgblack@eecs.umich.edu //In SE, this mechanism is how the process requests a service from the 6884111Sgblack@eecs.umich.edu //operating system. We'll get the process object from the thread context 6894111Sgblack@eecs.umich.edu //and let it service the request. 6904111Sgblack@eecs.umich.edu 6914111Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 6924111Sgblack@eecs.umich.edu 6934111Sgblack@eecs.umich.edu SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 6944111Sgblack@eecs.umich.edu assert(lp); 6954111Sgblack@eecs.umich.edu 6964111Sgblack@eecs.umich.edu lp->handleTrap(_n, tc); 6974111Sgblack@eecs.umich.edu 6984111Sgblack@eecs.umich.edu //We need to explicitly advance the pc, since that's not done for us 6994111Sgblack@eecs.umich.edu //on a faulting instruction 7007720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 7017720Sgblack@eecs.umich.edu pc.advance(); 7027720Sgblack@eecs.umich.edu tc->pcState(pc); 7034111Sgblack@eecs.umich.edu} 7044111Sgblack@eecs.umich.edu 7052221SN/A#endif 7062221SN/A 7072223SN/A} // namespace SparcISA 7082221SN/A 709