faults.cc revision 3826
12221SN/A/*
22221SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32221SN/A * All rights reserved.
42221SN/A *
52221SN/A * Redistribution and use in source and binary forms, with or without
62221SN/A * modification, are permitted provided that the following conditions are
72221SN/A * met: redistributions of source code must retain the above copyright
82221SN/A * notice, this list of conditions and the following disclaimer;
92221SN/A * redistributions in binary form must reproduce the above copyright
102221SN/A * notice, this list of conditions and the following disclaimer in the
112221SN/A * documentation and/or other materials provided with the distribution;
122221SN/A * neither the name of the copyright holders nor the names of its
132221SN/A * contributors may be used to endorse or promote products derived from
142221SN/A * this software without specific prior written permission.
152221SN/A *
162221SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172221SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182221SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192221SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202221SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212221SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222221SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232221SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242221SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252221SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262221SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Gabe Black
292665Ssaidi@eecs.umich.edu *          Kevin Lim
302221SN/A */
312221SN/A
323415Sgblack@eecs.umich.edu#include <algorithm>
333415Sgblack@eecs.umich.edu
342223SN/A#include "arch/sparc/faults.hh"
353415Sgblack@eecs.umich.edu#include "arch/sparc/isa_traits.hh"
363578Sgblack@eecs.umich.edu#include "arch/sparc/types.hh"
373415Sgblack@eecs.umich.edu#include "base/bitfield.hh"
383415Sgblack@eecs.umich.edu#include "base/trace.hh"
393523Sgblack@eecs.umich.edu#include "config/full_system.hh"
403415Sgblack@eecs.umich.edu#include "cpu/base.hh"
412680Sktlim@umich.edu#include "cpu/thread_context.hh"
422800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM
433523Sgblack@eecs.umich.edu#include "arch/sparc/process.hh"
443415Sgblack@eecs.umich.edu#include "mem/page_table.hh"
452800Ssaidi@eecs.umich.edu#include "sim/process.hh"
462800Ssaidi@eecs.umich.edu#endif
472221SN/A
483415Sgblack@eecs.umich.eduusing namespace std;
493415Sgblack@eecs.umich.edu
502223SN/Anamespace SparcISA
512221SN/A{
522221SN/A
533573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
543576Sgblack@eecs.umich.edu    SparcFault<PowerOnReset>::vals =
553576Sgblack@eecs.umich.edu    {"power_on_reset", 0x001, 0, {H, H, H}};
562221SN/A
573573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
583576Sgblack@eecs.umich.edu    SparcFault<WatchDogReset>::vals =
593576Sgblack@eecs.umich.edu    {"watch_dog_reset", 0x002, 120, {H, H, H}};
602221SN/A
613573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
623576Sgblack@eecs.umich.edu    SparcFault<ExternallyInitiatedReset>::vals =
633576Sgblack@eecs.umich.edu    {"externally_initiated_reset", 0x003, 110, {H, H, H}};
642221SN/A
653573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
663576Sgblack@eecs.umich.edu    SparcFault<SoftwareInitiatedReset>::vals =
673576Sgblack@eecs.umich.edu    {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
682221SN/A
693573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
703576Sgblack@eecs.umich.edu    SparcFault<REDStateException>::vals =
713576Sgblack@eecs.umich.edu    {"RED_state_exception", 0x005, 1, {H, H, H}};
722221SN/A
733573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
743576Sgblack@eecs.umich.edu    SparcFault<StoreError>::vals =
753576Sgblack@eecs.umich.edu    {"store_error", 0x007, 201, {H, H, H}};
762221SN/A
773573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
783576Sgblack@eecs.umich.edu    SparcFault<InstructionAccessException>::vals =
793576Sgblack@eecs.umich.edu    {"instruction_access_exception", 0x008, 300, {H, H, H}};
803576Sgblack@eecs.umich.edu
813576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005
823576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals
833576Sgblack@eecs.umich.edu    SparcFault<InstructionAccessMMUMiss>::vals =
843576Sgblack@eecs.umich.edu    {"inst_mmu", 0x009, 2, {H, H, H}};*/
852221SN/A
863573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
873576Sgblack@eecs.umich.edu    SparcFault<InstructionAccessError>::vals =
883576Sgblack@eecs.umich.edu    {"instruction_access_error", 0x00A, 400, {H, H, H}};
892221SN/A
903573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
913576Sgblack@eecs.umich.edu    SparcFault<IllegalInstruction>::vals =
923576Sgblack@eecs.umich.edu    {"illegal_instruction", 0x010, 620, {H, H, H}};
932221SN/A
943573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
953576Sgblack@eecs.umich.edu    SparcFault<PrivilegedOpcode>::vals =
963576Sgblack@eecs.umich.edu    {"privileged_opcode", 0x011, 700, {P, SH, SH}};
973576Sgblack@eecs.umich.edu
983576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005
993576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals
1003576Sgblack@eecs.umich.edu    SparcFault<UnimplementedLDD>::vals =
1013576Sgblack@eecs.umich.edu    {"unimp_ldd", 0x012, 6, {H, H, H}};*/
1023576Sgblack@eecs.umich.edu
1033576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005
1043576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals
1053576Sgblack@eecs.umich.edu    SparcFault<UnimplementedSTD>::vals =
1063576Sgblack@eecs.umich.edu    {"unimp_std", 0x013, 6, {H, H, H}};*/
1072221SN/A
1083573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1093576Sgblack@eecs.umich.edu    SparcFault<FpDisabled>::vals =
1103576Sgblack@eecs.umich.edu    {"fp_disabled", 0x020, 800, {P, P, H}};
1112221SN/A
1123573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1133576Sgblack@eecs.umich.edu    SparcFault<FpExceptionIEEE754>::vals =
1143576Sgblack@eecs.umich.edu    {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
1152221SN/A
1163573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1173576Sgblack@eecs.umich.edu    SparcFault<FpExceptionOther>::vals =
1183576Sgblack@eecs.umich.edu    {"fp_exception_other", 0x022, 1110, {P, P, H}};
1192221SN/A
1203573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1213576Sgblack@eecs.umich.edu    SparcFault<TagOverflow>::vals =
1223576Sgblack@eecs.umich.edu    {"tag_overflow", 0x023, 1400, {P, P, H}};
1232221SN/A
1243573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1253576Sgblack@eecs.umich.edu    SparcFault<CleanWindow>::vals =
1263576Sgblack@eecs.umich.edu    {"clean_window", 0x024, 1010, {P, P, H}};
1272221SN/A
1283573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1293576Sgblack@eecs.umich.edu    SparcFault<DivisionByZero>::vals =
1303576Sgblack@eecs.umich.edu    {"division_by_zero", 0x028, 1500, {P, P, H}};
1312223SN/A
1323573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1333576Sgblack@eecs.umich.edu    SparcFault<InternalProcessorError>::vals =
1343576Sgblack@eecs.umich.edu    {"internal_processor_error", 0x029, 4, {H, H, H}};
1352223SN/A
1363573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1373576Sgblack@eecs.umich.edu    SparcFault<InstructionInvalidTSBEntry>::vals =
1383576Sgblack@eecs.umich.edu    {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
1392223SN/A
1403573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1413576Sgblack@eecs.umich.edu    SparcFault<DataInvalidTSBEntry>::vals =
1423576Sgblack@eecs.umich.edu    {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
1432223SN/A
1443573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1453576Sgblack@eecs.umich.edu    SparcFault<DataAccessException>::vals =
1463576Sgblack@eecs.umich.edu    {"data_access_exception", 0x030, 1201, {H, H, H}};
1473576Sgblack@eecs.umich.edu
1483576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005
1493576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals
1503576Sgblack@eecs.umich.edu    SparcFault<DataAccessMMUMiss>::vals =
1513576Sgblack@eecs.umich.edu    {"data_mmu", 0x031, 12, {H, H, H}};*/
1522223SN/A
1533573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1543576Sgblack@eecs.umich.edu    SparcFault<DataAccessError>::vals =
1553576Sgblack@eecs.umich.edu    {"data_access_error", 0x032, 1210, {H, H, H}};
1562223SN/A
1573573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1583576Sgblack@eecs.umich.edu    SparcFault<DataAccessProtection>::vals =
1593576Sgblack@eecs.umich.edu    {"data_access_protection", 0x033, 1207, {H, H, H}};
1602223SN/A
1613573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1623576Sgblack@eecs.umich.edu    SparcFault<MemAddressNotAligned>::vals =
1633576Sgblack@eecs.umich.edu    {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
1642223SN/A
1653573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1663576Sgblack@eecs.umich.edu    SparcFault<LDDFMemAddressNotAligned>::vals =
1673576Sgblack@eecs.umich.edu    {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
1682223SN/A
1693573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1703576Sgblack@eecs.umich.edu    SparcFault<STDFMemAddressNotAligned>::vals =
1713576Sgblack@eecs.umich.edu    {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
1722223SN/A
1733573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1743576Sgblack@eecs.umich.edu    SparcFault<PrivilegedAction>::vals =
1753576Sgblack@eecs.umich.edu    {"privileged_action", 0x037, 1110, {H, H, SH}};
1762223SN/A
1773573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1783576Sgblack@eecs.umich.edu    SparcFault<LDQFMemAddressNotAligned>::vals =
1793576Sgblack@eecs.umich.edu    {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
1802223SN/A
1813573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1823576Sgblack@eecs.umich.edu    SparcFault<STQFMemAddressNotAligned>::vals =
1833576Sgblack@eecs.umich.edu    {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
1842223SN/A
1853573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1863576Sgblack@eecs.umich.edu    SparcFault<InstructionRealTranslationMiss>::vals =
1873576Sgblack@eecs.umich.edu    {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
1882223SN/A
1893573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1903576Sgblack@eecs.umich.edu    SparcFault<DataRealTranslationMiss>::vals =
1913576Sgblack@eecs.umich.edu    {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
1922223SN/A
1933576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005
1943576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals
1953576Sgblack@eecs.umich.edu    SparcFault<AsyncDataError>::vals =
1963576Sgblack@eecs.umich.edu    {"async_data", 0x040, 2, {H, H, H}};*/
1972527SN/A
1983573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1993576Sgblack@eecs.umich.edu    SparcFault<InterruptLevelN>::vals =
2003576Sgblack@eecs.umich.edu    {"interrupt_level_n", 0x041, 0, {P, P, SH}};
2012223SN/A
2023573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2033576Sgblack@eecs.umich.edu    SparcFault<HstickMatch>::vals =
2043576Sgblack@eecs.umich.edu    {"hstick_match", 0x05E, 1601, {H, H, H}};
2052223SN/A
2063573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2073576Sgblack@eecs.umich.edu    SparcFault<TrapLevelZero>::vals =
2083576Sgblack@eecs.umich.edu    {"trap_level_zero", 0x05F, 202, {H, H, SH}};
2092223SN/A
2103573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2113576Sgblack@eecs.umich.edu    SparcFault<PAWatchpoint>::vals =
2123576Sgblack@eecs.umich.edu    {"PA_watchpoint", 0x061, 1209, {H, H, H}};
2132223SN/A
2143573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2153576Sgblack@eecs.umich.edu    SparcFault<VAWatchpoint>::vals =
2163576Sgblack@eecs.umich.edu    {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
2172223SN/A
2183573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2193576Sgblack@eecs.umich.edu    SparcFault<FastInstructionAccessMMUMiss>::vals =
2203576Sgblack@eecs.umich.edu    {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
2213576Sgblack@eecs.umich.edu
2223576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2233576Sgblack@eecs.umich.edu    SparcFault<FastDataAccessMMUMiss>::vals =
2243576Sgblack@eecs.umich.edu    {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
2253576Sgblack@eecs.umich.edu
2263576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2273576Sgblack@eecs.umich.edu    SparcFault<FastDataAccessProtection>::vals =
2283576Sgblack@eecs.umich.edu    {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
2293576Sgblack@eecs.umich.edu
2303576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2313576Sgblack@eecs.umich.edu    SparcFault<InstructionBreakpoint>::vals =
2323576Sgblack@eecs.umich.edu    {"instruction_break", 0x076, 610, {H, H, H}};
2333576Sgblack@eecs.umich.edu
2343576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2353576Sgblack@eecs.umich.edu    SparcFault<CpuMondo>::vals =
2363576Sgblack@eecs.umich.edu    {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
2373576Sgblack@eecs.umich.edu
2383576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2393576Sgblack@eecs.umich.edu    SparcFault<DevMondo>::vals =
2403576Sgblack@eecs.umich.edu    {"dev_mondo", 0x07D, 1611, {P, P, SH}};
2413576Sgblack@eecs.umich.edu
2423576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2433576Sgblack@eecs.umich.edu    SparcFault<ResumeableError>::vals =
2443576Sgblack@eecs.umich.edu    {"resume_error", 0x07E, 3330, {P, P, SH}};
2453576Sgblack@eecs.umich.edu
2463576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2473576Sgblack@eecs.umich.edu    SparcFault<SpillNNormal>::vals =
2483576Sgblack@eecs.umich.edu    {"spill_n_normal", 0x080, 900, {P, P, H}};
2493576Sgblack@eecs.umich.edu
2503576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2513576Sgblack@eecs.umich.edu    SparcFault<SpillNOther>::vals =
2523576Sgblack@eecs.umich.edu    {"spill_n_other", 0x0A0, 900, {P, P, H}};
2533576Sgblack@eecs.umich.edu
2543576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2553576Sgblack@eecs.umich.edu    SparcFault<FillNNormal>::vals =
2563576Sgblack@eecs.umich.edu    {"fill_n_normal", 0x0C0, 900, {P, P, H}};
2573576Sgblack@eecs.umich.edu
2583576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2593576Sgblack@eecs.umich.edu    SparcFault<FillNOther>::vals =
2603576Sgblack@eecs.umich.edu    {"fill_n_other", 0x0E0, 900, {P, P, H}};
2613576Sgblack@eecs.umich.edu
2623576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2633576Sgblack@eecs.umich.edu    SparcFault<TrapInstruction>::vals =
2643576Sgblack@eecs.umich.edu    {"trap_instruction", 0x100, 1602, {P, P, H}};
2652223SN/A
2662800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM
2673573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2683576Sgblack@eecs.umich.edu    SparcFault<PageTableFault>::vals =
2693576Sgblack@eecs.umich.edu    {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
2702800Ssaidi@eecs.umich.edu#endif
2712800Ssaidi@eecs.umich.edu
2723415Sgblack@eecs.umich.edu/**
2733578Sgblack@eecs.umich.edu * This causes the thread context to enter RED state. This causes the side
2743578Sgblack@eecs.umich.edu * effects which go with entering RED state because of a trap.
2753415Sgblack@eecs.umich.edu */
2763415Sgblack@eecs.umich.edu
2773578Sgblack@eecs.umich.eduvoid enterREDState(ThreadContext *tc)
2783415Sgblack@eecs.umich.edu{
2793578Sgblack@eecs.umich.edu    //@todo Disable the mmu?
2803578Sgblack@eecs.umich.edu    //@todo Disable watchpoints?
2813578Sgblack@eecs.umich.edu    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
2823578Sgblack@eecs.umich.edu    //HPSTATE.red = 1
2833578Sgblack@eecs.umich.edu    HPSTATE |= (1 << 5);
2843578Sgblack@eecs.umich.edu    //HPSTATE.hpriv = 1
2853578Sgblack@eecs.umich.edu    HPSTATE |= (1 << 2);
2863595Sgblack@eecs.umich.edu    tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
2873746Sgblack@eecs.umich.edu    //PSTATE.priv is set to 1 here. The manual says it should be 0, but
2883746Sgblack@eecs.umich.edu    //Legion sets it to 1.
2893746Sgblack@eecs.umich.edu    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
2903746Sgblack@eecs.umich.edu    PSTATE |= (1 << 2);
2913746Sgblack@eecs.umich.edu    tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE);
2923578Sgblack@eecs.umich.edu}
2933578Sgblack@eecs.umich.edu
2943578Sgblack@eecs.umich.edu/**
2953578Sgblack@eecs.umich.edu * This sets everything up for a RED state trap except for actually jumping to
2963578Sgblack@eecs.umich.edu * the handler.
2973578Sgblack@eecs.umich.edu */
2983578Sgblack@eecs.umich.edu
2993578Sgblack@eecs.umich.eduvoid doREDFault(ThreadContext *tc, TrapType tt)
3003578Sgblack@eecs.umich.edu{
3013578Sgblack@eecs.umich.edu    MiscReg TL = tc->readMiscReg(MISCREG_TL);
3023578Sgblack@eecs.umich.edu    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
3033578Sgblack@eecs.umich.edu    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
3043578Sgblack@eecs.umich.edu    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
3053578Sgblack@eecs.umich.edu    MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
3063578Sgblack@eecs.umich.edu    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
3073578Sgblack@eecs.umich.edu    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
3083578Sgblack@eecs.umich.edu    MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
3093578Sgblack@eecs.umich.edu    MiscReg GL = tc->readMiscReg(MISCREG_GL);
3103578Sgblack@eecs.umich.edu    MiscReg PC = tc->readPC();
3113578Sgblack@eecs.umich.edu    MiscReg NPC = tc->readNextPC();
3123578Sgblack@eecs.umich.edu
3133578Sgblack@eecs.umich.edu    TL++;
3143578Sgblack@eecs.umich.edu
3153578Sgblack@eecs.umich.edu    //set TSTATE.gl to gl
3163578Sgblack@eecs.umich.edu    replaceBits(TSTATE, 42, 40, GL);
3173578Sgblack@eecs.umich.edu    //set TSTATE.ccr to ccr
3183578Sgblack@eecs.umich.edu    replaceBits(TSTATE, 39, 32, CCR);
3193578Sgblack@eecs.umich.edu    //set TSTATE.asi to asi
3203578Sgblack@eecs.umich.edu    replaceBits(TSTATE, 31, 24, ASI);
3213578Sgblack@eecs.umich.edu    //set TSTATE.pstate to pstate
3223578Sgblack@eecs.umich.edu    replaceBits(TSTATE, 20, 8, PSTATE);
3233578Sgblack@eecs.umich.edu    //set TSTATE.cwp to cwp
3243578Sgblack@eecs.umich.edu    replaceBits(TSTATE, 4, 0, CWP);
3253578Sgblack@eecs.umich.edu
3263578Sgblack@eecs.umich.edu    //Write back TSTATE
3273578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
3283578Sgblack@eecs.umich.edu
3293578Sgblack@eecs.umich.edu    //set TPC to PC
3303578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TPC, PC);
3313578Sgblack@eecs.umich.edu    //set TNPC to NPC
3323578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TNPC, NPC);
3333578Sgblack@eecs.umich.edu
3343578Sgblack@eecs.umich.edu    //set HTSTATE.hpstate to hpstate
3353578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
3363578Sgblack@eecs.umich.edu
3373578Sgblack@eecs.umich.edu    //TT = trap type;
3383578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TT, tt);
3393578Sgblack@eecs.umich.edu
3403578Sgblack@eecs.umich.edu    //Update GL
3413578Sgblack@eecs.umich.edu    tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
3423578Sgblack@eecs.umich.edu
3433578Sgblack@eecs.umich.edu    //set PSTATE.mm to 00
3443578Sgblack@eecs.umich.edu    //set PSTATE.pef to 1
3453578Sgblack@eecs.umich.edu    PSTATE |= (1 << 4);
3463578Sgblack@eecs.umich.edu    //set PSTATE.am to 0
3473578Sgblack@eecs.umich.edu    PSTATE &= ~(1 << 3);
3483746Sgblack@eecs.umich.edu/*    //set PSTATE.priv to 0
3493746Sgblack@eecs.umich.edu    PSTATE &= ~(1 << 2);*/
3503578Sgblack@eecs.umich.edu    //set PSTATE.ie to 0
3513746Sgblack@eecs.umich.edu    //PSTATE.priv is set to 1 here. The manual says it should be 0, but
3523746Sgblack@eecs.umich.edu    //Legion sets it to 1.
3533746Sgblack@eecs.umich.edu    PSTATE |= (1 << 2);
3543578Sgblack@eecs.umich.edu    //set PSTATE.cle to 0
3553578Sgblack@eecs.umich.edu    PSTATE &= ~(1 << 9);
3563578Sgblack@eecs.umich.edu    //PSTATE.tle is unchanged
3573578Sgblack@eecs.umich.edu    //XXX Where is the tct bit?
3583578Sgblack@eecs.umich.edu    //set PSTATE.tct to 0
3593578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
3603578Sgblack@eecs.umich.edu
3613578Sgblack@eecs.umich.edu    //set HPSTATE.red to 1
3623578Sgblack@eecs.umich.edu    HPSTATE |= (1 << 5);
3633578Sgblack@eecs.umich.edu    //set HPSTATE.hpriv to 1
3643578Sgblack@eecs.umich.edu    HPSTATE |= (1 << 2);
3653578Sgblack@eecs.umich.edu    //set HPSTATE.ibe to 0
3663578Sgblack@eecs.umich.edu    HPSTATE &= ~(1 << 10);
3673578Sgblack@eecs.umich.edu    //set HPSTATE.tlz to 0
3683578Sgblack@eecs.umich.edu    HPSTATE &= ~(1 << 0);
3693578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
3703578Sgblack@eecs.umich.edu
3713578Sgblack@eecs.umich.edu    bool changedCWP = true;
3723578Sgblack@eecs.umich.edu    if(tt == 0x24)
3733578Sgblack@eecs.umich.edu        CWP++;
3743578Sgblack@eecs.umich.edu    else if(0x80 <= tt && tt <= 0xbf)
3753578Sgblack@eecs.umich.edu        CWP += (CANSAVE + 2);
3763578Sgblack@eecs.umich.edu    else if(0xc0 <= tt && tt <= 0xff)
3773578Sgblack@eecs.umich.edu        CWP--;
3783578Sgblack@eecs.umich.edu    else
3793578Sgblack@eecs.umich.edu        changedCWP = false;
3803578Sgblack@eecs.umich.edu
3813578Sgblack@eecs.umich.edu    if(changedCWP)
3823578Sgblack@eecs.umich.edu    {
3833578Sgblack@eecs.umich.edu        CWP = (CWP + NWindows) % NWindows;
3843578Sgblack@eecs.umich.edu        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
3853578Sgblack@eecs.umich.edu    }
3863578Sgblack@eecs.umich.edu}
3873578Sgblack@eecs.umich.edu
3883578Sgblack@eecs.umich.edu/**
3893578Sgblack@eecs.umich.edu * This sets everything up for a normal trap except for actually jumping to
3903578Sgblack@eecs.umich.edu * the handler.
3913578Sgblack@eecs.umich.edu */
3923578Sgblack@eecs.umich.edu
3933578Sgblack@eecs.umich.eduvoid doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
3943578Sgblack@eecs.umich.edu{
3953578Sgblack@eecs.umich.edu    MiscReg TL = tc->readMiscReg(MISCREG_TL);
3963578Sgblack@eecs.umich.edu    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
3973578Sgblack@eecs.umich.edu    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
3983578Sgblack@eecs.umich.edu    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
3993578Sgblack@eecs.umich.edu    MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
4003578Sgblack@eecs.umich.edu    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
4013578Sgblack@eecs.umich.edu    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
4023578Sgblack@eecs.umich.edu    MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
4033578Sgblack@eecs.umich.edu    MiscReg GL = tc->readMiscReg(MISCREG_GL);
4043578Sgblack@eecs.umich.edu    MiscReg PC = tc->readPC();
4053578Sgblack@eecs.umich.edu    MiscReg NPC = tc->readNextPC();
4063415Sgblack@eecs.umich.edu
4073415Sgblack@eecs.umich.edu    //Increment the trap level
4083415Sgblack@eecs.umich.edu    TL++;
4093415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TL, TL);
4103415Sgblack@eecs.umich.edu
4113415Sgblack@eecs.umich.edu    //Save off state
4123415Sgblack@eecs.umich.edu
4133415Sgblack@eecs.umich.edu    //set TSTATE.gl to gl
4143415Sgblack@eecs.umich.edu    replaceBits(TSTATE, 42, 40, GL);
4153415Sgblack@eecs.umich.edu    //set TSTATE.ccr to ccr
4163415Sgblack@eecs.umich.edu    replaceBits(TSTATE, 39, 32, CCR);
4173415Sgblack@eecs.umich.edu    //set TSTATE.asi to asi
4183415Sgblack@eecs.umich.edu    replaceBits(TSTATE, 31, 24, ASI);
4193415Sgblack@eecs.umich.edu    //set TSTATE.pstate to pstate
4203415Sgblack@eecs.umich.edu    replaceBits(TSTATE, 20, 8, PSTATE);
4213415Sgblack@eecs.umich.edu    //set TSTATE.cwp to cwp
4223415Sgblack@eecs.umich.edu    replaceBits(TSTATE, 4, 0, CWP);
4233415Sgblack@eecs.umich.edu
4243415Sgblack@eecs.umich.edu    //Write back TSTATE
4253415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
4263415Sgblack@eecs.umich.edu
4273415Sgblack@eecs.umich.edu    //set TPC to PC
4283415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TPC, PC);
4293415Sgblack@eecs.umich.edu    //set TNPC to NPC
4303415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TNPC, NPC);
4313415Sgblack@eecs.umich.edu
4323415Sgblack@eecs.umich.edu    //set HTSTATE.hpstate to hpstate
4333415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
4343415Sgblack@eecs.umich.edu
4353415Sgblack@eecs.umich.edu    //TT = trap type;
4363415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TT, tt);
4373415Sgblack@eecs.umich.edu
4383415Sgblack@eecs.umich.edu    //Update the global register level
4393578Sgblack@eecs.umich.edu    if(!gotoHpriv)
4403578Sgblack@eecs.umich.edu        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
4413415Sgblack@eecs.umich.edu    else
4423578Sgblack@eecs.umich.edu        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
4433415Sgblack@eecs.umich.edu
4443415Sgblack@eecs.umich.edu    //PSTATE.mm is unchanged
4453415Sgblack@eecs.umich.edu    //PSTATE.pef = whether or not an fpu is present
4463415Sgblack@eecs.umich.edu    //XXX We'll say there's one present, even though there aren't
4473415Sgblack@eecs.umich.edu    //implementations for a decent number of the instructions
4483415Sgblack@eecs.umich.edu    PSTATE |= (1 << 4);
4493415Sgblack@eecs.umich.edu    //PSTATE.am = 0
4503415Sgblack@eecs.umich.edu    PSTATE &= ~(1 << 3);
4513578Sgblack@eecs.umich.edu    if(!gotoHpriv)
4523415Sgblack@eecs.umich.edu    {
4533415Sgblack@eecs.umich.edu        //PSTATE.priv = 1
4543415Sgblack@eecs.umich.edu        PSTATE |= (1 << 2);
4553415Sgblack@eecs.umich.edu        //PSTATE.cle = PSTATE.tle
4563415Sgblack@eecs.umich.edu        replaceBits(PSTATE, 9, 9, PSTATE >> 8);
4573415Sgblack@eecs.umich.edu    }
4583415Sgblack@eecs.umich.edu    else
4593415Sgblack@eecs.umich.edu    {
4603415Sgblack@eecs.umich.edu        //PSTATE.priv = 0
4613746Sgblack@eecs.umich.edu        //PSTATE.priv is set to 1 here. The manual says it should be 0, but
4623746Sgblack@eecs.umich.edu        //Legion sets it to 1.
4633746Sgblack@eecs.umich.edu        PSTATE |= (1 << 2);
4643415Sgblack@eecs.umich.edu        //PSTATE.cle = 0
4653415Sgblack@eecs.umich.edu        PSTATE &= ~(1 << 9);
4663415Sgblack@eecs.umich.edu    }
4673415Sgblack@eecs.umich.edu    //PSTATE.ie = 0
4683415Sgblack@eecs.umich.edu    PSTATE &= ~(1 << 1);
4693415Sgblack@eecs.umich.edu    //PSTATE.tle is unchanged
4703415Sgblack@eecs.umich.edu    //PSTATE.tct = 0
4713415Sgblack@eecs.umich.edu    //XXX Where exactly is this field?
4723415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
4733415Sgblack@eecs.umich.edu
4743578Sgblack@eecs.umich.edu    if(gotoHpriv)
4753415Sgblack@eecs.umich.edu    {
4763415Sgblack@eecs.umich.edu        //HPSTATE.red = 0
4773415Sgblack@eecs.umich.edu        HPSTATE &= ~(1 << 5);
4783415Sgblack@eecs.umich.edu        //HPSTATE.hpriv = 1
4793415Sgblack@eecs.umich.edu        HPSTATE |= (1 << 2);
4803415Sgblack@eecs.umich.edu        //HPSTATE.ibe = 0
4813415Sgblack@eecs.umich.edu        HPSTATE &= ~(1 << 10);
4823415Sgblack@eecs.umich.edu        //HPSTATE.tlz is unchanged
4833415Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
4843415Sgblack@eecs.umich.edu    }
4853415Sgblack@eecs.umich.edu
4863415Sgblack@eecs.umich.edu    bool changedCWP = true;
4873415Sgblack@eecs.umich.edu    if(tt == 0x24)
4883415Sgblack@eecs.umich.edu        CWP++;
4893415Sgblack@eecs.umich.edu    else if(0x80 <= tt && tt <= 0xbf)
4903415Sgblack@eecs.umich.edu        CWP += (CANSAVE + 2);
4913415Sgblack@eecs.umich.edu    else if(0xc0 <= tt && tt <= 0xff)
4923415Sgblack@eecs.umich.edu        CWP--;
4933415Sgblack@eecs.umich.edu    else
4943415Sgblack@eecs.umich.edu        changedCWP = false;
4953420Sgblack@eecs.umich.edu
4963415Sgblack@eecs.umich.edu    if(changedCWP)
4973415Sgblack@eecs.umich.edu    {
4983415Sgblack@eecs.umich.edu        CWP = (CWP + NWindows) % NWindows;
4993415Sgblack@eecs.umich.edu        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
5003415Sgblack@eecs.umich.edu    }
5013415Sgblack@eecs.umich.edu}
5023415Sgblack@eecs.umich.edu
5033595Sgblack@eecs.umich.eduvoid getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
5043578Sgblack@eecs.umich.edu{
5053585Sgblack@eecs.umich.edu    //XXX The following constant might belong in a header file.
5063603Ssaidi@eecs.umich.edu    const Addr RSTVAddr = 0xFFF0000000ULL;
5073595Sgblack@eecs.umich.edu    PC = RSTVAddr | ((TT << 5) & 0xFF);
5083578Sgblack@eecs.umich.edu    NPC = PC + sizeof(MachInst);
5093578Sgblack@eecs.umich.edu}
5103578Sgblack@eecs.umich.edu
5113585Sgblack@eecs.umich.eduvoid getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
5123578Sgblack@eecs.umich.edu{
5133585Sgblack@eecs.umich.edu    Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
5143578Sgblack@eecs.umich.edu    PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
5153578Sgblack@eecs.umich.edu    NPC = PC + sizeof(MachInst);
5163578Sgblack@eecs.umich.edu}
5173578Sgblack@eecs.umich.edu
5183585Sgblack@eecs.umich.eduvoid getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
5193578Sgblack@eecs.umich.edu{
5203585Sgblack@eecs.umich.edu    Addr TBA = tc->readMiscReg(MISCREG_TBA);
5213578Sgblack@eecs.umich.edu    PC = (TBA & ~mask(15)) |
5223578Sgblack@eecs.umich.edu        (TL > 1 ? (1 << 14) : 0) |
5233578Sgblack@eecs.umich.edu        ((TT << 5) & mask(14));
5243578Sgblack@eecs.umich.edu    NPC = PC + sizeof(MachInst);
5253578Sgblack@eecs.umich.edu}
5263578Sgblack@eecs.umich.edu
5272221SN/A#if FULL_SYSTEM
5282221SN/A
5293573Sgblack@eecs.umich.eduvoid SparcFaultBase::invoke(ThreadContext * tc)
5302221SN/A{
5313825Ssaidi@eecs.umich.edu    //panic("Invoking a second fault!\n");
5322680Sktlim@umich.edu    FaultBase::invoke(tc);
5332223SN/A    countStat()++;
5342221SN/A
5353578Sgblack@eecs.umich.edu    //We can refer to this to see what the trap level -was-, but something
5363578Sgblack@eecs.umich.edu    //in the middle could change it in the regfile out from under us.
5373578Sgblack@eecs.umich.edu    MiscReg TL = tc->readMiscReg(MISCREG_TL);
5383578Sgblack@eecs.umich.edu    MiscReg TT = tc->readMiscReg(MISCREG_TT);
5393578Sgblack@eecs.umich.edu    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
5403578Sgblack@eecs.umich.edu    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
5413578Sgblack@eecs.umich.edu
5423578Sgblack@eecs.umich.edu    Addr PC, NPC;
5433578Sgblack@eecs.umich.edu
5443578Sgblack@eecs.umich.edu    PrivilegeLevel current;
5453746Sgblack@eecs.umich.edu    if(HPSTATE & (1 << 2))
5463746Sgblack@eecs.umich.edu        current = Hyperprivileged;
5473746Sgblack@eecs.umich.edu    else if(PSTATE & (1 << 2))
5483578Sgblack@eecs.umich.edu        current = Privileged;
5493578Sgblack@eecs.umich.edu    else
5503746Sgblack@eecs.umich.edu        current = User;
5513578Sgblack@eecs.umich.edu
5523578Sgblack@eecs.umich.edu    PrivilegeLevel level = getNextLevel(current);
5533578Sgblack@eecs.umich.edu
5543826Ssaidi@eecs.umich.edu    if(HPSTATE & (1 << 5) || TL == MaxTL - 1) {
5553595Sgblack@eecs.umich.edu        getREDVector(5, PC, NPC);
5563746Sgblack@eecs.umich.edu        doREDFault(tc, TT);
5573746Sgblack@eecs.umich.edu        //This changes the hpstate and pstate, so we need to make sure we
5583746Sgblack@eecs.umich.edu        //save the old version on the trap stack in doREDFault.
5593578Sgblack@eecs.umich.edu        enterREDState(tc);
5603826Ssaidi@eecs.umich.edu    } else if(TL == MaxTL) {
5613825Ssaidi@eecs.umich.edu        panic("Should go to error state here.. crap\n");
5623578Sgblack@eecs.umich.edu        //Do error_state somehow?
5633578Sgblack@eecs.umich.edu        //Probably inject a WDR fault using the interrupt mechanism.
5643578Sgblack@eecs.umich.edu        //What should the PC and NPC be set to?
5653826Ssaidi@eecs.umich.edu    } else if(TL > MaxPTL && level == Privileged) {
5663578Sgblack@eecs.umich.edu        //guest_watchdog fault
5673578Sgblack@eecs.umich.edu        doNormalFault(tc, trapType(), true);
5683585Sgblack@eecs.umich.edu        getHyperVector(tc, PC, NPC, 2);
5693826Ssaidi@eecs.umich.edu    } else if(level == Hyperprivileged ||
5703826Ssaidi@eecs.umich.edu            level == Privileged && trapType() >= 384) {
5713578Sgblack@eecs.umich.edu        doNormalFault(tc, trapType(), true);
5723585Sgblack@eecs.umich.edu        getHyperVector(tc, PC, NPC, trapType());
5733826Ssaidi@eecs.umich.edu    } else {
5743578Sgblack@eecs.umich.edu        doNormalFault(tc, trapType(), false);
5753585Sgblack@eecs.umich.edu        getPrivVector(tc, PC, NPC, trapType(), TL+1);
5763578Sgblack@eecs.umich.edu    }
5773578Sgblack@eecs.umich.edu
5783578Sgblack@eecs.umich.edu    tc->setPC(PC);
5793578Sgblack@eecs.umich.edu    tc->setNextPC(NPC);
5803578Sgblack@eecs.umich.edu    tc->setNextNPC(NPC + sizeof(MachInst));
5813420Sgblack@eecs.umich.edu}
5822221SN/A
5833523Sgblack@eecs.umich.eduvoid PowerOnReset::invoke(ThreadContext * tc)
5843523Sgblack@eecs.umich.edu{
5853523Sgblack@eecs.umich.edu    //For SPARC, when a system is first started, there is a power
5863523Sgblack@eecs.umich.edu    //on reset Trap which sets the processor into the following state.
5873523Sgblack@eecs.umich.edu    //Bits that aren't set aren't defined on startup.
5883595Sgblack@eecs.umich.edu
5893595Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TL, MaxTL);
5903595Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TT, trapType());
5913595Sgblack@eecs.umich.edu    tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
5923595Sgblack@eecs.umich.edu
5933746Sgblack@eecs.umich.edu    //Turn on pef and priv, set everything else to 0
5943746Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2));
5953595Sgblack@eecs.umich.edu
5963595Sgblack@eecs.umich.edu    //Turn on red and hpriv, set everything else to 0
5973628Sgblack@eecs.umich.edu    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
5983628Sgblack@eecs.umich.edu    //HPSTATE.red = 1
5993628Sgblack@eecs.umich.edu    HPSTATE |= (1 << 5);
6003628Sgblack@eecs.umich.edu    //HPSTATE.hpriv = 1
6013628Sgblack@eecs.umich.edu    HPSTATE |= (1 << 2);
6023628Sgblack@eecs.umich.edu    //HPSTATE.ibe = 0
6033628Sgblack@eecs.umich.edu    HPSTATE &= ~(1 << 10);
6043628Sgblack@eecs.umich.edu    //HPSTATE.tlz = 0
6053628Sgblack@eecs.umich.edu    HPSTATE &= ~(1 << 0);
6063628Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
6073595Sgblack@eecs.umich.edu
6083595Sgblack@eecs.umich.edu    //The tick register is unreadable by nonprivileged software
6093595Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
6103595Sgblack@eecs.umich.edu
6113746Sgblack@eecs.umich.edu    //Enter RED state. We do this last so that the actual state preserved in
6123746Sgblack@eecs.umich.edu    //the trap stack is the state from before this fault.
6133746Sgblack@eecs.umich.edu    enterREDState(tc);
6143746Sgblack@eecs.umich.edu
6153595Sgblack@eecs.umich.edu    Addr PC, NPC;
6163595Sgblack@eecs.umich.edu    getREDVector(trapType(), PC, NPC);
6173595Sgblack@eecs.umich.edu    tc->setPC(PC);
6183595Sgblack@eecs.umich.edu    tc->setNextPC(NPC);
6193595Sgblack@eecs.umich.edu    tc->setNextNPC(NPC + sizeof(MachInst));
6203595Sgblack@eecs.umich.edu
6213595Sgblack@eecs.umich.edu    //These registers are specified as "undefined" after a POR, and they
6223595Sgblack@eecs.umich.edu    //should have reasonable values after the miscregfile is reset
6233523Sgblack@eecs.umich.edu    /*
6243595Sgblack@eecs.umich.edu    // Clear all the soft interrupt bits
6253595Sgblack@eecs.umich.edu    softint = 0;
6263595Sgblack@eecs.umich.edu    // disable timer compare interrupts, reset tick_cmpr
6273595Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_
6283595Sgblack@eecs.umich.edu    tick_cmprFields.int_dis = 1;
6293523Sgblack@eecs.umich.edu    tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
6303523Sgblack@eecs.umich.edu    stickFields.npt = 1; //The TICK register is unreadable by by !priv
6313523Sgblack@eecs.umich.edu    stick_cmprFields.int_dis = 1; // disable timer compare interrupts
6323523Sgblack@eecs.umich.edu    stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
6333523Sgblack@eecs.umich.edu
6343523Sgblack@eecs.umich.edu    tt[tl] = _trapType;
6353523Sgblack@eecs.umich.edu
6363523Sgblack@eecs.umich.edu    hintp = 0; // no interrupts pending
6373523Sgblack@eecs.umich.edu    hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
6383523Sgblack@eecs.umich.edu    hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
6393523Sgblack@eecs.umich.edu    */
6402221SN/A}
6412221SN/A
6423578Sgblack@eecs.umich.edu#else // !FULL_SYSTEM
6432612SN/A
6443415Sgblack@eecs.umich.eduvoid SpillNNormal::invoke(ThreadContext *tc)
6453415Sgblack@eecs.umich.edu{
6463578Sgblack@eecs.umich.edu    doNormalFault(tc, trapType(), false);
6473415Sgblack@eecs.umich.edu
6483415Sgblack@eecs.umich.edu    Process *p = tc->getProcessPtr();
6493415Sgblack@eecs.umich.edu
6503578Sgblack@eecs.umich.edu    //XXX This will only work in faults from a SparcLiveProcess
6513415Sgblack@eecs.umich.edu    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
6523415Sgblack@eecs.umich.edu    assert(lp);
6533415Sgblack@eecs.umich.edu
6543415Sgblack@eecs.umich.edu    //Then adjust the PC and NPC
6553415Sgblack@eecs.umich.edu    Addr spillStart = lp->readSpillStart();
6563415Sgblack@eecs.umich.edu    tc->setPC(spillStart);
6573415Sgblack@eecs.umich.edu    tc->setNextPC(spillStart + sizeof(MachInst));
6583415Sgblack@eecs.umich.edu    tc->setNextNPC(spillStart + 2*sizeof(MachInst));
6593415Sgblack@eecs.umich.edu}
6603415Sgblack@eecs.umich.edu
6613415Sgblack@eecs.umich.eduvoid FillNNormal::invoke(ThreadContext *tc)
6623415Sgblack@eecs.umich.edu{
6633578Sgblack@eecs.umich.edu    doNormalFault(tc, trapType(), false);
6643415Sgblack@eecs.umich.edu
6653415Sgblack@eecs.umich.edu    Process * p = tc->getProcessPtr();
6663415Sgblack@eecs.umich.edu
6673578Sgblack@eecs.umich.edu    //XXX This will only work in faults from a SparcLiveProcess
6683415Sgblack@eecs.umich.edu    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
6693415Sgblack@eecs.umich.edu    assert(lp);
6703415Sgblack@eecs.umich.edu
6713578Sgblack@eecs.umich.edu    //Then adjust the PC and NPC
6723415Sgblack@eecs.umich.edu    Addr fillStart = lp->readFillStart();
6733415Sgblack@eecs.umich.edu    tc->setPC(fillStart);
6743415Sgblack@eecs.umich.edu    tc->setNextPC(fillStart + sizeof(MachInst));
6753415Sgblack@eecs.umich.edu    tc->setNextNPC(fillStart + 2*sizeof(MachInst));
6763415Sgblack@eecs.umich.edu}
6773415Sgblack@eecs.umich.edu
6782800Ssaidi@eecs.umich.eduvoid PageTableFault::invoke(ThreadContext *tc)
6792800Ssaidi@eecs.umich.edu{
6802800Ssaidi@eecs.umich.edu    Process *p = tc->getProcessPtr();
6812800Ssaidi@eecs.umich.edu
6822800Ssaidi@eecs.umich.edu    // address is higher than the stack region or in the current stack region
6832800Ssaidi@eecs.umich.edu    if (vaddr > p->stack_base || vaddr > p->stack_min)
6842800Ssaidi@eecs.umich.edu        FaultBase::invoke(tc);
6852800Ssaidi@eecs.umich.edu
6862800Ssaidi@eecs.umich.edu    // We've accessed the next page
6872800Ssaidi@eecs.umich.edu    if (vaddr > p->stack_min - PageBytes) {
6882800Ssaidi@eecs.umich.edu        p->stack_min -= PageBytes;
6892800Ssaidi@eecs.umich.edu        if (p->stack_base - p->stack_min > 8*1024*1024)
6902800Ssaidi@eecs.umich.edu            fatal("Over max stack size for one thread\n");
6912800Ssaidi@eecs.umich.edu        p->pTable->allocate(p->stack_min, PageBytes);
6922800Ssaidi@eecs.umich.edu        warn("Increasing stack size by one page.");
6932800Ssaidi@eecs.umich.edu    } else {
6942800Ssaidi@eecs.umich.edu        FaultBase::invoke(tc);
6952800Ssaidi@eecs.umich.edu    }
6962800Ssaidi@eecs.umich.edu}
6973415Sgblack@eecs.umich.edu
6982221SN/A#endif
6992221SN/A
7002223SN/A} // namespace SparcISA
7012221SN/A
702