faults.cc revision 3761
12221SN/A/*
22221SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32221SN/A * All rights reserved.
42221SN/A *
52221SN/A * Redistribution and use in source and binary forms, with or without
62221SN/A * modification, are permitted provided that the following conditions are
72221SN/A * met: redistributions of source code must retain the above copyright
82221SN/A * notice, this list of conditions and the following disclaimer;
92221SN/A * redistributions in binary form must reproduce the above copyright
102221SN/A * notice, this list of conditions and the following disclaimer in the
112221SN/A * documentation and/or other materials provided with the distribution;
122221SN/A * neither the name of the copyright holders nor the names of its
132221SN/A * contributors may be used to endorse or promote products derived from
142221SN/A * this software without specific prior written permission.
152221SN/A *
162221SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172221SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182221SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192221SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202221SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212221SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222221SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232221SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242221SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252221SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262221SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Gabe Black
292665Ssaidi@eecs.umich.edu *          Kevin Lim
302221SN/A */
312221SN/A
323415Sgblack@eecs.umich.edu#include <algorithm>
333415Sgblack@eecs.umich.edu
342223SN/A#include "arch/sparc/faults.hh"
353415Sgblack@eecs.umich.edu#include "arch/sparc/isa_traits.hh"
363578Sgblack@eecs.umich.edu#include "arch/sparc/types.hh"
373415Sgblack@eecs.umich.edu#include "base/bitfield.hh"
383415Sgblack@eecs.umich.edu#include "base/trace.hh"
393523Sgblack@eecs.umich.edu#include "config/full_system.hh"
403415Sgblack@eecs.umich.edu#include "cpu/base.hh"
412680Sktlim@umich.edu#include "cpu/thread_context.hh"
422800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM
433523Sgblack@eecs.umich.edu#include "arch/sparc/process.hh"
443415Sgblack@eecs.umich.edu#include "mem/page_table.hh"
452800Ssaidi@eecs.umich.edu#include "sim/process.hh"
462800Ssaidi@eecs.umich.edu#endif
472221SN/A
483415Sgblack@eecs.umich.eduusing namespace std;
493415Sgblack@eecs.umich.edu
502223SN/Anamespace SparcISA
512221SN/A{
522221SN/A
533573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
543576Sgblack@eecs.umich.edu    SparcFault<PowerOnReset>::vals =
553576Sgblack@eecs.umich.edu    {"power_on_reset", 0x001, 0, {H, H, H}};
562221SN/A
573573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
583576Sgblack@eecs.umich.edu    SparcFault<WatchDogReset>::vals =
593576Sgblack@eecs.umich.edu    {"watch_dog_reset", 0x002, 120, {H, H, H}};
602221SN/A
613573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
623576Sgblack@eecs.umich.edu    SparcFault<ExternallyInitiatedReset>::vals =
633576Sgblack@eecs.umich.edu    {"externally_initiated_reset", 0x003, 110, {H, H, H}};
642221SN/A
653573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
663576Sgblack@eecs.umich.edu    SparcFault<SoftwareInitiatedReset>::vals =
673576Sgblack@eecs.umich.edu    {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
682221SN/A
693573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
703576Sgblack@eecs.umich.edu    SparcFault<REDStateException>::vals =
713576Sgblack@eecs.umich.edu    {"RED_state_exception", 0x005, 1, {H, H, H}};
722221SN/A
733573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
743576Sgblack@eecs.umich.edu    SparcFault<StoreError>::vals =
753576Sgblack@eecs.umich.edu    {"store_error", 0x007, 201, {H, H, H}};
762221SN/A
773573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
783576Sgblack@eecs.umich.edu    SparcFault<InstructionAccessException>::vals =
793576Sgblack@eecs.umich.edu    {"instruction_access_exception", 0x008, 300, {H, H, H}};
803576Sgblack@eecs.umich.edu
813576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005
823576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals
833576Sgblack@eecs.umich.edu    SparcFault<InstructionAccessMMUMiss>::vals =
843576Sgblack@eecs.umich.edu    {"inst_mmu", 0x009, 2, {H, H, H}};*/
852221SN/A
863573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
873576Sgblack@eecs.umich.edu    SparcFault<InstructionAccessError>::vals =
883576Sgblack@eecs.umich.edu    {"instruction_access_error", 0x00A, 400, {H, H, H}};
892221SN/A
903573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
913576Sgblack@eecs.umich.edu    SparcFault<IllegalInstruction>::vals =
923576Sgblack@eecs.umich.edu    {"illegal_instruction", 0x010, 620, {H, H, H}};
932221SN/A
943573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
953576Sgblack@eecs.umich.edu    SparcFault<PrivilegedOpcode>::vals =
963576Sgblack@eecs.umich.edu    {"privileged_opcode", 0x011, 700, {P, SH, SH}};
973576Sgblack@eecs.umich.edu
983576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005
993576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals
1003576Sgblack@eecs.umich.edu    SparcFault<UnimplementedLDD>::vals =
1013576Sgblack@eecs.umich.edu    {"unimp_ldd", 0x012, 6, {H, H, H}};*/
1023576Sgblack@eecs.umich.edu
1033576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005
1043576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals
1053576Sgblack@eecs.umich.edu    SparcFault<UnimplementedSTD>::vals =
1063576Sgblack@eecs.umich.edu    {"unimp_std", 0x013, 6, {H, H, H}};*/
1072221SN/A
1083573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1093576Sgblack@eecs.umich.edu    SparcFault<FpDisabled>::vals =
1103576Sgblack@eecs.umich.edu    {"fp_disabled", 0x020, 800, {P, P, H}};
1112221SN/A
1123573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1133576Sgblack@eecs.umich.edu    SparcFault<FpExceptionIEEE754>::vals =
1143576Sgblack@eecs.umich.edu    {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
1152221SN/A
1163573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1173576Sgblack@eecs.umich.edu    SparcFault<FpExceptionOther>::vals =
1183576Sgblack@eecs.umich.edu    {"fp_exception_other", 0x022, 1110, {P, P, H}};
1192221SN/A
1203573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1213576Sgblack@eecs.umich.edu    SparcFault<TagOverflow>::vals =
1223576Sgblack@eecs.umich.edu    {"tag_overflow", 0x023, 1400, {P, P, H}};
1232221SN/A
1243573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1253576Sgblack@eecs.umich.edu    SparcFault<CleanWindow>::vals =
1263576Sgblack@eecs.umich.edu    {"clean_window", 0x024, 1010, {P, P, H}};
1272221SN/A
1283573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1293576Sgblack@eecs.umich.edu    SparcFault<DivisionByZero>::vals =
1303576Sgblack@eecs.umich.edu    {"division_by_zero", 0x028, 1500, {P, P, H}};
1312223SN/A
1323573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1333576Sgblack@eecs.umich.edu    SparcFault<InternalProcessorError>::vals =
1343576Sgblack@eecs.umich.edu    {"internal_processor_error", 0x029, 4, {H, H, H}};
1352223SN/A
1363573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1373576Sgblack@eecs.umich.edu    SparcFault<InstructionInvalidTSBEntry>::vals =
1383576Sgblack@eecs.umich.edu    {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
1392223SN/A
1403573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1413576Sgblack@eecs.umich.edu    SparcFault<DataInvalidTSBEntry>::vals =
1423576Sgblack@eecs.umich.edu    {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
1432223SN/A
1443573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1453576Sgblack@eecs.umich.edu    SparcFault<DataAccessException>::vals =
1463576Sgblack@eecs.umich.edu    {"data_access_exception", 0x030, 1201, {H, H, H}};
1473576Sgblack@eecs.umich.edu
1483576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005
1493576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals
1503576Sgblack@eecs.umich.edu    SparcFault<DataAccessMMUMiss>::vals =
1513576Sgblack@eecs.umich.edu    {"data_mmu", 0x031, 12, {H, H, H}};*/
1522223SN/A
1533573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1543576Sgblack@eecs.umich.edu    SparcFault<DataAccessError>::vals =
1553576Sgblack@eecs.umich.edu    {"data_access_error", 0x032, 1210, {H, H, H}};
1562223SN/A
1573573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1583576Sgblack@eecs.umich.edu    SparcFault<DataAccessProtection>::vals =
1593576Sgblack@eecs.umich.edu    {"data_access_protection", 0x033, 1207, {H, H, H}};
1602223SN/A
1613573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1623576Sgblack@eecs.umich.edu    SparcFault<MemAddressNotAligned>::vals =
1633576Sgblack@eecs.umich.edu    {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
1642223SN/A
1653573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1663576Sgblack@eecs.umich.edu    SparcFault<LDDFMemAddressNotAligned>::vals =
1673576Sgblack@eecs.umich.edu    {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
1682223SN/A
1693573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1703576Sgblack@eecs.umich.edu    SparcFault<STDFMemAddressNotAligned>::vals =
1713576Sgblack@eecs.umich.edu    {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
1722223SN/A
1733573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1743576Sgblack@eecs.umich.edu    SparcFault<PrivilegedAction>::vals =
1753576Sgblack@eecs.umich.edu    {"privileged_action", 0x037, 1110, {H, H, SH}};
1762223SN/A
1773573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1783576Sgblack@eecs.umich.edu    SparcFault<LDQFMemAddressNotAligned>::vals =
1793576Sgblack@eecs.umich.edu    {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
1802223SN/A
1813573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1823576Sgblack@eecs.umich.edu    SparcFault<STQFMemAddressNotAligned>::vals =
1833576Sgblack@eecs.umich.edu    {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
1842223SN/A
1853573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1863576Sgblack@eecs.umich.edu    SparcFault<InstructionRealTranslationMiss>::vals =
1873576Sgblack@eecs.umich.edu    {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
1882223SN/A
1893573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1903576Sgblack@eecs.umich.edu    SparcFault<DataRealTranslationMiss>::vals =
1913576Sgblack@eecs.umich.edu    {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
1922223SN/A
1933576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005
1943576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals
1953576Sgblack@eecs.umich.edu    SparcFault<AsyncDataError>::vals =
1963576Sgblack@eecs.umich.edu    {"async_data", 0x040, 2, {H, H, H}};*/
1972527SN/A
1983573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
1993576Sgblack@eecs.umich.edu    SparcFault<InterruptLevelN>::vals =
2003576Sgblack@eecs.umich.edu    {"interrupt_level_n", 0x041, 0, {P, P, SH}};
2012223SN/A
2023573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2033576Sgblack@eecs.umich.edu    SparcFault<HstickMatch>::vals =
2043576Sgblack@eecs.umich.edu    {"hstick_match", 0x05E, 1601, {H, H, H}};
2052223SN/A
2063573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2073576Sgblack@eecs.umich.edu    SparcFault<TrapLevelZero>::vals =
2083576Sgblack@eecs.umich.edu    {"trap_level_zero", 0x05F, 202, {H, H, SH}};
2092223SN/A
2103573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2113576Sgblack@eecs.umich.edu    SparcFault<PAWatchpoint>::vals =
2123576Sgblack@eecs.umich.edu    {"PA_watchpoint", 0x061, 1209, {H, H, H}};
2132223SN/A
2143573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2153576Sgblack@eecs.umich.edu    SparcFault<VAWatchpoint>::vals =
2163576Sgblack@eecs.umich.edu    {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
2172223SN/A
2183573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2193576Sgblack@eecs.umich.edu    SparcFault<FastInstructionAccessMMUMiss>::vals =
2203576Sgblack@eecs.umich.edu    {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
2213576Sgblack@eecs.umich.edu
2223576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2233576Sgblack@eecs.umich.edu    SparcFault<FastDataAccessMMUMiss>::vals =
2243576Sgblack@eecs.umich.edu    {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
2253576Sgblack@eecs.umich.edu
2263576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2273576Sgblack@eecs.umich.edu    SparcFault<FastDataAccessProtection>::vals =
2283576Sgblack@eecs.umich.edu    {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
2293576Sgblack@eecs.umich.edu
2303576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2313576Sgblack@eecs.umich.edu    SparcFault<InstructionBreakpoint>::vals =
2323576Sgblack@eecs.umich.edu    {"instruction_break", 0x076, 610, {H, H, H}};
2333576Sgblack@eecs.umich.edu
2343576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2353576Sgblack@eecs.umich.edu    SparcFault<CpuMondo>::vals =
2363576Sgblack@eecs.umich.edu    {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
2373576Sgblack@eecs.umich.edu
2383576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2393576Sgblack@eecs.umich.edu    SparcFault<DevMondo>::vals =
2403576Sgblack@eecs.umich.edu    {"dev_mondo", 0x07D, 1611, {P, P, SH}};
2413576Sgblack@eecs.umich.edu
2423576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2433576Sgblack@eecs.umich.edu    SparcFault<ResumeableError>::vals =
2443576Sgblack@eecs.umich.edu    {"resume_error", 0x07E, 3330, {P, P, SH}};
2453576Sgblack@eecs.umich.edu
2463576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2473576Sgblack@eecs.umich.edu    SparcFault<SpillNNormal>::vals =
2483576Sgblack@eecs.umich.edu    {"spill_n_normal", 0x080, 900, {P, P, H}};
2493576Sgblack@eecs.umich.edu
2503576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2513576Sgblack@eecs.umich.edu    SparcFault<SpillNOther>::vals =
2523576Sgblack@eecs.umich.edu    {"spill_n_other", 0x0A0, 900, {P, P, H}};
2533576Sgblack@eecs.umich.edu
2543576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2553576Sgblack@eecs.umich.edu    SparcFault<FillNNormal>::vals =
2563576Sgblack@eecs.umich.edu    {"fill_n_normal", 0x0C0, 900, {P, P, H}};
2573576Sgblack@eecs.umich.edu
2583576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2593576Sgblack@eecs.umich.edu    SparcFault<FillNOther>::vals =
2603576Sgblack@eecs.umich.edu    {"fill_n_other", 0x0E0, 900, {P, P, H}};
2613576Sgblack@eecs.umich.edu
2623576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2633576Sgblack@eecs.umich.edu    SparcFault<TrapInstruction>::vals =
2643576Sgblack@eecs.umich.edu    {"trap_instruction", 0x100, 1602, {P, P, H}};
2652223SN/A
2662800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM
2673573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals
2683576Sgblack@eecs.umich.edu    SparcFault<PageTableFault>::vals =
2693576Sgblack@eecs.umich.edu    {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
2702800Ssaidi@eecs.umich.edu#endif
2712800Ssaidi@eecs.umich.edu
2723415Sgblack@eecs.umich.edu/**
2733578Sgblack@eecs.umich.edu * This causes the thread context to enter RED state. This causes the side
2743578Sgblack@eecs.umich.edu * effects which go with entering RED state because of a trap.
2753415Sgblack@eecs.umich.edu */
2763415Sgblack@eecs.umich.edu
2773578Sgblack@eecs.umich.eduvoid enterREDState(ThreadContext *tc)
2783415Sgblack@eecs.umich.edu{
2793578Sgblack@eecs.umich.edu    //@todo Disable the mmu?
2803578Sgblack@eecs.umich.edu    //@todo Disable watchpoints?
2813578Sgblack@eecs.umich.edu    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
2823578Sgblack@eecs.umich.edu    //HPSTATE.red = 1
2833578Sgblack@eecs.umich.edu    HPSTATE |= (1 << 5);
2843578Sgblack@eecs.umich.edu    //HPSTATE.hpriv = 1
2853578Sgblack@eecs.umich.edu    HPSTATE |= (1 << 2);
2863595Sgblack@eecs.umich.edu    tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
2873746Sgblack@eecs.umich.edu    //PSTATE.priv is set to 1 here. The manual says it should be 0, but
2883746Sgblack@eecs.umich.edu    //Legion sets it to 1.
2893746Sgblack@eecs.umich.edu    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
2903746Sgblack@eecs.umich.edu    PSTATE |= (1 << 2);
2913746Sgblack@eecs.umich.edu    tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE);
2923578Sgblack@eecs.umich.edu}
2933578Sgblack@eecs.umich.edu
2943578Sgblack@eecs.umich.edu/**
2953578Sgblack@eecs.umich.edu * This sets everything up for a RED state trap except for actually jumping to
2963578Sgblack@eecs.umich.edu * the handler.
2973578Sgblack@eecs.umich.edu */
2983578Sgblack@eecs.umich.edu
2993578Sgblack@eecs.umich.eduvoid doREDFault(ThreadContext *tc, TrapType tt)
3003578Sgblack@eecs.umich.edu{
3013578Sgblack@eecs.umich.edu    MiscReg TL = tc->readMiscReg(MISCREG_TL);
3023578Sgblack@eecs.umich.edu    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
3033578Sgblack@eecs.umich.edu    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
3043578Sgblack@eecs.umich.edu    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
3053761Sgblack@eecs.umich.edu    //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
3063761Sgblack@eecs.umich.edu    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
3073578Sgblack@eecs.umich.edu    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
3083578Sgblack@eecs.umich.edu    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
3093761Sgblack@eecs.umich.edu    //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
3103761Sgblack@eecs.umich.edu    MiscReg CANSAVE = tc->readMiscReg(NumIntArchRegs + 3);
3113578Sgblack@eecs.umich.edu    MiscReg GL = tc->readMiscReg(MISCREG_GL);
3123578Sgblack@eecs.umich.edu    MiscReg PC = tc->readPC();
3133578Sgblack@eecs.umich.edu    MiscReg NPC = tc->readNextPC();
3143578Sgblack@eecs.umich.edu
3153578Sgblack@eecs.umich.edu    TL++;
3163578Sgblack@eecs.umich.edu
3173578Sgblack@eecs.umich.edu    //set TSTATE.gl to gl
3183578Sgblack@eecs.umich.edu    replaceBits(TSTATE, 42, 40, GL);
3193578Sgblack@eecs.umich.edu    //set TSTATE.ccr to ccr
3203578Sgblack@eecs.umich.edu    replaceBits(TSTATE, 39, 32, CCR);
3213578Sgblack@eecs.umich.edu    //set TSTATE.asi to asi
3223578Sgblack@eecs.umich.edu    replaceBits(TSTATE, 31, 24, ASI);
3233578Sgblack@eecs.umich.edu    //set TSTATE.pstate to pstate
3243578Sgblack@eecs.umich.edu    replaceBits(TSTATE, 20, 8, PSTATE);
3253578Sgblack@eecs.umich.edu    //set TSTATE.cwp to cwp
3263578Sgblack@eecs.umich.edu    replaceBits(TSTATE, 4, 0, CWP);
3273578Sgblack@eecs.umich.edu
3283578Sgblack@eecs.umich.edu    //Write back TSTATE
3293578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
3303578Sgblack@eecs.umich.edu
3313578Sgblack@eecs.umich.edu    //set TPC to PC
3323578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TPC, PC);
3333578Sgblack@eecs.umich.edu    //set TNPC to NPC
3343578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TNPC, NPC);
3353578Sgblack@eecs.umich.edu
3363578Sgblack@eecs.umich.edu    //set HTSTATE.hpstate to hpstate
3373578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
3383578Sgblack@eecs.umich.edu
3393578Sgblack@eecs.umich.edu    //TT = trap type;
3403578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TT, tt);
3413578Sgblack@eecs.umich.edu
3423578Sgblack@eecs.umich.edu    //Update GL
3433578Sgblack@eecs.umich.edu    tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
3443578Sgblack@eecs.umich.edu
3453578Sgblack@eecs.umich.edu    //set PSTATE.mm to 00
3463578Sgblack@eecs.umich.edu    //set PSTATE.pef to 1
3473578Sgblack@eecs.umich.edu    PSTATE |= (1 << 4);
3483578Sgblack@eecs.umich.edu    //set PSTATE.am to 0
3493578Sgblack@eecs.umich.edu    PSTATE &= ~(1 << 3);
3503746Sgblack@eecs.umich.edu/*    //set PSTATE.priv to 0
3513746Sgblack@eecs.umich.edu    PSTATE &= ~(1 << 2);*/
3523578Sgblack@eecs.umich.edu    //set PSTATE.ie to 0
3533746Sgblack@eecs.umich.edu    //PSTATE.priv is set to 1 here. The manual says it should be 0, but
3543746Sgblack@eecs.umich.edu    //Legion sets it to 1.
3553746Sgblack@eecs.umich.edu    PSTATE |= (1 << 2);
3563578Sgblack@eecs.umich.edu    //set PSTATE.cle to 0
3573578Sgblack@eecs.umich.edu    PSTATE &= ~(1 << 9);
3583578Sgblack@eecs.umich.edu    //PSTATE.tle is unchanged
3593578Sgblack@eecs.umich.edu    //XXX Where is the tct bit?
3603578Sgblack@eecs.umich.edu    //set PSTATE.tct to 0
3613578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
3623578Sgblack@eecs.umich.edu
3633578Sgblack@eecs.umich.edu    //set HPSTATE.red to 1
3643578Sgblack@eecs.umich.edu    HPSTATE |= (1 << 5);
3653578Sgblack@eecs.umich.edu    //set HPSTATE.hpriv to 1
3663578Sgblack@eecs.umich.edu    HPSTATE |= (1 << 2);
3673578Sgblack@eecs.umich.edu    //set HPSTATE.ibe to 0
3683578Sgblack@eecs.umich.edu    HPSTATE &= ~(1 << 10);
3693578Sgblack@eecs.umich.edu    //set HPSTATE.tlz to 0
3703578Sgblack@eecs.umich.edu    HPSTATE &= ~(1 << 0);
3713578Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
3723578Sgblack@eecs.umich.edu
3733578Sgblack@eecs.umich.edu    bool changedCWP = true;
3743578Sgblack@eecs.umich.edu    if(tt == 0x24)
3753578Sgblack@eecs.umich.edu        CWP++;
3763578Sgblack@eecs.umich.edu    else if(0x80 <= tt && tt <= 0xbf)
3773578Sgblack@eecs.umich.edu        CWP += (CANSAVE + 2);
3783578Sgblack@eecs.umich.edu    else if(0xc0 <= tt && tt <= 0xff)
3793578Sgblack@eecs.umich.edu        CWP--;
3803578Sgblack@eecs.umich.edu    else
3813578Sgblack@eecs.umich.edu        changedCWP = false;
3823578Sgblack@eecs.umich.edu
3833578Sgblack@eecs.umich.edu    if(changedCWP)
3843578Sgblack@eecs.umich.edu    {
3853578Sgblack@eecs.umich.edu        CWP = (CWP + NWindows) % NWindows;
3863578Sgblack@eecs.umich.edu        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
3873578Sgblack@eecs.umich.edu    }
3883578Sgblack@eecs.umich.edu}
3893578Sgblack@eecs.umich.edu
3903578Sgblack@eecs.umich.edu/**
3913578Sgblack@eecs.umich.edu * This sets everything up for a normal trap except for actually jumping to
3923578Sgblack@eecs.umich.edu * the handler.
3933578Sgblack@eecs.umich.edu */
3943578Sgblack@eecs.umich.edu
3953578Sgblack@eecs.umich.eduvoid doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
3963578Sgblack@eecs.umich.edu{
3973578Sgblack@eecs.umich.edu    MiscReg TL = tc->readMiscReg(MISCREG_TL);
3983578Sgblack@eecs.umich.edu    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
3993578Sgblack@eecs.umich.edu    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
4003578Sgblack@eecs.umich.edu    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
4013761Sgblack@eecs.umich.edu    //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
4023761Sgblack@eecs.umich.edu    MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
4033578Sgblack@eecs.umich.edu    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
4043578Sgblack@eecs.umich.edu    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
4053761Sgblack@eecs.umich.edu    //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
4063761Sgblack@eecs.umich.edu    MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
4073578Sgblack@eecs.umich.edu    MiscReg GL = tc->readMiscReg(MISCREG_GL);
4083578Sgblack@eecs.umich.edu    MiscReg PC = tc->readPC();
4093578Sgblack@eecs.umich.edu    MiscReg NPC = tc->readNextPC();
4103415Sgblack@eecs.umich.edu
4113415Sgblack@eecs.umich.edu    //Increment the trap level
4123415Sgblack@eecs.umich.edu    TL++;
4133415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TL, TL);
4143415Sgblack@eecs.umich.edu
4153415Sgblack@eecs.umich.edu    //Save off state
4163415Sgblack@eecs.umich.edu
4173415Sgblack@eecs.umich.edu    //set TSTATE.gl to gl
4183415Sgblack@eecs.umich.edu    replaceBits(TSTATE, 42, 40, GL);
4193415Sgblack@eecs.umich.edu    //set TSTATE.ccr to ccr
4203415Sgblack@eecs.umich.edu    replaceBits(TSTATE, 39, 32, CCR);
4213415Sgblack@eecs.umich.edu    //set TSTATE.asi to asi
4223415Sgblack@eecs.umich.edu    replaceBits(TSTATE, 31, 24, ASI);
4233415Sgblack@eecs.umich.edu    //set TSTATE.pstate to pstate
4243415Sgblack@eecs.umich.edu    replaceBits(TSTATE, 20, 8, PSTATE);
4253415Sgblack@eecs.umich.edu    //set TSTATE.cwp to cwp
4263415Sgblack@eecs.umich.edu    replaceBits(TSTATE, 4, 0, CWP);
4273415Sgblack@eecs.umich.edu
4283415Sgblack@eecs.umich.edu    //Write back TSTATE
4293415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
4303415Sgblack@eecs.umich.edu
4313415Sgblack@eecs.umich.edu    //set TPC to PC
4323415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TPC, PC);
4333415Sgblack@eecs.umich.edu    //set TNPC to NPC
4343415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TNPC, NPC);
4353415Sgblack@eecs.umich.edu
4363415Sgblack@eecs.umich.edu    //set HTSTATE.hpstate to hpstate
4373415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
4383415Sgblack@eecs.umich.edu
4393415Sgblack@eecs.umich.edu    //TT = trap type;
4403415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TT, tt);
4413415Sgblack@eecs.umich.edu
4423415Sgblack@eecs.umich.edu    //Update the global register level
4433578Sgblack@eecs.umich.edu    if(!gotoHpriv)
4443578Sgblack@eecs.umich.edu        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
4453415Sgblack@eecs.umich.edu    else
4463578Sgblack@eecs.umich.edu        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
4473415Sgblack@eecs.umich.edu
4483415Sgblack@eecs.umich.edu    //PSTATE.mm is unchanged
4493415Sgblack@eecs.umich.edu    //PSTATE.pef = whether or not an fpu is present
4503415Sgblack@eecs.umich.edu    //XXX We'll say there's one present, even though there aren't
4513415Sgblack@eecs.umich.edu    //implementations for a decent number of the instructions
4523415Sgblack@eecs.umich.edu    PSTATE |= (1 << 4);
4533415Sgblack@eecs.umich.edu    //PSTATE.am = 0
4543415Sgblack@eecs.umich.edu    PSTATE &= ~(1 << 3);
4553578Sgblack@eecs.umich.edu    if(!gotoHpriv)
4563415Sgblack@eecs.umich.edu    {
4573415Sgblack@eecs.umich.edu        //PSTATE.priv = 1
4583415Sgblack@eecs.umich.edu        PSTATE |= (1 << 2);
4593415Sgblack@eecs.umich.edu        //PSTATE.cle = PSTATE.tle
4603415Sgblack@eecs.umich.edu        replaceBits(PSTATE, 9, 9, PSTATE >> 8);
4613415Sgblack@eecs.umich.edu    }
4623415Sgblack@eecs.umich.edu    else
4633415Sgblack@eecs.umich.edu    {
4643415Sgblack@eecs.umich.edu        //PSTATE.priv = 0
4653746Sgblack@eecs.umich.edu        //PSTATE.priv is set to 1 here. The manual says it should be 0, but
4663746Sgblack@eecs.umich.edu        //Legion sets it to 1.
4673746Sgblack@eecs.umich.edu        PSTATE |= (1 << 2);
4683415Sgblack@eecs.umich.edu        //PSTATE.cle = 0
4693415Sgblack@eecs.umich.edu        PSTATE &= ~(1 << 9);
4703415Sgblack@eecs.umich.edu    }
4713415Sgblack@eecs.umich.edu    //PSTATE.ie = 0
4723415Sgblack@eecs.umich.edu    PSTATE &= ~(1 << 1);
4733415Sgblack@eecs.umich.edu    //PSTATE.tle is unchanged
4743415Sgblack@eecs.umich.edu    //PSTATE.tct = 0
4753415Sgblack@eecs.umich.edu    //XXX Where exactly is this field?
4763415Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
4773415Sgblack@eecs.umich.edu
4783578Sgblack@eecs.umich.edu    if(gotoHpriv)
4793415Sgblack@eecs.umich.edu    {
4803415Sgblack@eecs.umich.edu        //HPSTATE.red = 0
4813415Sgblack@eecs.umich.edu        HPSTATE &= ~(1 << 5);
4823415Sgblack@eecs.umich.edu        //HPSTATE.hpriv = 1
4833415Sgblack@eecs.umich.edu        HPSTATE |= (1 << 2);
4843415Sgblack@eecs.umich.edu        //HPSTATE.ibe = 0
4853415Sgblack@eecs.umich.edu        HPSTATE &= ~(1 << 10);
4863415Sgblack@eecs.umich.edu        //HPSTATE.tlz is unchanged
4873415Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
4883415Sgblack@eecs.umich.edu    }
4893415Sgblack@eecs.umich.edu
4903415Sgblack@eecs.umich.edu    bool changedCWP = true;
4913415Sgblack@eecs.umich.edu    if(tt == 0x24)
4923415Sgblack@eecs.umich.edu        CWP++;
4933415Sgblack@eecs.umich.edu    else if(0x80 <= tt && tt <= 0xbf)
4943415Sgblack@eecs.umich.edu        CWP += (CANSAVE + 2);
4953415Sgblack@eecs.umich.edu    else if(0xc0 <= tt && tt <= 0xff)
4963415Sgblack@eecs.umich.edu        CWP--;
4973415Sgblack@eecs.umich.edu    else
4983415Sgblack@eecs.umich.edu        changedCWP = false;
4993420Sgblack@eecs.umich.edu
5003415Sgblack@eecs.umich.edu    if(changedCWP)
5013415Sgblack@eecs.umich.edu    {
5023415Sgblack@eecs.umich.edu        CWP = (CWP + NWindows) % NWindows;
5033415Sgblack@eecs.umich.edu        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
5043415Sgblack@eecs.umich.edu    }
5053415Sgblack@eecs.umich.edu}
5063415Sgblack@eecs.umich.edu
5073595Sgblack@eecs.umich.eduvoid getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
5083578Sgblack@eecs.umich.edu{
5093585Sgblack@eecs.umich.edu    //XXX The following constant might belong in a header file.
5103603Ssaidi@eecs.umich.edu    const Addr RSTVAddr = 0xFFF0000000ULL;
5113595Sgblack@eecs.umich.edu    PC = RSTVAddr | ((TT << 5) & 0xFF);
5123578Sgblack@eecs.umich.edu    NPC = PC + sizeof(MachInst);
5133578Sgblack@eecs.umich.edu}
5143578Sgblack@eecs.umich.edu
5153585Sgblack@eecs.umich.eduvoid getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
5163578Sgblack@eecs.umich.edu{
5173585Sgblack@eecs.umich.edu    Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
5183578Sgblack@eecs.umich.edu    PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
5193578Sgblack@eecs.umich.edu    NPC = PC + sizeof(MachInst);
5203578Sgblack@eecs.umich.edu}
5213578Sgblack@eecs.umich.edu
5223585Sgblack@eecs.umich.eduvoid getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
5233578Sgblack@eecs.umich.edu{
5243585Sgblack@eecs.umich.edu    Addr TBA = tc->readMiscReg(MISCREG_TBA);
5253578Sgblack@eecs.umich.edu    PC = (TBA & ~mask(15)) |
5263578Sgblack@eecs.umich.edu        (TL > 1 ? (1 << 14) : 0) |
5273578Sgblack@eecs.umich.edu        ((TT << 5) & mask(14));
5283578Sgblack@eecs.umich.edu    NPC = PC + sizeof(MachInst);
5293578Sgblack@eecs.umich.edu}
5303578Sgblack@eecs.umich.edu
5312221SN/A#if FULL_SYSTEM
5322221SN/A
5333573Sgblack@eecs.umich.eduvoid SparcFaultBase::invoke(ThreadContext * tc)
5342221SN/A{
5353595Sgblack@eecs.umich.edu    panic("Invoking a second fault!\n");
5362680Sktlim@umich.edu    FaultBase::invoke(tc);
5372223SN/A    countStat()++;
5382221SN/A
5393578Sgblack@eecs.umich.edu    //We can refer to this to see what the trap level -was-, but something
5403578Sgblack@eecs.umich.edu    //in the middle could change it in the regfile out from under us.
5413578Sgblack@eecs.umich.edu    MiscReg TL = tc->readMiscReg(MISCREG_TL);
5423578Sgblack@eecs.umich.edu    MiscReg TT = tc->readMiscReg(MISCREG_TT);
5433578Sgblack@eecs.umich.edu    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
5443578Sgblack@eecs.umich.edu    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
5453578Sgblack@eecs.umich.edu
5463578Sgblack@eecs.umich.edu    Addr PC, NPC;
5473578Sgblack@eecs.umich.edu
5483578Sgblack@eecs.umich.edu    PrivilegeLevel current;
5493746Sgblack@eecs.umich.edu    if(HPSTATE & (1 << 2))
5503746Sgblack@eecs.umich.edu        current = Hyperprivileged;
5513746Sgblack@eecs.umich.edu    else if(PSTATE & (1 << 2))
5523578Sgblack@eecs.umich.edu        current = Privileged;
5533578Sgblack@eecs.umich.edu    else
5543746Sgblack@eecs.umich.edu        current = User;
5553578Sgblack@eecs.umich.edu
5563578Sgblack@eecs.umich.edu    PrivilegeLevel level = getNextLevel(current);
5573578Sgblack@eecs.umich.edu
5583578Sgblack@eecs.umich.edu    if(HPSTATE & (1 << 5) || TL == MaxTL - 1)
5593578Sgblack@eecs.umich.edu    {
5603595Sgblack@eecs.umich.edu        getREDVector(5, PC, NPC);
5613746Sgblack@eecs.umich.edu        doREDFault(tc, TT);
5623746Sgblack@eecs.umich.edu        //This changes the hpstate and pstate, so we need to make sure we
5633746Sgblack@eecs.umich.edu        //save the old version on the trap stack in doREDFault.
5643578Sgblack@eecs.umich.edu        enterREDState(tc);
5653578Sgblack@eecs.umich.edu    }
5663578Sgblack@eecs.umich.edu    else if(TL == MaxTL)
5673578Sgblack@eecs.umich.edu    {
5683578Sgblack@eecs.umich.edu        //Do error_state somehow?
5693578Sgblack@eecs.umich.edu        //Probably inject a WDR fault using the interrupt mechanism.
5703578Sgblack@eecs.umich.edu        //What should the PC and NPC be set to?
5713578Sgblack@eecs.umich.edu    }
5723578Sgblack@eecs.umich.edu    else if(TL > MaxPTL && level == Privileged)
5733578Sgblack@eecs.umich.edu    {
5743578Sgblack@eecs.umich.edu        //guest_watchdog fault
5753578Sgblack@eecs.umich.edu        doNormalFault(tc, trapType(), true);
5763585Sgblack@eecs.umich.edu        getHyperVector(tc, PC, NPC, 2);
5773578Sgblack@eecs.umich.edu    }
5783578Sgblack@eecs.umich.edu    else if(level == Hyperprivileged)
5793578Sgblack@eecs.umich.edu    {
5803578Sgblack@eecs.umich.edu        doNormalFault(tc, trapType(), true);
5813585Sgblack@eecs.umich.edu        getHyperVector(tc, PC, NPC, trapType());
5823578Sgblack@eecs.umich.edu    }
5833578Sgblack@eecs.umich.edu    else
5843578Sgblack@eecs.umich.edu    {
5853578Sgblack@eecs.umich.edu        doNormalFault(tc, trapType(), false);
5863585Sgblack@eecs.umich.edu        getPrivVector(tc, PC, NPC, trapType(), TL+1);
5873578Sgblack@eecs.umich.edu    }
5883578Sgblack@eecs.umich.edu
5893578Sgblack@eecs.umich.edu    tc->setPC(PC);
5903578Sgblack@eecs.umich.edu    tc->setNextPC(NPC);
5913578Sgblack@eecs.umich.edu    tc->setNextNPC(NPC + sizeof(MachInst));
5923420Sgblack@eecs.umich.edu}
5932221SN/A
5943523Sgblack@eecs.umich.eduvoid PowerOnReset::invoke(ThreadContext * tc)
5953523Sgblack@eecs.umich.edu{
5963523Sgblack@eecs.umich.edu    //For SPARC, when a system is first started, there is a power
5973523Sgblack@eecs.umich.edu    //on reset Trap which sets the processor into the following state.
5983523Sgblack@eecs.umich.edu    //Bits that aren't set aren't defined on startup.
5993595Sgblack@eecs.umich.edu
6003595Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TL, MaxTL);
6013595Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TT, trapType());
6023595Sgblack@eecs.umich.edu    tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
6033595Sgblack@eecs.umich.edu
6043746Sgblack@eecs.umich.edu    //Turn on pef and priv, set everything else to 0
6053746Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2));
6063595Sgblack@eecs.umich.edu
6073595Sgblack@eecs.umich.edu    //Turn on red and hpriv, set everything else to 0
6083628Sgblack@eecs.umich.edu    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
6093628Sgblack@eecs.umich.edu    //HPSTATE.red = 1
6103628Sgblack@eecs.umich.edu    HPSTATE |= (1 << 5);
6113628Sgblack@eecs.umich.edu    //HPSTATE.hpriv = 1
6123628Sgblack@eecs.umich.edu    HPSTATE |= (1 << 2);
6133628Sgblack@eecs.umich.edu    //HPSTATE.ibe = 0
6143628Sgblack@eecs.umich.edu    HPSTATE &= ~(1 << 10);
6153628Sgblack@eecs.umich.edu    //HPSTATE.tlz = 0
6163628Sgblack@eecs.umich.edu    HPSTATE &= ~(1 << 0);
6173628Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
6183595Sgblack@eecs.umich.edu
6193595Sgblack@eecs.umich.edu    //The tick register is unreadable by nonprivileged software
6203595Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
6213595Sgblack@eecs.umich.edu
6223746Sgblack@eecs.umich.edu    //Enter RED state. We do this last so that the actual state preserved in
6233746Sgblack@eecs.umich.edu    //the trap stack is the state from before this fault.
6243746Sgblack@eecs.umich.edu    enterREDState(tc);
6253746Sgblack@eecs.umich.edu
6263595Sgblack@eecs.umich.edu    Addr PC, NPC;
6273595Sgblack@eecs.umich.edu    getREDVector(trapType(), PC, NPC);
6283595Sgblack@eecs.umich.edu    tc->setPC(PC);
6293595Sgblack@eecs.umich.edu    tc->setNextPC(NPC);
6303595Sgblack@eecs.umich.edu    tc->setNextNPC(NPC + sizeof(MachInst));
6313595Sgblack@eecs.umich.edu
6323595Sgblack@eecs.umich.edu    //These registers are specified as "undefined" after a POR, and they
6333595Sgblack@eecs.umich.edu    //should have reasonable values after the miscregfile is reset
6343523Sgblack@eecs.umich.edu    /*
6353595Sgblack@eecs.umich.edu    // Clear all the soft interrupt bits
6363595Sgblack@eecs.umich.edu    softint = 0;
6373595Sgblack@eecs.umich.edu    // disable timer compare interrupts, reset tick_cmpr
6383595Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_
6393595Sgblack@eecs.umich.edu    tick_cmprFields.int_dis = 1;
6403523Sgblack@eecs.umich.edu    tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
6413523Sgblack@eecs.umich.edu    stickFields.npt = 1; //The TICK register is unreadable by by !priv
6423523Sgblack@eecs.umich.edu    stick_cmprFields.int_dis = 1; // disable timer compare interrupts
6433523Sgblack@eecs.umich.edu    stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
6443523Sgblack@eecs.umich.edu
6453523Sgblack@eecs.umich.edu    tt[tl] = _trapType;
6463523Sgblack@eecs.umich.edu
6473523Sgblack@eecs.umich.edu    hintp = 0; // no interrupts pending
6483523Sgblack@eecs.umich.edu    hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
6493523Sgblack@eecs.umich.edu    hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
6503523Sgblack@eecs.umich.edu    */
6512221SN/A}
6522221SN/A
6533578Sgblack@eecs.umich.edu#else // !FULL_SYSTEM
6542612SN/A
6553415Sgblack@eecs.umich.eduvoid SpillNNormal::invoke(ThreadContext *tc)
6563415Sgblack@eecs.umich.edu{
6573578Sgblack@eecs.umich.edu    doNormalFault(tc, trapType(), false);
6583415Sgblack@eecs.umich.edu
6593415Sgblack@eecs.umich.edu    Process *p = tc->getProcessPtr();
6603415Sgblack@eecs.umich.edu
6613578Sgblack@eecs.umich.edu    //XXX This will only work in faults from a SparcLiveProcess
6623415Sgblack@eecs.umich.edu    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
6633415Sgblack@eecs.umich.edu    assert(lp);
6643415Sgblack@eecs.umich.edu
6653415Sgblack@eecs.umich.edu    //Then adjust the PC and NPC
6663415Sgblack@eecs.umich.edu    Addr spillStart = lp->readSpillStart();
6673415Sgblack@eecs.umich.edu    tc->setPC(spillStart);
6683415Sgblack@eecs.umich.edu    tc->setNextPC(spillStart + sizeof(MachInst));
6693415Sgblack@eecs.umich.edu    tc->setNextNPC(spillStart + 2*sizeof(MachInst));
6703415Sgblack@eecs.umich.edu}
6713415Sgblack@eecs.umich.edu
6723415Sgblack@eecs.umich.eduvoid FillNNormal::invoke(ThreadContext *tc)
6733415Sgblack@eecs.umich.edu{
6743578Sgblack@eecs.umich.edu    doNormalFault(tc, trapType(), false);
6753415Sgblack@eecs.umich.edu
6763415Sgblack@eecs.umich.edu    Process * p = tc->getProcessPtr();
6773415Sgblack@eecs.umich.edu
6783578Sgblack@eecs.umich.edu    //XXX This will only work in faults from a SparcLiveProcess
6793415Sgblack@eecs.umich.edu    SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
6803415Sgblack@eecs.umich.edu    assert(lp);
6813415Sgblack@eecs.umich.edu
6823578Sgblack@eecs.umich.edu    //Then adjust the PC and NPC
6833415Sgblack@eecs.umich.edu    Addr fillStart = lp->readFillStart();
6843415Sgblack@eecs.umich.edu    tc->setPC(fillStart);
6853415Sgblack@eecs.umich.edu    tc->setNextPC(fillStart + sizeof(MachInst));
6863415Sgblack@eecs.umich.edu    tc->setNextNPC(fillStart + 2*sizeof(MachInst));
6873415Sgblack@eecs.umich.edu}
6883415Sgblack@eecs.umich.edu
6892800Ssaidi@eecs.umich.eduvoid PageTableFault::invoke(ThreadContext *tc)
6902800Ssaidi@eecs.umich.edu{
6912800Ssaidi@eecs.umich.edu    Process *p = tc->getProcessPtr();
6922800Ssaidi@eecs.umich.edu
6932800Ssaidi@eecs.umich.edu    // address is higher than the stack region or in the current stack region
6942800Ssaidi@eecs.umich.edu    if (vaddr > p->stack_base || vaddr > p->stack_min)
6952800Ssaidi@eecs.umich.edu        FaultBase::invoke(tc);
6962800Ssaidi@eecs.umich.edu
6972800Ssaidi@eecs.umich.edu    // We've accessed the next page
6982800Ssaidi@eecs.umich.edu    if (vaddr > p->stack_min - PageBytes) {
6992800Ssaidi@eecs.umich.edu        p->stack_min -= PageBytes;
7002800Ssaidi@eecs.umich.edu        if (p->stack_base - p->stack_min > 8*1024*1024)
7012800Ssaidi@eecs.umich.edu            fatal("Over max stack size for one thread\n");
7022800Ssaidi@eecs.umich.edu        p->pTable->allocate(p->stack_min, PageBytes);
7032800Ssaidi@eecs.umich.edu        warn("Increasing stack size by one page.");
7042800Ssaidi@eecs.umich.edu    } else {
7052800Ssaidi@eecs.umich.edu        FaultBase::invoke(tc);
7062800Ssaidi@eecs.umich.edu    }
7072800Ssaidi@eecs.umich.edu}
7083415Sgblack@eecs.umich.edu
7092221SN/A#endif
7102221SN/A
7112223SN/A} // namespace SparcISA
7122221SN/A
713