faults.cc revision 3523
16019Shines@cs.fsu.edu/* 211496Sandreas.sandberg@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 37093Sgblack@eecs.umich.edu * All rights reserved. 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67093Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77093Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87093Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97093Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107093Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117093Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127093Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137093Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Gabe Black 296019Shines@cs.fsu.edu * Kevin Lim 306019Shines@cs.fsu.edu */ 316019Shines@cs.fsu.edu 326019Shines@cs.fsu.edu#include <algorithm> 336019Shines@cs.fsu.edu 346019Shines@cs.fsu.edu#include "arch/sparc/faults.hh" 356019Shines@cs.fsu.edu#include "arch/sparc/isa_traits.hh" 366019Shines@cs.fsu.edu#include "base/bitfield.hh" 376019Shines@cs.fsu.edu#include "base/trace.hh" 386019Shines@cs.fsu.edu#include "config/full_system.hh" 396019Shines@cs.fsu.edu#include "cpu/base.hh" 406019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 416735Sgblack@eecs.umich.edu#if !FULL_SYSTEM 426735Sgblack@eecs.umich.edu#include "arch/sparc/process.hh" 4310037SARM gem5 Developers#include "mem/page_table.hh" 4410037SARM gem5 Developers#include "sim/process.hh" 456019Shines@cs.fsu.edu#endif 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.eduusing namespace std; 4810037SARM gem5 Developers 4910037SARM gem5 Developersnamespace SparcISA 5010037SARM gem5 Developers{ 5110037SARM gem5 Developers 528229Snate@binkert.orgFaultName InternalProcessorError::_name = "intprocerr"; 538229Snate@binkert.orgTrapType InternalProcessorError::_trapType = 0x029; 546019Shines@cs.fsu.eduFaultPriority InternalProcessorError::_priority = 4; 558232Snate@binkert.orgFaultStat InternalProcessorError::_count; 568782Sgblack@eecs.umich.edu 576019Shines@cs.fsu.eduFaultName MemAddressNotAligned::_name = "unalign"; 586019Shines@cs.fsu.eduTrapType MemAddressNotAligned::_trapType = 0x034; 596019Shines@cs.fsu.eduFaultPriority MemAddressNotAligned::_priority = 10; 606019Shines@cs.fsu.eduFaultStat MemAddressNotAligned::_count; 6110037SARM gem5 Developers 6210037SARM gem5 DevelopersFaultName PowerOnReset::_name = "pow_reset"; 6310037SARM gem5 DevelopersTrapType PowerOnReset::_trapType = 0x001; 6410037SARM gem5 DevelopersFaultPriority PowerOnReset::_priority = 0; 6510037SARM gem5 DevelopersFaultStat PowerOnReset::_count; 6610037SARM gem5 Developers 6710037SARM gem5 DevelopersFaultName WatchDogReset::_name = "watch_dog_reset"; 6810037SARM gem5 DevelopersTrapType WatchDogReset::_trapType = 0x002; 6910037SARM gem5 DevelopersFaultPriority WatchDogReset::_priority = 1; 7010037SARM gem5 DevelopersFaultStat WatchDogReset::_count; 7110037SARM gem5 Developers 7210037SARM gem5 DevelopersFaultName ExternallyInitiatedReset::_name = "extern_reset"; 7310037SARM gem5 DevelopersTrapType ExternallyInitiatedReset::_trapType = 0x003; 7410037SARM gem5 DevelopersFaultPriority ExternallyInitiatedReset::_priority = 1; 7510037SARM gem5 DevelopersFaultStat ExternallyInitiatedReset::_count; 7610037SARM gem5 Developers 7710037SARM gem5 DevelopersFaultName SoftwareInitiatedReset::_name = "software_reset"; 7810037SARM gem5 DevelopersTrapType SoftwareInitiatedReset::_trapType = 0x004; 7910037SARM gem5 DevelopersFaultPriority SoftwareInitiatedReset::_priority = 1; 8010037SARM gem5 DevelopersFaultStat SoftwareInitiatedReset::_count; 8110037SARM gem5 Developers 8210037SARM gem5 DevelopersFaultName REDStateException::_name = "red_counte"; 8310037SARM gem5 DevelopersTrapType REDStateException::_trapType = 0x005; 8410037SARM gem5 DevelopersFaultPriority REDStateException::_priority = 1; 8510037SARM gem5 DevelopersFaultStat REDStateException::_count; 8610037SARM gem5 Developers 8710037SARM gem5 DevelopersFaultName InstructionAccessException::_name = "inst_access"; 8810037SARM gem5 DevelopersTrapType InstructionAccessException::_trapType = 0x008; 8910037SARM gem5 DevelopersFaultPriority InstructionAccessException::_priority = 5; 9010037SARM gem5 DevelopersFaultStat InstructionAccessException::_count; 9110037SARM gem5 Developers 9210037SARM gem5 DevelopersFaultName InstructionAccessMMUMiss::_name = "inst_mmu"; 9310037SARM gem5 DevelopersTrapType InstructionAccessMMUMiss::_trapType = 0x009; 9410037SARM gem5 DevelopersFaultPriority InstructionAccessMMUMiss::_priority = 2; 9510037SARM gem5 DevelopersFaultStat InstructionAccessMMUMiss::_count; 9610037SARM gem5 Developers 9710037SARM gem5 DevelopersFaultName InstructionAccessError::_name = "inst_error"; 9810037SARM gem5 DevelopersTrapType InstructionAccessError::_trapType = 0x00A; 9910037SARM gem5 DevelopersFaultPriority InstructionAccessError::_priority = 3; 10010037SARM gem5 DevelopersFaultStat InstructionAccessError::_count; 1016019Shines@cs.fsu.edu 10210037SARM gem5 DevelopersFaultName IllegalInstruction::_name = "illegal_inst"; 10310037SARM gem5 DevelopersTrapType IllegalInstruction::_trapType = 0x010; 10410037SARM gem5 DevelopersFaultPriority IllegalInstruction::_priority = 7; 1056019Shines@cs.fsu.eduFaultStat IllegalInstruction::_count; 10610037SARM gem5 Developers 10710037SARM gem5 DevelopersFaultName PrivilegedOpcode::_name = "priv_opcode"; 10810037SARM gem5 DevelopersTrapType PrivilegedOpcode::_trapType = 0x011; 10910037SARM gem5 DevelopersFaultPriority PrivilegedOpcode::_priority = 6; 11010037SARM gem5 DevelopersFaultStat PrivilegedOpcode::_count; 11110037SARM gem5 Developers 11210037SARM gem5 DevelopersFaultName UnimplementedLDD::_name = "unimp_ldd"; 11310037SARM gem5 DevelopersTrapType UnimplementedLDD::_trapType = 0x012; 11410037SARM gem5 DevelopersFaultPriority UnimplementedLDD::_priority = 6; 11510037SARM gem5 DevelopersFaultStat UnimplementedLDD::_count; 11610037SARM gem5 Developers 11710037SARM gem5 DevelopersFaultName UnimplementedSTD::_name = "unimp_std"; 11810037SARM gem5 DevelopersTrapType UnimplementedSTD::_trapType = 0x013; 11910037SARM gem5 DevelopersFaultPriority UnimplementedSTD::_priority = 6; 12010037SARM gem5 DevelopersFaultStat UnimplementedSTD::_count; 12110037SARM gem5 Developers 12210037SARM gem5 DevelopersFaultName FpDisabled::_name = "fp_disabled"; 12310037SARM gem5 DevelopersTrapType FpDisabled::_trapType = 0x020; 12410037SARM gem5 DevelopersFaultPriority FpDisabled::_priority = 8; 12510037SARM gem5 DevelopersFaultStat FpDisabled::_count; 12610037SARM gem5 Developers 12710037SARM gem5 DevelopersFaultName FpExceptionIEEE754::_name = "fp_754"; 12810037SARM gem5 DevelopersTrapType FpExceptionIEEE754::_trapType = 0x021; 12910037SARM gem5 DevelopersFaultPriority FpExceptionIEEE754::_priority = 11; 13010037SARM gem5 DevelopersFaultStat FpExceptionIEEE754::_count; 13110037SARM gem5 Developers 13210037SARM gem5 DevelopersFaultName FpExceptionOther::_name = "fp_other"; 13310037SARM gem5 DevelopersTrapType FpExceptionOther::_trapType = 0x022; 13410037SARM gem5 DevelopersFaultPriority FpExceptionOther::_priority = 11; 13510037SARM gem5 DevelopersFaultStat FpExceptionOther::_count; 13610037SARM gem5 Developers 13710037SARM gem5 DevelopersFaultName TagOverflow::_name = "tag_overflow"; 13810037SARM gem5 DevelopersTrapType TagOverflow::_trapType = 0x023; 13910037SARM gem5 DevelopersFaultPriority TagOverflow::_priority = 14; 14010037SARM gem5 DevelopersFaultStat TagOverflow::_count; 14110037SARM gem5 Developers 14210037SARM gem5 DevelopersFaultName DivisionByZero::_name = "div_by_zero"; 14310037SARM gem5 DevelopersTrapType DivisionByZero::_trapType = 0x028; 14410037SARM gem5 DevelopersFaultPriority DivisionByZero::_priority = 15; 14510037SARM gem5 DevelopersFaultStat DivisionByZero::_count; 1466019Shines@cs.fsu.edu 14710037SARM gem5 DevelopersFaultName DataAccessException::_name = "data_access"; 14810037SARM gem5 DevelopersTrapType DataAccessException::_trapType = 0x030; 14910037SARM gem5 DevelopersFaultPriority DataAccessException::_priority = 12; 1506019Shines@cs.fsu.eduFaultStat DataAccessException::_count; 15110037SARM gem5 Developers 15210037SARM gem5 DevelopersFaultName DataAccessMMUMiss::_name = "data_mmu"; 15310037SARM gem5 DevelopersTrapType DataAccessMMUMiss::_trapType = 0x031; 15410037SARM gem5 DevelopersFaultPriority DataAccessMMUMiss::_priority = 12; 15510037SARM gem5 DevelopersFaultStat DataAccessMMUMiss::_count; 15610037SARM gem5 Developers 15710037SARM gem5 DevelopersFaultName DataAccessError::_name = "data_error"; 15810037SARM gem5 DevelopersTrapType DataAccessError::_trapType = 0x032; 15910037SARM gem5 DevelopersFaultPriority DataAccessError::_priority = 12; 16010037SARM gem5 DevelopersFaultStat DataAccessError::_count; 16110037SARM gem5 Developers 16210037SARM gem5 DevelopersFaultName DataAccessProtection::_name = "data_protection"; 16310037SARM gem5 DevelopersTrapType DataAccessProtection::_trapType = 0x033; 16410037SARM gem5 DevelopersFaultPriority DataAccessProtection::_priority = 12; 16510037SARM gem5 DevelopersFaultStat DataAccessProtection::_count; 16610037SARM gem5 Developers 16710037SARM gem5 DevelopersFaultName LDDFMemAddressNotAligned::_name = "unalign_lddf"; 16810037SARM gem5 DevelopersTrapType LDDFMemAddressNotAligned::_trapType = 0x035; 16910037SARM gem5 DevelopersFaultPriority LDDFMemAddressNotAligned::_priority = 10; 17010037SARM gem5 DevelopersFaultStat LDDFMemAddressNotAligned::_count; 17110037SARM gem5 Developers 17210037SARM gem5 DevelopersFaultName STDFMemAddressNotAligned::_name = "unalign_stdf"; 17310037SARM gem5 DevelopersTrapType STDFMemAddressNotAligned::_trapType = 0x036; 17410037SARM gem5 DevelopersFaultPriority STDFMemAddressNotAligned::_priority = 10; 17510037SARM gem5 DevelopersFaultStat STDFMemAddressNotAligned::_count; 17610037SARM gem5 Developers 17710037SARM gem5 DevelopersFaultName PrivilegedAction::_name = "priv_action"; 17810037SARM gem5 DevelopersTrapType PrivilegedAction::_trapType = 0x037; 17910037SARM gem5 DevelopersFaultPriority PrivilegedAction::_priority = 11; 18010037SARM gem5 DevelopersFaultStat PrivilegedAction::_count; 18110037SARM gem5 Developers 18210037SARM gem5 DevelopersFaultName LDQFMemAddressNotAligned::_name = "unalign_ldqf"; 18310037SARM gem5 DevelopersTrapType LDQFMemAddressNotAligned::_trapType = 0x038; 18410037SARM gem5 DevelopersFaultPriority LDQFMemAddressNotAligned::_priority = 10; 18510037SARM gem5 DevelopersFaultStat LDQFMemAddressNotAligned::_count; 18610037SARM gem5 Developers 18710037SARM gem5 DevelopersFaultName STQFMemAddressNotAligned::_name = "unalign_stqf"; 18810037SARM gem5 DevelopersTrapType STQFMemAddressNotAligned::_trapType = 0x039; 18910037SARM gem5 DevelopersFaultPriority STQFMemAddressNotAligned::_priority = 10; 19010037SARM gem5 DevelopersFaultStat STQFMemAddressNotAligned::_count; 19110037SARM gem5 Developers 1926019Shines@cs.fsu.eduFaultName AsyncDataError::_name = "async_data"; 19310037SARM gem5 DevelopersTrapType AsyncDataError::_trapType = 0x040; 19410037SARM gem5 DevelopersFaultPriority AsyncDataError::_priority = 2; 19510037SARM gem5 DevelopersFaultStat AsyncDataError::_count; 1966019Shines@cs.fsu.edu 19710037SARM gem5 DevelopersFaultName CleanWindow::_name = "clean_win"; 19810037SARM gem5 DevelopersTrapType CleanWindow::_trapType = 0x024; 19910037SARM gem5 DevelopersFaultPriority CleanWindow::_priority = 10; 20010037SARM gem5 DevelopersFaultStat CleanWindow::_count; 20110037SARM gem5 Developers 20210037SARM gem5 Developers//The enumerated faults 20310037SARM gem5 Developers 20410037SARM gem5 DevelopersFaultName InterruptLevelN::_name = "interrupt_n"; 20510037SARM gem5 DevelopersTrapType InterruptLevelN::_baseTrapType = 0x041; 20610037SARM gem5 DevelopersFaultStat InterruptLevelN::_count; 20710037SARM gem5 Developers 20810037SARM gem5 DevelopersFaultName SpillNNormal::_name = "spill_n_normal"; 20910037SARM gem5 DevelopersTrapType SpillNNormal::_baseTrapType = 0x080; 21010037SARM gem5 DevelopersFaultPriority SpillNNormal::_priority = 9; 21110037SARM gem5 DevelopersFaultStat SpillNNormal::_count; 21210037SARM gem5 Developers 21310037SARM gem5 DevelopersFaultName SpillNOther::_name = "spill_n_other"; 21410037SARM gem5 DevelopersTrapType SpillNOther::_baseTrapType = 0x0A0; 21510037SARM gem5 DevelopersFaultPriority SpillNOther::_priority = 9; 21610037SARM gem5 DevelopersFaultStat SpillNOther::_count; 21710037SARM gem5 Developers 21810037SARM gem5 DevelopersFaultName FillNNormal::_name = "fill_n_normal"; 21910037SARM gem5 DevelopersTrapType FillNNormal::_baseTrapType = 0x0C0; 22010037SARM gem5 DevelopersFaultPriority FillNNormal::_priority = 9; 22110037SARM gem5 DevelopersFaultStat FillNNormal::_count; 22210037SARM gem5 Developers 22310037SARM gem5 DevelopersFaultName FillNOther::_name = "fill_n_other"; 22410037SARM gem5 DevelopersTrapType FillNOther::_baseTrapType = 0x0E0; 22510037SARM gem5 DevelopersFaultPriority FillNOther::_priority = 9; 22610037SARM gem5 DevelopersFaultStat FillNOther::_count; 22710037SARM gem5 Developers 22810037SARM gem5 DevelopersFaultName TrapInstruction::_name = "trap_inst_n"; 22910037SARM gem5 DevelopersTrapType TrapInstruction::_baseTrapType = 0x100; 23010037SARM gem5 DevelopersFaultPriority TrapInstruction::_priority = 16; 23110037SARM gem5 DevelopersFaultStat TrapInstruction::_count; 23210037SARM gem5 Developers 23310037SARM gem5 Developers#if !FULL_SYSTEM 23410037SARM gem5 DevelopersFaultName PageTableFault::_name = "page_table_fault"; 23510037SARM gem5 DevelopersTrapType PageTableFault::_trapType = 0x0000; 23610037SARM gem5 DevelopersFaultPriority PageTableFault::_priority = 0; 23710037SARM gem5 DevelopersFaultStat PageTableFault::_count; 23810037SARM gem5 Developers#endif 23910037SARM gem5 Developers 24010037SARM gem5 Developers/** 24110037SARM gem5 Developers * This sets everything up for a normal trap except for actually jumping to 24210037SARM gem5 Developers * the handler. It will need to be expanded to include the state machine in 24310037SARM gem5 Developers * the manual. Right now it assumes that traps will always be to the 24410037SARM gem5 Developers * privileged level. 24510037SARM gem5 Developers */ 24610037SARM gem5 Developers 24710037SARM gem5 Developersvoid doNormalFault(ThreadContext *tc, TrapType tt) 24810037SARM gem5 Developers{ 24910037SARM gem5 Developers uint64_t TL = tc->readMiscReg(MISCREG_TL); 25010037SARM gem5 Developers uint64_t TSTATE = tc->readMiscReg(MISCREG_TSTATE); 25110037SARM gem5 Developers uint64_t PSTATE = tc->readMiscReg(MISCREG_PSTATE); 25210037SARM gem5 Developers uint64_t HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); 25310037SARM gem5 Developers uint64_t CCR = tc->readMiscReg(MISCREG_CCR); 25410037SARM gem5 Developers uint64_t ASI = tc->readMiscReg(MISCREG_ASI); 25510037SARM gem5 Developers uint64_t CWP = tc->readMiscReg(MISCREG_CWP); 25610037SARM gem5 Developers uint64_t CANSAVE = tc->readMiscReg(MISCREG_CANSAVE); 25710037SARM gem5 Developers uint64_t GL = tc->readMiscReg(MISCREG_GL); 25810037SARM gem5 Developers uint64_t PC = tc->readPC(); 25910037SARM gem5 Developers uint64_t NPC = tc->readNextPC(); 26010037SARM gem5 Developers 26110037SARM gem5 Developers //Increment the trap level 26210037SARM gem5 Developers TL++; 26310037SARM gem5 Developers tc->setMiscReg(MISCREG_TL, TL); 26410037SARM gem5 Developers 26510037SARM gem5 Developers //Save off state 26610037SARM gem5 Developers 26710037SARM gem5 Developers //set TSTATE.gl to gl 26810037SARM gem5 Developers replaceBits(TSTATE, 42, 40, GL); 26910037SARM gem5 Developers //set TSTATE.ccr to ccr 27010037SARM gem5 Developers replaceBits(TSTATE, 39, 32, CCR); 27110037SARM gem5 Developers //set TSTATE.asi to asi 27210037SARM gem5 Developers replaceBits(TSTATE, 31, 24, ASI); 27310037SARM gem5 Developers //set TSTATE.pstate to pstate 27410037SARM gem5 Developers replaceBits(TSTATE, 20, 8, PSTATE); 27510037SARM gem5 Developers //set TSTATE.cwp to cwp 27610037SARM gem5 Developers replaceBits(TSTATE, 4, 0, CWP); 27710037SARM gem5 Developers 27810037SARM gem5 Developers //Write back TSTATE 27910037SARM gem5 Developers tc->setMiscReg(MISCREG_TSTATE, TSTATE); 28010037SARM gem5 Developers 28110037SARM gem5 Developers //set TPC to PC 28210037SARM gem5 Developers tc->setMiscReg(MISCREG_TPC, PC); 28310037SARM gem5 Developers //set TNPC to NPC 28410037SARM gem5 Developers tc->setMiscReg(MISCREG_TNPC, NPC); 28510037SARM gem5 Developers 28610037SARM gem5 Developers //set HTSTATE.hpstate to hpstate 28710037SARM gem5 Developers tc->setMiscReg(MISCREG_HTSTATE, HPSTATE); 28810037SARM gem5 Developers 28910037SARM gem5 Developers //TT = trap type; 29010037SARM gem5 Developers tc->setMiscReg(MISCREG_TT, tt); 29110037SARM gem5 Developers 29210037SARM gem5 Developers //Update the global register level 29310037SARM gem5 Developers if(1/*We're delivering the trap in priveleged mode*/) 29410037SARM gem5 Developers tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxGL)); 2956019Shines@cs.fsu.edu else 29610037SARM gem5 Developers tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxPGL)); 2977362Sgblack@eecs.umich.edu 2986735Sgblack@eecs.umich.edu //PSTATE.mm is unchanged 29910037SARM gem5 Developers //PSTATE.pef = whether or not an fpu is present 3006019Shines@cs.fsu.edu //XXX We'll say there's one present, even though there aren't 30110037SARM gem5 Developers //implementations for a decent number of the instructions 30210037SARM gem5 Developers PSTATE |= (1 << 4); 3037400SAli.Saidi@ARM.com //PSTATE.am = 0 3046735Sgblack@eecs.umich.edu PSTATE &= ~(1 << 3); 3056735Sgblack@eecs.umich.edu if(1/*We're delivering the trap in priveleged mode*/) 30610037SARM gem5 Developers { 3076735Sgblack@eecs.umich.edu //PSTATE.priv = 1 30810037SARM gem5 Developers PSTATE |= (1 << 2); 30910037SARM gem5 Developers //PSTATE.cle = PSTATE.tle 31010037SARM gem5 Developers replaceBits(PSTATE, 9, 9, PSTATE >> 8); 31110037SARM gem5 Developers } 3127400SAli.Saidi@ARM.com else 31310037SARM gem5 Developers { 31410037SARM gem5 Developers //PSTATE.priv = 0 31510037SARM gem5 Developers PSTATE &= ~(1 << 2); 31610037SARM gem5 Developers //PSTATE.cle = 0 31710037SARM gem5 Developers PSTATE &= ~(1 << 9); 31810037SARM gem5 Developers } 31910037SARM gem5 Developers //PSTATE.ie = 0 32010037SARM gem5 Developers PSTATE &= ~(1 << 1); 32110037SARM gem5 Developers //PSTATE.tle is unchanged 32210037SARM gem5 Developers //PSTATE.tct = 0 32310037SARM gem5 Developers //XXX Where exactly is this field? 32410037SARM gem5 Developers tc->setMiscReg(MISCREG_PSTATE, PSTATE); 32510037SARM gem5 Developers 32610037SARM gem5 Developers if(0/*We're delivering the trap in hyperprivileged mode*/) 32710037SARM gem5 Developers { 32810037SARM gem5 Developers //HPSTATE.red = 0 32910037SARM gem5 Developers HPSTATE &= ~(1 << 5); 3306019Shines@cs.fsu.edu //HPSTATE.hpriv = 1 3316019Shines@cs.fsu.edu HPSTATE |= (1 << 2); 33210037SARM gem5 Developers //HPSTATE.ibe = 0 33310037SARM gem5 Developers HPSTATE &= ~(1 << 10); 33410037SARM gem5 Developers //HPSTATE.tlz is unchanged 33510037SARM gem5 Developers tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); 33610037SARM gem5 Developers } 33710037SARM gem5 Developers 33810037SARM gem5 Developers bool changedCWP = true; 33910037SARM gem5 Developers if(tt == 0x24) 34010037SARM gem5 Developers CWP++; 34111574SCurtis.Dunham@arm.com else if(0x80 <= tt && tt <= 0xbf) 34211574SCurtis.Dunham@arm.com CWP += (CANSAVE + 2); 34311574SCurtis.Dunham@arm.com else if(0xc0 <= tt && tt <= 0xff) 34411574SCurtis.Dunham@arm.com CWP--; 34510037SARM gem5 Developers else 34610037SARM gem5 Developers changedCWP = false; 34710037SARM gem5 Developers 34810037SARM gem5 Developers if(changedCWP) 34910037SARM gem5 Developers { 35010037SARM gem5 Developers CWP = (CWP + NWindows) % NWindows; 35110037SARM gem5 Developers tc->setMiscRegWithEffect(MISCREG_CWP, CWP); 35210037SARM gem5 Developers } 35310037SARM gem5 Developers} 35410037SARM gem5 Developers 35510037SARM gem5 Developers#if FULL_SYSTEM 35610037SARM gem5 Developers 35710037SARM gem5 Developersvoid SparcFault::invoke(ThreadContext * tc) 35810037SARM gem5 Developers{ 35910037SARM gem5 Developers FaultBase::invoke(tc); 36010037SARM gem5 Developers countStat()++; 36110037SARM gem5 Developers 36210037SARM gem5 Developers //Use the SPARC trap state machine 36310037SARM gem5 Developers} 36410037SARM gem5 Developers 36510037SARM gem5 Developersvoid PowerOnReset::invoke(ThreadContext * tc) 36610037SARM gem5 Developers{ 36710037SARM gem5 Developers //For SPARC, when a system is first started, there is a power 36810037SARM gem5 Developers //on reset Trap which sets the processor into the following state. 36910037SARM gem5 Developers //Bits that aren't set aren't defined on startup. 37010037SARM gem5 Developers /* 37110037SARM gem5 Developers tl = MaxTL; 37210037SARM gem5 Developers gl = MaxGL; 37310037SARM gem5 Developers 37410037SARM gem5 Developers tickFields.counter = 0; //The TICK register is unreadable bya 37510037SARM gem5 Developers tickFields.npt = 1; //The TICK register is unreadable by by !priv 37610037SARM gem5 Developers 37710037SARM gem5 Developers softint = 0; // Clear all the soft interrupt bits 37810037SARM gem5 Developers tick_cmprFields.int_dis = 1; // disable timer compare interrupts 37910037SARM gem5 Developers tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 38010037SARM gem5 Developers stickFields.npt = 1; //The TICK register is unreadable by by !priv 38110037SARM gem5 Developers stick_cmprFields.int_dis = 1; // disable timer compare interrupts 38210037SARM gem5 Developers stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 38310037SARM gem5 Developers 38410037SARM gem5 Developers tt[tl] = _trapType; 38510037SARM gem5 Developers pstate = 0; // fields 0 but pef 38610037SARM gem5 Developers pstateFields.pef = 1; 38710037SARM gem5 Developers 38810037SARM gem5 Developers hpstate = 0; 38910037SARM gem5 Developers hpstateFields.red = 1; 39010037SARM gem5 Developers hpstateFields.hpriv = 1; 39110037SARM gem5 Developers hpstateFields.tlz = 0; // this is a guess 39210037SARM gem5 Developers hintp = 0; // no interrupts pending 39310037SARM gem5 Developers hstick_cmprFields.int_dis = 1; // disable timer compare interrupts 39410037SARM gem5 Developers hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 39510037SARM gem5 Developers */ 39610037SARM gem5 Developers} 39710037SARM gem5 Developers 39810037SARM gem5 Developers#endif 39910037SARM gem5 Developers 40010037SARM gem5 Developers#if !FULL_SYSTEM 40110037SARM gem5 Developers 40210037SARM gem5 Developersvoid TrapInstruction::invoke(ThreadContext * tc) 40310037SARM gem5 Developers{ 40410037SARM gem5 Developers // Should be handled in ISA. 40510037SARM gem5 Developers} 40610037SARM gem5 Developers 40710037SARM gem5 Developersvoid SpillNNormal::invoke(ThreadContext *tc) 40810037SARM gem5 Developers{ 40910037SARM gem5 Developers doNormalFault(tc, trapType()); 41010037SARM gem5 Developers 41110037SARM gem5 Developers Process *p = tc->getProcessPtr(); 41210037SARM gem5 Developers 41310037SARM gem5 Developers //This will only work in faults from a SparcLiveProcess 41410037SARM gem5 Developers SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 41510037SARM gem5 Developers assert(lp); 41610037SARM gem5 Developers 41710037SARM gem5 Developers //Then adjust the PC and NPC 41810037SARM gem5 Developers Addr spillStart = lp->readSpillStart(); 41910037SARM gem5 Developers tc->setPC(spillStart); 42010037SARM gem5 Developers tc->setNextPC(spillStart + sizeof(MachInst)); 42110037SARM gem5 Developers tc->setNextNPC(spillStart + 2*sizeof(MachInst)); 42210037SARM gem5 Developers} 42310037SARM gem5 Developers 42410037SARM gem5 Developersvoid FillNNormal::invoke(ThreadContext *tc) 42510037SARM gem5 Developers{ 42610037SARM gem5 Developers doNormalFault(tc, trapType()); 42710037SARM gem5 Developers 42810417Sandreas.hansson@arm.com Process * p = tc->getProcessPtr(); 4296019Shines@cs.fsu.edu 43010037SARM gem5 Developers //This will only work in faults from a SparcLiveProcess 43110037SARM gem5 Developers SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 43210037SARM gem5 Developers assert(lp); 43310037SARM gem5 Developers 43410037SARM gem5 Developers //The adjust the PC and NPC 43510037SARM gem5 Developers Addr fillStart = lp->readFillStart(); 43610037SARM gem5 Developers tc->setPC(fillStart); 43710037SARM gem5 Developers tc->setNextPC(fillStart + sizeof(MachInst)); 43810037SARM gem5 Developers tc->setNextNPC(fillStart + 2*sizeof(MachInst)); 43910037SARM gem5 Developers} 44010037SARM gem5 Developers 44110037SARM gem5 Developersvoid PageTableFault::invoke(ThreadContext *tc) 44211578SDylan.Johnson@ARM.com{ 44311578SDylan.Johnson@ARM.com Process *p = tc->getProcessPtr(); 44410037SARM gem5 Developers 44510037SARM gem5 Developers // address is higher than the stack region or in the current stack region 44610037SARM gem5 Developers if (vaddr > p->stack_base || vaddr > p->stack_min) 44710037SARM gem5 Developers FaultBase::invoke(tc); 44810037SARM gem5 Developers 44910037SARM gem5 Developers // We've accessed the next page 45010037SARM gem5 Developers if (vaddr > p->stack_min - PageBytes) { 45110037SARM gem5 Developers p->stack_min -= PageBytes; 45210037SARM gem5 Developers if (p->stack_base - p->stack_min > 8*1024*1024) 45310037SARM gem5 Developers fatal("Over max stack size for one thread\n"); 45410037SARM gem5 Developers p->pTable->allocate(p->stack_min, PageBytes); 45510037SARM gem5 Developers warn("Increasing stack size by one page."); 45610037SARM gem5 Developers } else { 45710037SARM gem5 Developers FaultBase::invoke(tc); 45810037SARM gem5 Developers } 45910037SARM gem5 Developers} 46010037SARM gem5 Developers 46110037SARM gem5 Developers#endif 4626735Sgblack@eecs.umich.edu 4638782Sgblack@eecs.umich.edu} // namespace SparcISA 4648782Sgblack@eecs.umich.edu 4656735Sgblack@eecs.umich.edu