faults.cc revision 2719
12221SN/A/*
22221SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32221SN/A * All rights reserved.
42221SN/A *
52221SN/A * Redistribution and use in source and binary forms, with or without
62221SN/A * modification, are permitted provided that the following conditions are
72221SN/A * met: redistributions of source code must retain the above copyright
82221SN/A * notice, this list of conditions and the following disclaimer;
92221SN/A * redistributions in binary form must reproduce the above copyright
102221SN/A * notice, this list of conditions and the following disclaimer in the
112221SN/A * documentation and/or other materials provided with the distribution;
122221SN/A * neither the name of the copyright holders nor the names of its
132221SN/A * contributors may be used to endorse or promote products derived from
142221SN/A * this software without specific prior written permission.
152221SN/A *
162221SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172221SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182221SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192221SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202221SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212221SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222221SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232221SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242221SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252221SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262221SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Gabe Black
292665Ssaidi@eecs.umich.edu *          Kevin Lim
302221SN/A */
312221SN/A
322223SN/A#include "arch/sparc/faults.hh"
332680Sktlim@umich.edu#include "cpu/thread_context.hh"
342221SN/A#include "cpu/base.hh"
352221SN/A#include "base/trace.hh"
362221SN/A
372223SN/Anamespace SparcISA
382221SN/A{
392221SN/A
402223SN/AFaultName     InternalProcessorError::_name = "intprocerr";
412223SN/ATrapType      InternalProcessorError::_trapType = 0x029;
422223SN/AFaultPriority InternalProcessorError::_priority = 4;
432223SN/AFaultStat     InternalProcessorError::_count;
442221SN/A
452223SN/AFaultName     MemAddressNotAligned::_name = "unalign";
462223SN/ATrapType      MemAddressNotAligned::_trapType = 0x034;
472223SN/AFaultPriority MemAddressNotAligned::_priority = 10;
482223SN/AFaultStat     MemAddressNotAligned::_count;
492221SN/A
502223SN/AFaultName     PowerOnReset::_name = "pow_reset";
512223SN/ATrapType      PowerOnReset::_trapType = 0x001;
522223SN/AFaultPriority PowerOnReset::_priority = 0;
532223SN/AFaultStat     PowerOnReset::_count;
542221SN/A
552223SN/AFaultName     WatchDogReset::_name = "watch_dog_reset";
562223SN/ATrapType      WatchDogReset::_trapType = 0x002;
572223SN/AFaultPriority WatchDogReset::_priority = 1;
582223SN/AFaultStat     WatchDogReset::_count;
592221SN/A
602223SN/AFaultName     ExternallyInitiatedReset::_name = "extern_reset";
612223SN/ATrapType      ExternallyInitiatedReset::_trapType = 0x003;
622223SN/AFaultPriority ExternallyInitiatedReset::_priority = 1;
632223SN/AFaultStat     ExternallyInitiatedReset::_count;
642221SN/A
652223SN/AFaultName     SoftwareInitiatedReset::_name = "software_reset";
662223SN/ATrapType      SoftwareInitiatedReset::_trapType = 0x004;
672223SN/AFaultPriority SoftwareInitiatedReset::_priority = 1;
682223SN/AFaultStat     SoftwareInitiatedReset::_count;
692221SN/A
702223SN/AFaultName     REDStateException::_name = "red_counte";
712223SN/ATrapType      REDStateException::_trapType = 0x005;
722223SN/AFaultPriority REDStateException::_priority = 1;
732223SN/AFaultStat     REDStateException::_count;
742221SN/A
752223SN/AFaultName     InstructionAccessException::_name = "inst_access";
762223SN/ATrapType      InstructionAccessException::_trapType = 0x008;
772223SN/AFaultPriority InstructionAccessException::_priority = 5;
782223SN/AFaultStat     InstructionAccessException::_count;
792221SN/A
802223SN/AFaultName     InstructionAccessMMUMiss::_name = "inst_mmu";
812223SN/ATrapType      InstructionAccessMMUMiss::_trapType = 0x009;
822223SN/AFaultPriority InstructionAccessMMUMiss::_priority = 2;
832223SN/AFaultStat     InstructionAccessMMUMiss::_count;
842221SN/A
852223SN/AFaultName     InstructionAccessError::_name = "inst_error";
862223SN/ATrapType      InstructionAccessError::_trapType = 0x00A;
872223SN/AFaultPriority InstructionAccessError::_priority = 3;
882223SN/AFaultStat     InstructionAccessError::_count;
892221SN/A
902223SN/AFaultName     IllegalInstruction::_name = "illegal_inst";
912223SN/ATrapType      IllegalInstruction::_trapType = 0x010;
922223SN/AFaultPriority IllegalInstruction::_priority = 7;
932223SN/AFaultStat     IllegalInstruction::_count;
942221SN/A
952469SN/AFaultName     PrivilegedOpcode::_name = "priv_opcode";
962469SN/ATrapType      PrivilegedOpcode::_trapType = 0x011;
972469SN/AFaultPriority PrivilegedOpcode::_priority = 6;
982469SN/AFaultStat     PrivilegedOpcode::_count;
992221SN/A
1002223SN/AFaultName     UnimplementedLDD::_name = "unimp_ldd";
1012223SN/ATrapType      UnimplementedLDD::_trapType = 0x012;
1022223SN/AFaultPriority UnimplementedLDD::_priority = 6;
1032223SN/AFaultStat     UnimplementedLDD::_count;
1042221SN/A
1052223SN/AFaultName     UnimplementedSTD::_name = "unimp_std";
1062223SN/ATrapType      UnimplementedSTD::_trapType = 0x013;
1072223SN/AFaultPriority UnimplementedSTD::_priority = 6;
1082223SN/AFaultStat     UnimplementedSTD::_count;
1092221SN/A
1102223SN/AFaultName     FpDisabled::_name = "fp_disabled";
1112223SN/ATrapType      FpDisabled::_trapType = 0x020;
1122223SN/AFaultPriority FpDisabled::_priority = 8;
1132223SN/AFaultStat     FpDisabled::_count;
1142221SN/A
1152223SN/AFaultName     FpExceptionIEEE754::_name = "fp_754";
1162223SN/ATrapType      FpExceptionIEEE754::_trapType = 0x021;
1172223SN/AFaultPriority FpExceptionIEEE754::_priority = 11;
1182223SN/AFaultStat     FpExceptionIEEE754::_count;
1192223SN/A
1202223SN/AFaultName     FpExceptionOther::_name = "fp_other";
1212223SN/ATrapType      FpExceptionOther::_trapType = 0x022;
1222223SN/AFaultPriority FpExceptionOther::_priority = 11;
1232223SN/AFaultStat     FpExceptionOther::_count;
1242223SN/A
1252223SN/AFaultName     TagOverflow::_name = "tag_overflow";
1262223SN/ATrapType      TagOverflow::_trapType = 0x023;
1272223SN/AFaultPriority TagOverflow::_priority = 14;
1282223SN/AFaultStat     TagOverflow::_count;
1292223SN/A
1302223SN/AFaultName     DivisionByZero::_name = "div_by_zero";
1312223SN/ATrapType      DivisionByZero::_trapType = 0x028;
1322223SN/AFaultPriority DivisionByZero::_priority = 15;
1332223SN/AFaultStat     DivisionByZero::_count;
1342223SN/A
1352223SN/AFaultName     DataAccessException::_name = "data_access";
1362223SN/ATrapType      DataAccessException::_trapType = 0x030;
1372223SN/AFaultPriority DataAccessException::_priority = 12;
1382223SN/AFaultStat     DataAccessException::_count;
1392223SN/A
1402223SN/AFaultName     DataAccessMMUMiss::_name = "data_mmu";
1412223SN/ATrapType      DataAccessMMUMiss::_trapType = 0x031;
1422223SN/AFaultPriority DataAccessMMUMiss::_priority = 12;
1432223SN/AFaultStat     DataAccessMMUMiss::_count;
1442223SN/A
1452223SN/AFaultName     DataAccessError::_name = "data_error";
1462223SN/ATrapType      DataAccessError::_trapType = 0x032;
1472223SN/AFaultPriority DataAccessError::_priority = 12;
1482223SN/AFaultStat     DataAccessError::_count;
1492223SN/A
1502223SN/AFaultName     DataAccessProtection::_name = "data_protection";
1512223SN/ATrapType      DataAccessProtection::_trapType = 0x033;
1522223SN/AFaultPriority DataAccessProtection::_priority = 12;
1532223SN/AFaultStat     DataAccessProtection::_count;
1542223SN/A
1552223SN/AFaultName     LDDFMemAddressNotAligned::_name = "unalign_lddf";
1562223SN/ATrapType      LDDFMemAddressNotAligned::_trapType = 0x035;
1572223SN/AFaultPriority LDDFMemAddressNotAligned::_priority = 10;
1582223SN/AFaultStat     LDDFMemAddressNotAligned::_count;
1592223SN/A
1602223SN/AFaultName     STDFMemAddressNotAligned::_name = "unalign_stdf";
1612223SN/ATrapType      STDFMemAddressNotAligned::_trapType = 0x036;
1622223SN/AFaultPriority STDFMemAddressNotAligned::_priority = 10;
1632223SN/AFaultStat     STDFMemAddressNotAligned::_count;
1642223SN/A
1652469SN/AFaultName     PrivilegedAction::_name = "priv_action";
1662469SN/ATrapType      PrivilegedAction::_trapType = 0x037;
1672469SN/AFaultPriority PrivilegedAction::_priority = 11;
1682469SN/AFaultStat     PrivilegedAction::_count;
1692223SN/A
1702223SN/AFaultName     LDQFMemAddressNotAligned::_name = "unalign_ldqf";
1712223SN/ATrapType      LDQFMemAddressNotAligned::_trapType = 0x038;
1722223SN/AFaultPriority LDQFMemAddressNotAligned::_priority = 10;
1732223SN/AFaultStat     LDQFMemAddressNotAligned::_count;
1742223SN/A
1752223SN/AFaultName     STQFMemAddressNotAligned::_name = "unalign_stqf";
1762223SN/ATrapType      STQFMemAddressNotAligned::_trapType = 0x039;
1772223SN/AFaultPriority STQFMemAddressNotAligned::_priority = 10;
1782223SN/AFaultStat     STQFMemAddressNotAligned::_count;
1792223SN/A
1802223SN/AFaultName     AsyncDataError::_name = "async_data";
1812223SN/ATrapType      AsyncDataError::_trapType = 0x040;
1822223SN/AFaultPriority AsyncDataError::_priority = 2;
1832223SN/AFaultStat     AsyncDataError::_count;
1842223SN/A
1852223SN/AFaultName     CleanWindow::_name = "clean_win";
1862527SN/ATrapType      CleanWindow::_trapType = 0x024;
1872223SN/AFaultPriority CleanWindow::_priority = 10;
1882223SN/AFaultStat     CleanWindow::_count;
1892223SN/A
1902527SN/A//The enumerated faults
1912527SN/A
1922223SN/AFaultName     InterruptLevelN::_name = "interrupt_n";
1932223SN/ATrapType      InterruptLevelN::_baseTrapType = 0x041;
1942223SN/AFaultStat     InterruptLevelN::_count;
1952223SN/A
1962223SN/AFaultName     SpillNNormal::_name = "spill_n_normal";
1972223SN/ATrapType      SpillNNormal::_baseTrapType = 0x080;
1982223SN/AFaultPriority SpillNNormal::_priority = 9;
1992223SN/AFaultStat     SpillNNormal::_count;
2002223SN/A
2012223SN/AFaultName     SpillNOther::_name = "spill_n_other";
2022223SN/ATrapType      SpillNOther::_baseTrapType = 0x0A0;
2032223SN/AFaultPriority SpillNOther::_priority = 9;
2042223SN/AFaultStat     SpillNOther::_count;
2052223SN/A
2062223SN/AFaultName     FillNNormal::_name = "fill_n_normal";
2072223SN/ATrapType      FillNNormal::_baseTrapType = 0x0C0;
2082223SN/AFaultPriority FillNNormal::_priority = 9;
2092223SN/AFaultStat     FillNNormal::_count;
2102223SN/A
2112223SN/AFaultName     FillNOther::_name = "fill_n_other";
2122223SN/ATrapType      FillNOther::_baseTrapType = 0x0E0;
2132223SN/AFaultPriority FillNOther::_priority = 9;
2142223SN/AFaultStat     FillNOther::_count;
2152223SN/A
2162223SN/AFaultName     TrapInstruction::_name = "trap_inst_n";
2172223SN/ATrapType      TrapInstruction::_baseTrapType = 0x100;
2182223SN/AFaultPriority TrapInstruction::_priority = 16;
2192223SN/AFaultStat     TrapInstruction::_count;
2202223SN/A
2212221SN/A#if FULL_SYSTEM
2222221SN/A
2232680Sktlim@umich.eduvoid SparcFault::invoke(ThreadContext * tc)
2242221SN/A{
2252680Sktlim@umich.edu    FaultBase::invoke(tc);
2262223SN/A    countStat()++;
2272221SN/A
2282223SN/A    //Use the SPARC trap state machine
2292223SN/A    /*// exception restart address
2302680Sktlim@umich.edu    if (setRestartAddress() || !tc->inPalMode())
2312680Sktlim@umich.edu        tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->regs.pc);
2322221SN/A
2332221SN/A    if (skipFaultingInstruction()) {
2342221SN/A        // traps...  skip faulting instruction.
2352680Sktlim@umich.edu        tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
2362680Sktlim@umich.edu                   tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
2372221SN/A    }
2382221SN/A
2392680Sktlim@umich.edu    if (!tc->inPalMode())
2402680Sktlim@umich.edu        AlphaISA::swap_palshadow(&(tc->regs), true);
2412221SN/A
2422680Sktlim@umich.edu    tc->regs.pc = tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
2432680Sktlim@umich.edu    tc->regs.npc = tc->regs.pc + sizeof(MachInst);*/
2442221SN/A}
2452221SN/A
2462612SN/A#endif
2472612SN/A
2482612SN/A#if !FULL_SYSTEM
2492612SN/A
2502680Sktlim@umich.eduvoid TrapInstruction::invoke(ThreadContext * tc)
2512523SN/A{
2522719Sktlim@umich.edu    // Should be handled in ISA.
2532523SN/A}
2542523SN/A
2552221SN/A#endif
2562221SN/A
2572223SN/A} // namespace SparcISA
2582221SN/A
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