faults.cc revision 2222 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/alpha/faults.hh"
30#include "cpu/exec_context.hh"
31#include "cpu/base.hh"
32#include "base/trace.hh"
33#include "kern/kernel_stats.hh"
34
35namespace AlphaISA
36{
37
38FaultName MachineCheckFault::_name = "mchk";
39FaultVect MachineCheckFault::_vect = 0x0401;
40FaultStat MachineCheckFault::_stat;
41
42FaultName AlignmentFault::_name = "unalign";
43FaultVect AlignmentFault::_vect = 0x0301;
44FaultStat AlignmentFault::_stat;
45
46FaultName ResetFault::_name = "reset";
47FaultVect ResetFault::_vect = 0x0001;
48FaultStat ResetFault::_stat;
49
50FaultName ArithmeticFault::_name = "arith";
51FaultVect ArithmeticFault::_vect = 0x0501;
52FaultStat ArithmeticFault::_stat;
53
54FaultName InterruptFault::_name = "interrupt";
55FaultVect InterruptFault::_vect = 0x0101;
56FaultStat InterruptFault::_stat;
57
58FaultName NDtbMissFault::_name = "dtb_miss_single";
59FaultVect NDtbMissFault::_vect = 0x0201;
60FaultStat NDtbMissFault::_stat;
61
62FaultName PDtbMissFault::_name = "dtb_miss_double";
63FaultVect PDtbMissFault::_vect = 0x0281;
64FaultStat PDtbMissFault::_stat;
65
66FaultName DtbPageFault::_name = "dfault";
67FaultVect DtbPageFault::_vect = 0x0381;
68FaultStat DtbPageFault::_stat;
69
70FaultName DtbAcvFault::_name = "dfault";
71FaultVect DtbAcvFault::_vect = 0x0381;
72FaultStat DtbAcvFault::_stat;
73
74FaultName ItbMissFault::_name = "itbmiss";
75FaultVect ItbMissFault::_vect = 0x0181;
76FaultStat ItbMissFault::_stat;
77
78FaultName ItbPageFault::_name = "itbmiss";
79FaultVect ItbPageFault::_vect = 0x0181;
80FaultStat ItbPageFault::_stat;
81
82FaultName ItbAcvFault::_name = "iaccvio";
83FaultVect ItbAcvFault::_vect = 0x0081;
84FaultStat ItbAcvFault::_stat;
85
86FaultName UnimplementedOpcodeFault::_name = "opdec";
87FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
88FaultStat UnimplementedOpcodeFault::_stat;
89
90FaultName FloatEnableFault::_name = "fen";
91FaultVect FloatEnableFault::_vect = 0x0581;
92FaultStat FloatEnableFault::_stat;
93
94FaultName PalFault::_name = "pal";
95FaultVect PalFault::_vect = 0x2001;
96FaultStat PalFault::_stat;
97
98FaultName IntegerOverflowFault::_name = "intover";
99FaultVect IntegerOverflowFault::_vect = 0x0501;
100FaultStat IntegerOverflowFault::_stat;
101
102#if FULL_SYSTEM
103
104void AlphaFault::invoke(ExecContext * xc)
105{
106    DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
107    xc->cpu->recordEvent(csprintf("Fault %s", name()));
108
109    assert(!xc->misspeculating());
110    xc->kernelStats->fault(this);
111
112    // exception restart address
113    if (setRestartAddress() || !xc->inPalMode())
114        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
115
116    if (skipFaultingInstruction()) {
117        // traps...  skip faulting instruction.
118        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
119                   xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
120    }
121
122    if (!xc->inPalMode())
123        AlphaISA::swap_palshadow(&(xc->regs), true);
124
125    xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
126    xc->regs.npc = xc->regs.pc + sizeof(MachInst);
127}
128
129void ArithmeticFault::invoke(ExecContext * xc)
130{
131    DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
132    xc->cpu->recordEvent(csprintf("Fault %s", name()));
133
134    assert(!xc->misspeculating());
135    xc->kernelStats->fault(this);
136
137    panic("Arithmetic traps are unimplemented!");
138}
139
140
141/*void ArithmeticFault::invoke(ExecContext * xc)
142{
143    panic("Arithmetic traps are unimplemented!");
144}*/
145
146#endif
147
148} // namespace AlphaISA
149
150/*Fault * ListOfFaults[] = {
151        (Fault *)&NoFault,
152        (Fault *)&ResetFault,
153        (Fault *)&MachineCheckFault,
154        (Fault *)&ArithmeticFault,
155        (Fault *)&InterruptFault,
156        (Fault *)&NDtbMissFault,
157        (Fault *)&PDtbMissFault,
158        (Fault *)&AlignmentFault,
159        (Fault *)&DtbPageFault,
160        (Fault *)&DtbAcvFault,
161        (Fault *)&ItbMissFault,
162        (Fault *)&ItbPageFault,
163        (Fault *)&ItbAcvFault,
164        (Fault *)&UnimplementedOpcodeFault,
165        (Fault *)&FloatEnableFault,
166        (Fault *)&PalFault,
167        (Fault *)&IntegerOverflowFault,
168        };
169
170int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);*/
171