faults.cc revision 2221
12SN/A/*
210905Sandreas.sandberg@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan
310905Sandreas.sandberg@arm.com * All rights reserved.
410905Sandreas.sandberg@arm.com *
510905Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without
610905Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are
710905Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright
810905Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer;
910905Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright
1010905Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the
1110905Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution;
1210905Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its
1310905Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from
141762SN/A * this software without specific prior written permission.
159983Sstever@gmail.com *
169983Sstever@gmail.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272SN/A */
282SN/A
292SN/A#include "arch/alpha/faults.hh"
302SN/A#include "cpu/exec_context.hh"
312SN/A#include "cpu/base.hh"
322SN/A#include "base/trace.hh"
332SN/A#include "kern/kernel_stats.hh"
342SN/A
352SN/Anamespace AlphaISA
362SN/A{
372SN/A
382SN/AFaultName MachineCheckFault::_name = "mchk";
392SN/AFaultVect MachineCheckFault::_vect = 0x0401;
402SN/AFaultStat MachineCheckFault::_stat;
412665Ssaidi@eecs.umich.edu
422760Sbinkertn@umich.eduFaultName AlignmentFault::_name = "unalign";
432760Sbinkertn@umich.eduFaultVect AlignmentFault::_vect = 0x0301;
442665Ssaidi@eecs.umich.eduFaultStat AlignmentFault::_stat;
4510905Sandreas.sandberg@arm.com
462SN/AFaultName ResetFault::_name = "reset";
472SN/AFaultVect ResetFault::_vect = 0x0001;
488229Snate@binkert.orgFaultStat ResetFault::_stat;
492SN/A
50363SN/AFaultName ArithmeticFault::_name = "arith";
512SN/AFaultVect ArithmeticFault::_vect = 0x0501;
528229Snate@binkert.orgFaultStat ArithmeticFault::_stat;
532SN/A
542SN/AFaultName InterruptFault::_name = "interrupt";
552SN/AFaultVect InterruptFault::_vect = 0x0101;
562SN/AFaultStat InterruptFault::_stat;
572SN/A
5810907Sandreas.sandberg@arm.comFaultName NDtbMissFault::_name = "dtb_miss_single";
59363SN/AFaultVect NDtbMissFault::_vect = 0x0201;
6056SN/AFaultStat NDtbMissFault::_stat;
611388SN/A
62217SN/AFaultName PDtbMissFault::_name = "dtb_miss_double";
63363SN/AFaultVect PDtbMissFault::_vect = 0x0281;
6410905Sandreas.sandberg@arm.comFaultStat PDtbMissFault::_stat;
6556SN/A
6656SN/AFaultName DtbPageFault::_name = "dfault";
6756SN/AFaultVect DtbPageFault::_vect = 0x0381;
681638SN/AFaultStat DtbPageFault::_stat;
6956SN/A
702SN/AFaultName DtbAcvFault::_name = "dfault";
712356SN/AFaultVect DtbAcvFault::_vect = 0x0381;
722356SN/AFaultStat DtbAcvFault::_stat;
732356SN/A
742SN/AFaultName ItbMissFault::_name = "itbmiss";
752SN/AFaultVect ItbMissFault::_vect = 0x0181;
764762Snate@binkert.orgFaultStat ItbMissFault::_stat;
774762Snate@binkert.org
784762Snate@binkert.orgFaultName ItbPageFault::_name = "itbmiss";
794762Snate@binkert.orgFaultVect ItbPageFault::_vect = 0x0181;
804762Snate@binkert.orgFaultStat ItbPageFault::_stat;
814762Snate@binkert.org
824762Snate@binkert.orgFaultName ItbAcvFault::_name = "iaccvio";
834762Snate@binkert.orgFaultVect ItbAcvFault::_vect = 0x0081;
844762Snate@binkert.orgFaultStat ItbAcvFault::_stat;
854762Snate@binkert.org
864762Snate@binkert.orgFaultName UnimplementedOpcodeFault::_name = "opdec";
874762Snate@binkert.orgFaultVect UnimplementedOpcodeFault::_vect = 0x0481;
884762Snate@binkert.orgFaultStat UnimplementedOpcodeFault::_stat;
8910905Sandreas.sandberg@arm.com
904762Snate@binkert.orgFaultName FloatEnableFault::_name = "fen";
914762Snate@binkert.orgFaultVect FloatEnableFault::_vect = 0x0581;
924762Snate@binkert.orgFaultStat FloatEnableFault::_stat;
934762Snate@binkert.org
944762Snate@binkert.orgFaultName PalFault::_name = "pal";
954762Snate@binkert.orgFaultVect PalFault::_vect = 0x2001;
964762Snate@binkert.orgFaultStat PalFault::_stat;
974762Snate@binkert.org
984762Snate@binkert.orgFaultName IntegerOverflowFault::_name = "intover";
994762Snate@binkert.orgFaultVect IntegerOverflowFault::_vect = 0x0501;
1004762Snate@binkert.orgFaultStat IntegerOverflowFault::_stat;
1014762Snate@binkert.org
1024762Snate@binkert.org#if FULL_SYSTEM
1034762Snate@binkert.org
1044762Snate@binkert.orgvoid AlphaFault::invoke(ExecContext * xc)
10510905Sandreas.sandberg@arm.com{
1067494Ssteve.reinhardt@amd.com    DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
1077494Ssteve.reinhardt@amd.com    xc->cpu->recordEvent(csprintf("Fault %s", name()));
1087494Ssteve.reinhardt@amd.com
1097494Ssteve.reinhardt@amd.com    assert(!xc->misspeculating());
1107494Ssteve.reinhardt@amd.com    xc->kernelStats->fault(this);
1117494Ssteve.reinhardt@amd.com
1127494Ssteve.reinhardt@amd.com    // exception restart address
11310905Sandreas.sandberg@arm.com    if (setRestartAddress() || !xc->inPalMode())
1144762Snate@binkert.org        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
1154762Snate@binkert.org
1164762Snate@binkert.org    if (skipFaultingInstruction()) {
1174762Snate@binkert.org        // traps...  skip faulting instruction.
1184762Snate@binkert.org        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
1194762Snate@binkert.org                   xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
1204762Snate@binkert.org    }
12110905Sandreas.sandberg@arm.com
1224762Snate@binkert.org    if (!xc->inPalMode())
1234762Snate@binkert.org        AlphaISA::swap_palshadow(&(xc->regs), true);
1244762Snate@binkert.org
1254762Snate@binkert.org    xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
1264762Snate@binkert.org    xc->regs.npc = xc->regs.pc + sizeof(MachInst);
1274762Snate@binkert.org}
1284762Snate@binkert.org
1294762Snate@binkert.orgvoid ArithmeticFault::invoke(ExecContext * xc)
1304762Snate@binkert.org{
13110386Sandreas.hansson@arm.com    DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
1324762Snate@binkert.org    xc->cpu->recordEvent(csprintf("Fault %s", name()));
1334762Snate@binkert.org
1344762Snate@binkert.org    assert(!xc->misspeculating());
1354762Snate@binkert.org    xc->kernelStats->fault(this);
1364762Snate@binkert.org
1374762Snate@binkert.org    panic("Arithmetic traps are unimplemented!");
13810386Sandreas.hansson@arm.com}
1394762Snate@binkert.org
1404762Snate@binkert.org
1414762Snate@binkert.org/*void ArithmeticFault::invoke(ExecContext * xc)
1424762Snate@binkert.org{
1434762Snate@binkert.org    panic("Arithmetic traps are unimplemented!");
1444762Snate@binkert.org}*/
14510386Sandreas.hansson@arm.com
1464762Snate@binkert.org#endif
1474762Snate@binkert.org
1484762Snate@binkert.org} // namespace AlphaISA
1494762Snate@binkert.org
1504762Snate@binkert.org/*Fault * ListOfFaults[] = {
15110905Sandreas.sandberg@arm.com        (Fault *)&NoFault,
1524762Snate@binkert.org        (Fault *)&ResetFault,
1534762Snate@binkert.org        (Fault *)&MachineCheckFault,
1544762Snate@binkert.org        (Fault *)&ArithmeticFault,
1554762Snate@binkert.org        (Fault *)&InterruptFault,
1564762Snate@binkert.org        (Fault *)&NDtbMissFault,
1574762Snate@binkert.org        (Fault *)&PDtbMissFault,
1584762Snate@binkert.org        (Fault *)&AlignmentFault,
1594762Snate@binkert.org        (Fault *)&DtbPageFault,
1604762Snate@binkert.org        (Fault *)&DtbAcvFault,
1614762Snate@binkert.org        (Fault *)&ItbMissFault,
1624762Snate@binkert.org        (Fault *)&ItbPageFault,
1634762Snate@binkert.org        (Fault *)&ItbAcvFault,
1644762Snate@binkert.org        (Fault *)&UnimplementedOpcodeFault,
1654762Snate@binkert.org        (Fault *)&FloatEnableFault,
1662287SN/A        (Fault *)&PalFault,
1672287SN/A        (Fault *)&IntegerOverflowFault,
1682287SN/A        };
16910905Sandreas.sandberg@arm.com
1702SN/Aint NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);*/
171217SN/A