faults.cc revision 11851
12221SN/A/* 22221SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32221SN/A * All rights reserved. 42221SN/A * 52221SN/A * Redistribution and use in source and binary forms, with or without 62221SN/A * modification, are permitted provided that the following conditions are 72221SN/A * met: redistributions of source code must retain the above copyright 82221SN/A * notice, this list of conditions and the following disclaimer; 92221SN/A * redistributions in binary form must reproduce the above copyright 102221SN/A * notice, this list of conditions and the following disclaimer in the 112221SN/A * documentation and/or other materials provided with the distribution; 122221SN/A * neither the name of the copyright holders nor the names of its 132221SN/A * contributors may be used to endorse or promote products derived from 142221SN/A * this software without specific prior written permission. 152221SN/A * 162221SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172221SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182221SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192221SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202221SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212221SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222221SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232221SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242221SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252221SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262221SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Kevin Lim 302221SN/A */ 312221SN/A 3211793Sbrandon.potter@amd.com#include "arch/sparc/faults.hh" 3311793Sbrandon.potter@amd.com 343415Sgblack@eecs.umich.edu#include <algorithm> 353415Sgblack@eecs.umich.edu 363415Sgblack@eecs.umich.edu#include "arch/sparc/isa_traits.hh" 378778Sgblack@eecs.umich.edu#include "arch/sparc/process.hh" 383578Sgblack@eecs.umich.edu#include "arch/sparc/types.hh" 393415Sgblack@eecs.umich.edu#include "base/bitfield.hh" 403415Sgblack@eecs.umich.edu#include "base/trace.hh" 413415Sgblack@eecs.umich.edu#include "cpu/base.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 433415Sgblack@eecs.umich.edu#include "mem/page_table.hh" 4411793Sbrandon.potter@amd.com#include "sim/full_system.hh" 452800Ssaidi@eecs.umich.edu#include "sim/process.hh" 462221SN/A 473415Sgblack@eecs.umich.eduusing namespace std; 483415Sgblack@eecs.umich.edu 492223SN/Anamespace SparcISA 502221SN/A{ 512221SN/A 523573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 533576Sgblack@eecs.umich.edu SparcFault<PowerOnReset>::vals = 549551Sandreas.hansson@arm.com{"power_on_reset", 0x001, 0, {H, H, H}, FaultStat()}; 552221SN/A 563573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 573576Sgblack@eecs.umich.edu SparcFault<WatchDogReset>::vals = 589551Sandreas.hansson@arm.com{"watch_dog_reset", 0x002, 120, {H, H, H}, FaultStat()}; 592221SN/A 603573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 613576Sgblack@eecs.umich.edu SparcFault<ExternallyInitiatedReset>::vals = 629551Sandreas.hansson@arm.com{"externally_initiated_reset", 0x003, 110, {H, H, H}, FaultStat()}; 632221SN/A 643573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 653576Sgblack@eecs.umich.edu SparcFault<SoftwareInitiatedReset>::vals = 669551Sandreas.hansson@arm.com{"software_initiated_reset", 0x004, 130, {SH, SH, H}, FaultStat()}; 672221SN/A 683573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 693576Sgblack@eecs.umich.edu SparcFault<REDStateException>::vals = 709551Sandreas.hansson@arm.com{"RED_state_exception", 0x005, 1, {H, H, H}, FaultStat()}; 712221SN/A 723573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 733576Sgblack@eecs.umich.edu SparcFault<StoreError>::vals = 749551Sandreas.hansson@arm.com{"store_error", 0x007, 201, {H, H, H}, FaultStat()}; 752221SN/A 763573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 773576Sgblack@eecs.umich.edu SparcFault<InstructionAccessException>::vals = 789551Sandreas.hansson@arm.com{"instruction_access_exception", 0x008, 300, {H, H, H}, FaultStat()}; 793576Sgblack@eecs.umich.edu 803576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005 813576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals 823576Sgblack@eecs.umich.edu SparcFault<InstructionAccessMMUMiss>::vals = 833576Sgblack@eecs.umich.edu {"inst_mmu", 0x009, 2, {H, H, H}};*/ 842221SN/A 853573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 863576Sgblack@eecs.umich.edu SparcFault<InstructionAccessError>::vals = 879551Sandreas.hansson@arm.com{"instruction_access_error", 0x00A, 400, {H, H, H}, FaultStat()}; 882221SN/A 893573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 903576Sgblack@eecs.umich.edu SparcFault<IllegalInstruction>::vals = 919551Sandreas.hansson@arm.com{"illegal_instruction", 0x010, 620, {H, H, H}, FaultStat()}; 922221SN/A 933573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 943576Sgblack@eecs.umich.edu SparcFault<PrivilegedOpcode>::vals = 959551Sandreas.hansson@arm.com{"privileged_opcode", 0x011, 700, {P, SH, SH}, FaultStat()}; 963576Sgblack@eecs.umich.edu 973576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005 983576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals 993576Sgblack@eecs.umich.edu SparcFault<UnimplementedLDD>::vals = 1003576Sgblack@eecs.umich.edu {"unimp_ldd", 0x012, 6, {H, H, H}};*/ 1013576Sgblack@eecs.umich.edu 1023576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005 1033576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals 1043576Sgblack@eecs.umich.edu SparcFault<UnimplementedSTD>::vals = 1053576Sgblack@eecs.umich.edu {"unimp_std", 0x013, 6, {H, H, H}};*/ 1062221SN/A 1073573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1083576Sgblack@eecs.umich.edu SparcFault<FpDisabled>::vals = 1099551Sandreas.hansson@arm.com{"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()}; 1102221SN/A 1113573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1123576Sgblack@eecs.umich.edu SparcFault<FpExceptionIEEE754>::vals = 1139551Sandreas.hansson@arm.com{"fp_exception_ieee_754", 0x021, 1110, {P, P, H}, FaultStat()}; 1142221SN/A 1153573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1163576Sgblack@eecs.umich.edu SparcFault<FpExceptionOther>::vals = 1179551Sandreas.hansson@arm.com{"fp_exception_other", 0x022, 1110, {P, P, H}, FaultStat()}; 1182221SN/A 1193573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1203576Sgblack@eecs.umich.edu SparcFault<TagOverflow>::vals = 1219551Sandreas.hansson@arm.com{"tag_overflow", 0x023, 1400, {P, P, H}, FaultStat()}; 1222221SN/A 1233573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1243576Sgblack@eecs.umich.edu SparcFault<CleanWindow>::vals = 1259551Sandreas.hansson@arm.com{"clean_window", 0x024, 1010, {P, P, H}, FaultStat()}; 1262221SN/A 1273573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1283576Sgblack@eecs.umich.edu SparcFault<DivisionByZero>::vals = 1299551Sandreas.hansson@arm.com{"division_by_zero", 0x028, 1500, {P, P, H}, FaultStat()}; 1302223SN/A 1313573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1323576Sgblack@eecs.umich.edu SparcFault<InternalProcessorError>::vals = 1339551Sandreas.hansson@arm.com{"internal_processor_error", 0x029, 4, {H, H, H}, FaultStat()}; 1342223SN/A 1353573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1363576Sgblack@eecs.umich.edu SparcFault<InstructionInvalidTSBEntry>::vals = 1379551Sandreas.hansson@arm.com{"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}, FaultStat()}; 1382223SN/A 1393573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1403576Sgblack@eecs.umich.edu SparcFault<DataInvalidTSBEntry>::vals = 1419551Sandreas.hansson@arm.com{"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}, FaultStat()}; 1422223SN/A 1433573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1443576Sgblack@eecs.umich.edu SparcFault<DataAccessException>::vals = 1459551Sandreas.hansson@arm.com{"data_access_exception", 0x030, 1201, {H, H, H}, FaultStat()}; 1463576Sgblack@eecs.umich.edu 1473576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005 1483576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals 1493576Sgblack@eecs.umich.edu SparcFault<DataAccessMMUMiss>::vals = 1503576Sgblack@eecs.umich.edu {"data_mmu", 0x031, 12, {H, H, H}};*/ 1512223SN/A 1523573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1533576Sgblack@eecs.umich.edu SparcFault<DataAccessError>::vals = 1549551Sandreas.hansson@arm.com{"data_access_error", 0x032, 1210, {H, H, H}, FaultStat()}; 1552223SN/A 1563573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1573576Sgblack@eecs.umich.edu SparcFault<DataAccessProtection>::vals = 1589551Sandreas.hansson@arm.com{"data_access_protection", 0x033, 1207, {H, H, H}, FaultStat()}; 1592223SN/A 1603573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1613576Sgblack@eecs.umich.edu SparcFault<MemAddressNotAligned>::vals = 1629551Sandreas.hansson@arm.com{"mem_address_not_aligned", 0x034, 1020, {H, H, H}, FaultStat()}; 1632223SN/A 1643573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1653576Sgblack@eecs.umich.edu SparcFault<LDDFMemAddressNotAligned>::vals = 1669551Sandreas.hansson@arm.com{"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}, FaultStat()}; 1672223SN/A 1683573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1693576Sgblack@eecs.umich.edu SparcFault<STDFMemAddressNotAligned>::vals = 1709551Sandreas.hansson@arm.com{"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}, FaultStat()}; 1712223SN/A 1723573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1733576Sgblack@eecs.umich.edu SparcFault<PrivilegedAction>::vals = 1749551Sandreas.hansson@arm.com{"privileged_action", 0x037, 1110, {H, H, SH}, FaultStat()}; 1752223SN/A 1763573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1773576Sgblack@eecs.umich.edu SparcFault<LDQFMemAddressNotAligned>::vals = 1789551Sandreas.hansson@arm.com{"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}, FaultStat()}; 1792223SN/A 1803573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1813576Sgblack@eecs.umich.edu SparcFault<STQFMemAddressNotAligned>::vals = 1829551Sandreas.hansson@arm.com{"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}, FaultStat()}; 1832223SN/A 1843573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1853576Sgblack@eecs.umich.edu SparcFault<InstructionRealTranslationMiss>::vals = 1869551Sandreas.hansson@arm.com{"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}, FaultStat()}; 1872223SN/A 1883573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1893576Sgblack@eecs.umich.edu SparcFault<DataRealTranslationMiss>::vals = 1909551Sandreas.hansson@arm.com{"data_real_translation_miss", 0x03F, 1203, {H, H, H}, FaultStat()}; 1912223SN/A 1923576Sgblack@eecs.umich.edu//XXX This trap is apparently dropped from ua2005 1933576Sgblack@eecs.umich.edu/*template<> SparcFaultBase::FaultVals 1943576Sgblack@eecs.umich.edu SparcFault<AsyncDataError>::vals = 1953576Sgblack@eecs.umich.edu {"async_data", 0x040, 2, {H, H, H}};*/ 1962527SN/A 1973573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 1983576Sgblack@eecs.umich.edu SparcFault<InterruptLevelN>::vals = 1999551Sandreas.hansson@arm.com{"interrupt_level_n", 0x040, 0, {P, P, SH}, FaultStat()}; 2002223SN/A 2013573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2023576Sgblack@eecs.umich.edu SparcFault<HstickMatch>::vals = 2039551Sandreas.hansson@arm.com{"hstick_match", 0x05E, 1601, {H, H, H}, FaultStat()}; 2042223SN/A 2053573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2063576Sgblack@eecs.umich.edu SparcFault<TrapLevelZero>::vals = 2079551Sandreas.hansson@arm.com{"trap_level_zero", 0x05F, 202, {H, H, SH}, FaultStat()}; 2082223SN/A 2093573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2104103Ssaidi@eecs.umich.edu SparcFault<InterruptVector>::vals = 2119551Sandreas.hansson@arm.com{"interrupt_vector", 0x060, 2630, {H, H, H}, FaultStat()}; 2124103Ssaidi@eecs.umich.edu 2134103Ssaidi@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2143576Sgblack@eecs.umich.edu SparcFault<PAWatchpoint>::vals = 2159551Sandreas.hansson@arm.com{"PA_watchpoint", 0x061, 1209, {H, H, H}, FaultStat()}; 2162223SN/A 2173573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2183576Sgblack@eecs.umich.edu SparcFault<VAWatchpoint>::vals = 2199551Sandreas.hansson@arm.com{"VA_watchpoint", 0x062, 1120, {P, P, SH}, FaultStat()}; 2202223SN/A 2213573Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2223576Sgblack@eecs.umich.edu SparcFault<FastInstructionAccessMMUMiss>::vals = 2239551Sandreas.hansson@arm.com{"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}, FaultStat()}; 2243576Sgblack@eecs.umich.edu 2253576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2263576Sgblack@eecs.umich.edu SparcFault<FastDataAccessMMUMiss>::vals = 2279551Sandreas.hansson@arm.com{"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}, FaultStat()}; 2283576Sgblack@eecs.umich.edu 2293576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2303576Sgblack@eecs.umich.edu SparcFault<FastDataAccessProtection>::vals = 2319551Sandreas.hansson@arm.com{"fast_data_access_protection", 0x06C, 1207, {H, H, H}, FaultStat()}; 2323576Sgblack@eecs.umich.edu 2333576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2343576Sgblack@eecs.umich.edu SparcFault<InstructionBreakpoint>::vals = 2359551Sandreas.hansson@arm.com{"instruction_break", 0x076, 610, {H, H, H}, FaultStat()}; 2363576Sgblack@eecs.umich.edu 2373576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2383576Sgblack@eecs.umich.edu SparcFault<CpuMondo>::vals = 2399551Sandreas.hansson@arm.com{"cpu_mondo", 0x07C, 1608, {P, P, SH}, FaultStat()}; 2403576Sgblack@eecs.umich.edu 2413576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2423576Sgblack@eecs.umich.edu SparcFault<DevMondo>::vals = 2439551Sandreas.hansson@arm.com{"dev_mondo", 0x07D, 1611, {P, P, SH}, FaultStat()}; 2443576Sgblack@eecs.umich.edu 2453576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2463893Shsul@eecs.umich.edu SparcFault<ResumableError>::vals = 2479551Sandreas.hansson@arm.com{"resume_error", 0x07E, 3330, {P, P, SH}, FaultStat()}; 2483576Sgblack@eecs.umich.edu 2493576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2503576Sgblack@eecs.umich.edu SparcFault<SpillNNormal>::vals = 2519551Sandreas.hansson@arm.com{"spill_n_normal", 0x080, 900, {P, P, H}, FaultStat()}; 2523576Sgblack@eecs.umich.edu 2533576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2543576Sgblack@eecs.umich.edu SparcFault<SpillNOther>::vals = 2559551Sandreas.hansson@arm.com{"spill_n_other", 0x0A0, 900, {P, P, H}, FaultStat()}; 2563576Sgblack@eecs.umich.edu 2573576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2583576Sgblack@eecs.umich.edu SparcFault<FillNNormal>::vals = 2599551Sandreas.hansson@arm.com{"fill_n_normal", 0x0C0, 900, {P, P, H}, FaultStat()}; 2603576Sgblack@eecs.umich.edu 2613576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2623576Sgblack@eecs.umich.edu SparcFault<FillNOther>::vals = 2639551Sandreas.hansson@arm.com{"fill_n_other", 0x0E0, 900, {P, P, H}, FaultStat()}; 2643576Sgblack@eecs.umich.edu 2653576Sgblack@eecs.umich.edutemplate<> SparcFaultBase::FaultVals 2663576Sgblack@eecs.umich.edu SparcFault<TrapInstruction>::vals = 2679551Sandreas.hansson@arm.com{"trap_instruction", 0x100, 1602, {P, P, H}, FaultStat()}; 2682223SN/A 2693415Sgblack@eecs.umich.edu/** 2703578Sgblack@eecs.umich.edu * This causes the thread context to enter RED state. This causes the side 2713578Sgblack@eecs.umich.edu * effects which go with entering RED state because of a trap. 2723415Sgblack@eecs.umich.edu */ 2733415Sgblack@eecs.umich.edu 2747741Sgblack@eecs.umich.eduvoid 2757741Sgblack@eecs.umich.eduenterREDState(ThreadContext *tc) 2763415Sgblack@eecs.umich.edu{ 2773578Sgblack@eecs.umich.edu //@todo Disable the mmu? 2783578Sgblack@eecs.umich.edu //@todo Disable watchpoints? 2798829Sgblack@eecs.umich.edu HPSTATE hpstate= tc->readMiscRegNoEffect(MISCREG_HPSTATE); 2808829Sgblack@eecs.umich.edu hpstate.red = 1; 2818829Sgblack@eecs.umich.edu hpstate.hpriv = 1; 2828829Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_HPSTATE, hpstate); 2837741Sgblack@eecs.umich.edu // PSTATE.priv is set to 1 here. The manual says it should be 0, but 2847741Sgblack@eecs.umich.edu // Legion sets it to 1. 2858829Sgblack@eecs.umich.edu PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 2868829Sgblack@eecs.umich.edu pstate.priv = 1; 2878829Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PSTATE, pstate); 2883578Sgblack@eecs.umich.edu} 2893578Sgblack@eecs.umich.edu 2903578Sgblack@eecs.umich.edu/** 2913578Sgblack@eecs.umich.edu * This sets everything up for a RED state trap except for actually jumping to 2923578Sgblack@eecs.umich.edu * the handler. 2933578Sgblack@eecs.umich.edu */ 2943578Sgblack@eecs.umich.edu 2957741Sgblack@eecs.umich.eduvoid 2967741Sgblack@eecs.umich.edudoREDFault(ThreadContext *tc, TrapType tt) 2973578Sgblack@eecs.umich.edu{ 2984172Ssaidi@eecs.umich.edu MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL); 2994172Ssaidi@eecs.umich.edu MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE); 3008829Sgblack@eecs.umich.edu PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 3018829Sgblack@eecs.umich.edu HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 3023761Sgblack@eecs.umich.edu MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2); 3034172Ssaidi@eecs.umich.edu MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI); 3044172Ssaidi@eecs.umich.edu MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP); 3054172Ssaidi@eecs.umich.edu MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3); 3064172Ssaidi@eecs.umich.edu MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL); 3077720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 3083578Sgblack@eecs.umich.edu 3093578Sgblack@eecs.umich.edu TL++; 3103578Sgblack@eecs.umich.edu 3118829Sgblack@eecs.umich.edu Addr pcMask = pstate.am ? mask(32) : mask(64); 3123928Ssaidi@eecs.umich.edu 3137741Sgblack@eecs.umich.edu // set TSTATE.gl to gl 3143578Sgblack@eecs.umich.edu replaceBits(TSTATE, 42, 40, GL); 3157741Sgblack@eecs.umich.edu // set TSTATE.ccr to ccr 3163578Sgblack@eecs.umich.edu replaceBits(TSTATE, 39, 32, CCR); 3177741Sgblack@eecs.umich.edu // set TSTATE.asi to asi 3183578Sgblack@eecs.umich.edu replaceBits(TSTATE, 31, 24, ASI); 3197741Sgblack@eecs.umich.edu // set TSTATE.pstate to pstate 3208829Sgblack@eecs.umich.edu replaceBits(TSTATE, 20, 8, pstate); 3217741Sgblack@eecs.umich.edu // set TSTATE.cwp to cwp 3223578Sgblack@eecs.umich.edu replaceBits(TSTATE, 4, 0, CWP); 3233578Sgblack@eecs.umich.edu 3247741Sgblack@eecs.umich.edu // Write back TSTATE 3254172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE); 3263578Sgblack@eecs.umich.edu 3277741Sgblack@eecs.umich.edu // set TPC to PC 3287720Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask); 3297741Sgblack@eecs.umich.edu // set TNPC to NPC 3307720Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask); 3313578Sgblack@eecs.umich.edu 3327741Sgblack@eecs.umich.edu // set HTSTATE.hpstate to hpstate 3338829Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate); 3343578Sgblack@eecs.umich.edu 3357741Sgblack@eecs.umich.edu // TT = trap type; 3364172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TT, tt); 3373578Sgblack@eecs.umich.edu 3387741Sgblack@eecs.umich.edu // Update GL 3394172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL)); 3403578Sgblack@eecs.umich.edu 3418829Sgblack@eecs.umich.edu bool priv = pstate.priv; // just save the priv bit 3428829Sgblack@eecs.umich.edu pstate = 0; 3438829Sgblack@eecs.umich.edu pstate.priv = priv; 3448829Sgblack@eecs.umich.edu pstate.pef = 1; 3458829Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate); 3463578Sgblack@eecs.umich.edu 3478829Sgblack@eecs.umich.edu hpstate.red = 1; 3488829Sgblack@eecs.umich.edu hpstate.hpriv = 1; 3498829Sgblack@eecs.umich.edu hpstate.ibe = 0; 3508829Sgblack@eecs.umich.edu hpstate.tlz = 0; 3518829Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate); 3523578Sgblack@eecs.umich.edu 3533578Sgblack@eecs.umich.edu bool changedCWP = true; 3543893Shsul@eecs.umich.edu if (tt == 0x24) 3553415Sgblack@eecs.umich.edu CWP++; 3563893Shsul@eecs.umich.edu else if (0x80 <= tt && tt <= 0xbf) 3573415Sgblack@eecs.umich.edu CWP += (CANSAVE + 2); 3583893Shsul@eecs.umich.edu else if (0xc0 <= tt && tt <= 0xff) 3593415Sgblack@eecs.umich.edu CWP--; 3603415Sgblack@eecs.umich.edu else 3613415Sgblack@eecs.umich.edu changedCWP = false; 3623420Sgblack@eecs.umich.edu 3637741Sgblack@eecs.umich.edu if (changedCWP) { 3643415Sgblack@eecs.umich.edu CWP = (CWP + NWindows) % NWindows; 3654172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 3663415Sgblack@eecs.umich.edu } 3673415Sgblack@eecs.umich.edu} 3683415Sgblack@eecs.umich.edu 3697741Sgblack@eecs.umich.edu/** 3707741Sgblack@eecs.umich.edu * This sets everything up for a normal trap except for actually jumping to 3717741Sgblack@eecs.umich.edu * the handler. 3727741Sgblack@eecs.umich.edu */ 3737741Sgblack@eecs.umich.edu 3747741Sgblack@eecs.umich.eduvoid 3757741Sgblack@eecs.umich.edudoNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) 3767741Sgblack@eecs.umich.edu{ 3777741Sgblack@eecs.umich.edu MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL); 3787741Sgblack@eecs.umich.edu MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE); 3798829Sgblack@eecs.umich.edu PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 3808829Sgblack@eecs.umich.edu HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 3817741Sgblack@eecs.umich.edu MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2); 3827741Sgblack@eecs.umich.edu MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI); 3837741Sgblack@eecs.umich.edu MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP); 3847741Sgblack@eecs.umich.edu MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3); 3857741Sgblack@eecs.umich.edu MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL); 3867741Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 3877741Sgblack@eecs.umich.edu 3887741Sgblack@eecs.umich.edu // Increment the trap level 3897741Sgblack@eecs.umich.edu TL++; 3907741Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TL, TL); 3917741Sgblack@eecs.umich.edu 3928829Sgblack@eecs.umich.edu Addr pcMask = pstate.am ? mask(32) : mask(64); 3937741Sgblack@eecs.umich.edu 3947741Sgblack@eecs.umich.edu // Save off state 3957741Sgblack@eecs.umich.edu 3967741Sgblack@eecs.umich.edu // set TSTATE.gl to gl 3977741Sgblack@eecs.umich.edu replaceBits(TSTATE, 42, 40, GL); 3987741Sgblack@eecs.umich.edu // set TSTATE.ccr to ccr 3997741Sgblack@eecs.umich.edu replaceBits(TSTATE, 39, 32, CCR); 4007741Sgblack@eecs.umich.edu // set TSTATE.asi to asi 4017741Sgblack@eecs.umich.edu replaceBits(TSTATE, 31, 24, ASI); 4027741Sgblack@eecs.umich.edu // set TSTATE.pstate to pstate 4038829Sgblack@eecs.umich.edu replaceBits(TSTATE, 20, 8, pstate); 4047741Sgblack@eecs.umich.edu // set TSTATE.cwp to cwp 4057741Sgblack@eecs.umich.edu replaceBits(TSTATE, 4, 0, CWP); 4067741Sgblack@eecs.umich.edu 4077741Sgblack@eecs.umich.edu // Write back TSTATE 4087741Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE); 4097741Sgblack@eecs.umich.edu 4107741Sgblack@eecs.umich.edu // set TPC to PC 4117741Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask); 4127741Sgblack@eecs.umich.edu // set TNPC to NPC 4137741Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask); 4147741Sgblack@eecs.umich.edu 4157741Sgblack@eecs.umich.edu // set HTSTATE.hpstate to hpstate 4168829Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate); 4177741Sgblack@eecs.umich.edu 4187741Sgblack@eecs.umich.edu // TT = trap type; 4197741Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TT, tt); 4207741Sgblack@eecs.umich.edu 4217741Sgblack@eecs.umich.edu // Update the global register level 4227741Sgblack@eecs.umich.edu if (!gotoHpriv) 4237741Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxPGL)); 4247741Sgblack@eecs.umich.edu else 4257741Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL)); 4267741Sgblack@eecs.umich.edu 4278829Sgblack@eecs.umich.edu // pstate.mm is unchanged 4288829Sgblack@eecs.umich.edu pstate.pef = 1; // PSTATE.pef = whether or not an fpu is present 4298829Sgblack@eecs.umich.edu pstate.am = 0; 4308829Sgblack@eecs.umich.edu pstate.ie = 0; 4318829Sgblack@eecs.umich.edu // pstate.tle is unchanged 4328829Sgblack@eecs.umich.edu // pstate.tct = 0 4337741Sgblack@eecs.umich.edu 4347741Sgblack@eecs.umich.edu if (gotoHpriv) { 4358829Sgblack@eecs.umich.edu pstate.cle = 0; 4367741Sgblack@eecs.umich.edu // The manual says PSTATE.priv should be 0, but Legion leaves it alone 4378829Sgblack@eecs.umich.edu hpstate.red = 0; 4388829Sgblack@eecs.umich.edu hpstate.hpriv = 1; 4398829Sgblack@eecs.umich.edu hpstate.ibe = 0; 4408829Sgblack@eecs.umich.edu // hpstate.tlz is unchanged 4418829Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate); 4427741Sgblack@eecs.umich.edu } else { // we are going to priv 4438829Sgblack@eecs.umich.edu pstate.priv = 1; 4448829Sgblack@eecs.umich.edu pstate.cle = pstate.tle; 4457741Sgblack@eecs.umich.edu } 4468829Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate); 4477741Sgblack@eecs.umich.edu 4487741Sgblack@eecs.umich.edu 4497741Sgblack@eecs.umich.edu bool changedCWP = true; 4507741Sgblack@eecs.umich.edu if (tt == 0x24) 4517741Sgblack@eecs.umich.edu CWP++; 4527741Sgblack@eecs.umich.edu else if (0x80 <= tt && tt <= 0xbf) 4537741Sgblack@eecs.umich.edu CWP += (CANSAVE + 2); 4547741Sgblack@eecs.umich.edu else if (0xc0 <= tt && tt <= 0xff) 4557741Sgblack@eecs.umich.edu CWP--; 4567741Sgblack@eecs.umich.edu else 4577741Sgblack@eecs.umich.edu changedCWP = false; 4587741Sgblack@eecs.umich.edu 4597741Sgblack@eecs.umich.edu if (changedCWP) { 4607741Sgblack@eecs.umich.edu CWP = (CWP + NWindows) % NWindows; 4617741Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4627741Sgblack@eecs.umich.edu } 4637741Sgblack@eecs.umich.edu} 4647741Sgblack@eecs.umich.edu 4657741Sgblack@eecs.umich.eduvoid 4667741Sgblack@eecs.umich.edugetREDVector(MiscReg TT, Addr &PC, Addr &NPC) 4673578Sgblack@eecs.umich.edu{ 4683585Sgblack@eecs.umich.edu //XXX The following constant might belong in a header file. 4693603Ssaidi@eecs.umich.edu const Addr RSTVAddr = 0xFFF0000000ULL; 4703595Sgblack@eecs.umich.edu PC = RSTVAddr | ((TT << 5) & 0xFF); 4713578Sgblack@eecs.umich.edu NPC = PC + sizeof(MachInst); 4723578Sgblack@eecs.umich.edu} 4733578Sgblack@eecs.umich.edu 4747741Sgblack@eecs.umich.eduvoid 4757741Sgblack@eecs.umich.edugetHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT) 4763578Sgblack@eecs.umich.edu{ 4774172Ssaidi@eecs.umich.edu Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA); 4783578Sgblack@eecs.umich.edu PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14)); 4793578Sgblack@eecs.umich.edu NPC = PC + sizeof(MachInst); 4803578Sgblack@eecs.umich.edu} 4813578Sgblack@eecs.umich.edu 4827741Sgblack@eecs.umich.eduvoid 4837741Sgblack@eecs.umich.edugetPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL) 4843578Sgblack@eecs.umich.edu{ 4854172Ssaidi@eecs.umich.edu Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA); 4863578Sgblack@eecs.umich.edu PC = (TBA & ~mask(15)) | 4873578Sgblack@eecs.umich.edu (TL > 1 ? (1 << 14) : 0) | 4883578Sgblack@eecs.umich.edu ((TT << 5) & mask(14)); 4893578Sgblack@eecs.umich.edu NPC = PC + sizeof(MachInst); 4903578Sgblack@eecs.umich.edu} 4913578Sgblack@eecs.umich.edu 4927741Sgblack@eecs.umich.eduvoid 49310417Sandreas.hansson@arm.comSparcFaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst) 4942221SN/A{ 4952680Sktlim@umich.edu FaultBase::invoke(tc); 4968750Sgblack@eecs.umich.edu if (!FullSystem) 4978750Sgblack@eecs.umich.edu return; 4988750Sgblack@eecs.umich.edu 4992223SN/A countStat()++; 5002221SN/A 5017741Sgblack@eecs.umich.edu // We can refer to this to see what the trap level -was-, but something 5027741Sgblack@eecs.umich.edu // in the middle could change it in the regfile out from under us. 5034172Ssaidi@eecs.umich.edu MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL); 5044172Ssaidi@eecs.umich.edu MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT); 5058829Sgblack@eecs.umich.edu PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 5068829Sgblack@eecs.umich.edu HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 5073578Sgblack@eecs.umich.edu 5083578Sgblack@eecs.umich.edu Addr PC, NPC; 5093578Sgblack@eecs.umich.edu 5103578Sgblack@eecs.umich.edu PrivilegeLevel current; 5118829Sgblack@eecs.umich.edu if (hpstate.hpriv) 5123746Sgblack@eecs.umich.edu current = Hyperprivileged; 5138829Sgblack@eecs.umich.edu else if (pstate.priv) 5143578Sgblack@eecs.umich.edu current = Privileged; 5153578Sgblack@eecs.umich.edu else 5163746Sgblack@eecs.umich.edu current = User; 5173578Sgblack@eecs.umich.edu 5183578Sgblack@eecs.umich.edu PrivilegeLevel level = getNextLevel(current); 5193578Sgblack@eecs.umich.edu 5208829Sgblack@eecs.umich.edu if (hpstate.red || (tl == MaxTL - 1)) { 5213595Sgblack@eecs.umich.edu getREDVector(5, PC, NPC); 5223893Shsul@eecs.umich.edu doREDFault(tc, tt); 5237741Sgblack@eecs.umich.edu // This changes the hpstate and pstate, so we need to make sure we 5247741Sgblack@eecs.umich.edu // save the old version on the trap stack in doREDFault. 5253578Sgblack@eecs.umich.edu enterREDState(tc); 5263893Shsul@eecs.umich.edu } else if (tl == MaxTL) { 5273825Ssaidi@eecs.umich.edu panic("Should go to error state here.. crap\n"); 5287741Sgblack@eecs.umich.edu // Do error_state somehow? 5297741Sgblack@eecs.umich.edu // Probably inject a WDR fault using the interrupt mechanism. 5307741Sgblack@eecs.umich.edu // What should the PC and NPC be set to? 5313893Shsul@eecs.umich.edu } else if (tl > MaxPTL && level == Privileged) { 5327741Sgblack@eecs.umich.edu // guest_watchdog fault 5333578Sgblack@eecs.umich.edu doNormalFault(tc, trapType(), true); 5343585Sgblack@eecs.umich.edu getHyperVector(tc, PC, NPC, 2); 5353893Shsul@eecs.umich.edu } else if (level == Hyperprivileged || 5365570Snate@binkert.org (level == Privileged && trapType() >= 384)) { 5373578Sgblack@eecs.umich.edu doNormalFault(tc, trapType(), true); 5383585Sgblack@eecs.umich.edu getHyperVector(tc, PC, NPC, trapType()); 5393826Ssaidi@eecs.umich.edu } else { 5403578Sgblack@eecs.umich.edu doNormalFault(tc, trapType(), false); 5417741Sgblack@eecs.umich.edu getPrivVector(tc, PC, NPC, trapType(), tl + 1); 5423578Sgblack@eecs.umich.edu } 5433578Sgblack@eecs.umich.edu 5447720Sgblack@eecs.umich.edu PCState pc; 5457720Sgblack@eecs.umich.edu pc.pc(PC); 5467720Sgblack@eecs.umich.edu pc.npc(NPC); 5477720Sgblack@eecs.umich.edu pc.nnpc(NPC + sizeof(MachInst)); 5487720Sgblack@eecs.umich.edu pc.upc(0); 5497720Sgblack@eecs.umich.edu pc.nupc(1); 5507720Sgblack@eecs.umich.edu tc->pcState(pc); 5513420Sgblack@eecs.umich.edu} 5522221SN/A 5537741Sgblack@eecs.umich.eduvoid 55410417Sandreas.hansson@arm.comPowerOnReset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 5553523Sgblack@eecs.umich.edu{ 5567741Sgblack@eecs.umich.edu // For SPARC, when a system is first started, there is a power 5577741Sgblack@eecs.umich.edu // on reset Trap which sets the processor into the following state. 5587741Sgblack@eecs.umich.edu // Bits that aren't set aren't defined on startup. 5593595Sgblack@eecs.umich.edu 5604172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TL, MaxTL); 5614172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TT, trapType()); 5624172Ssaidi@eecs.umich.edu tc->setMiscReg(MISCREG_GL, MaxGL); 5633595Sgblack@eecs.umich.edu 5648829Sgblack@eecs.umich.edu PSTATE pstate = 0; 5658829Sgblack@eecs.umich.edu pstate.pef = 1; 5668829Sgblack@eecs.umich.edu pstate.priv = 1; 5678829Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate); 5683595Sgblack@eecs.umich.edu 5697741Sgblack@eecs.umich.edu // Turn on red and hpriv, set everything else to 0 5708829Sgblack@eecs.umich.edu HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 5718829Sgblack@eecs.umich.edu hpstate.red = 1; 5728829Sgblack@eecs.umich.edu hpstate.hpriv = 1; 5738829Sgblack@eecs.umich.edu hpstate.ibe = 0; 5748829Sgblack@eecs.umich.edu hpstate.tlz = 0; 5758829Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate); 5763595Sgblack@eecs.umich.edu 5777741Sgblack@eecs.umich.edu // The tick register is unreadable by nonprivileged software 5784172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63); 5793595Sgblack@eecs.umich.edu 5807741Sgblack@eecs.umich.edu // Enter RED state. We do this last so that the actual state preserved in 5817741Sgblack@eecs.umich.edu // the trap stack is the state from before this fault. 5823746Sgblack@eecs.umich.edu enterREDState(tc); 5833746Sgblack@eecs.umich.edu 5843595Sgblack@eecs.umich.edu Addr PC, NPC; 5853595Sgblack@eecs.umich.edu getREDVector(trapType(), PC, NPC); 5867720Sgblack@eecs.umich.edu 5877720Sgblack@eecs.umich.edu PCState pc; 5887720Sgblack@eecs.umich.edu pc.pc(PC); 5897720Sgblack@eecs.umich.edu pc.npc(NPC); 5907720Sgblack@eecs.umich.edu pc.nnpc(NPC + sizeof(MachInst)); 5917720Sgblack@eecs.umich.edu pc.upc(0); 5927720Sgblack@eecs.umich.edu pc.nupc(1); 5937720Sgblack@eecs.umich.edu tc->pcState(pc); 5943595Sgblack@eecs.umich.edu 5957741Sgblack@eecs.umich.edu // These registers are specified as "undefined" after a POR, and they 5967741Sgblack@eecs.umich.edu // should have reasonable values after the miscregfile is reset 5973523Sgblack@eecs.umich.edu /* 5983595Sgblack@eecs.umich.edu // Clear all the soft interrupt bits 5993595Sgblack@eecs.umich.edu softint = 0; 6003595Sgblack@eecs.umich.edu // disable timer compare interrupts, reset tick_cmpr 6014172Ssaidi@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ 6023595Sgblack@eecs.umich.edu tick_cmprFields.int_dis = 1; 6033523Sgblack@eecs.umich.edu tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 6047741Sgblack@eecs.umich.edu stickFields.npt = 1; // The TICK register is unreadable by by !priv 6053523Sgblack@eecs.umich.edu stick_cmprFields.int_dis = 1; // disable timer compare interrupts 6063523Sgblack@eecs.umich.edu stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 6073523Sgblack@eecs.umich.edu 6083523Sgblack@eecs.umich.edu tt[tl] = _trapType; 6093523Sgblack@eecs.umich.edu 6103523Sgblack@eecs.umich.edu hintp = 0; // no interrupts pending 6113523Sgblack@eecs.umich.edu hstick_cmprFields.int_dis = 1; // disable timer compare interrupts 6123523Sgblack@eecs.umich.edu hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 6133523Sgblack@eecs.umich.edu */ 6142221SN/A} 6152221SN/A 6167741Sgblack@eecs.umich.eduvoid 61710417Sandreas.hansson@arm.comFastInstructionAccessMMUMiss::invoke(ThreadContext *tc, 61810417Sandreas.hansson@arm.com const StaticInstPtr &inst) 6194997Sgblack@eecs.umich.edu{ 6208767Sgblack@eecs.umich.edu if (FullSystem) { 6218767Sgblack@eecs.umich.edu SparcFaultBase::invoke(tc, inst); 6228806Sgblack@eecs.umich.edu return; 6238806Sgblack@eecs.umich.edu } 6248806Sgblack@eecs.umich.edu 6258806Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 6268806Sgblack@eecs.umich.edu TlbEntry entry; 6278806Sgblack@eecs.umich.edu bool success = p->pTable->lookup(vaddr, entry); 6288806Sgblack@eecs.umich.edu if (!success) { 6298806Sgblack@eecs.umich.edu panic("Tried to execute unmapped address %#x.\n", vaddr); 6304997Sgblack@eecs.umich.edu } else { 63111850Sbrandon.potter@amd.com Addr alignedvaddr = p->pTable->pageAlign(vaddr); 63211850Sbrandon.potter@amd.com 63311850Sbrandon.potter@amd.com // Grab fields used during instruction translation to figure out 63411850Sbrandon.potter@amd.com // which context to use. 63511850Sbrandon.potter@amd.com uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 63611850Sbrandon.potter@amd.com 63711850Sbrandon.potter@amd.com // Inside a VM, a real address is the address that guest OS would 63811850Sbrandon.potter@amd.com // interpret to be a physical address. To map to the physical address, 63911850Sbrandon.potter@amd.com // it still needs to undergo a translation. The instruction 64011850Sbrandon.potter@amd.com // translation code in the SPARC ITLB code assumes that the context is 64111850Sbrandon.potter@amd.com // zero (kernel-level) if real addressing is being used. 64211850Sbrandon.potter@amd.com bool is_real_address = !bits(tlbdata, 4); 64311850Sbrandon.potter@amd.com 64411850Sbrandon.potter@amd.com // The SPARC ITLB code assumes that traps are executed in context 64511850Sbrandon.potter@amd.com // zero so we carry that assumption through here. 64611850Sbrandon.potter@amd.com bool trapped = bits(tlbdata, 18, 16) > 0; 64711850Sbrandon.potter@amd.com 64811850Sbrandon.potter@amd.com // The primary context acts as a PASID. It allows the MMU to 64911850Sbrandon.potter@amd.com // distinguish between virtual addresses that would alias to the 65011850Sbrandon.potter@amd.com // same physical address (if two or more processes shared the same 65111850Sbrandon.potter@amd.com // virtual address mapping). 65211850Sbrandon.potter@amd.com int primary_context = bits(tlbdata, 47, 32); 65311850Sbrandon.potter@amd.com 65411850Sbrandon.potter@amd.com // The partition id distinguishes between virtualized environments. 65511850Sbrandon.potter@amd.com int const partition_id = 0; 65611850Sbrandon.potter@amd.com 65711850Sbrandon.potter@amd.com // Given the assumptions in the translateInst code in the SPARC ITLB, 65811850Sbrandon.potter@amd.com // the logic works out to the following for the context. 65911850Sbrandon.potter@amd.com int context_id = (is_real_address || trapped) ? 0 : primary_context; 66011850Sbrandon.potter@amd.com 66111850Sbrandon.potter@amd.com // Insert the TLB entry. 66211850Sbrandon.potter@amd.com // The entry specifying whether the address is "real" is set to 66311850Sbrandon.potter@amd.com // false for syscall emulation mode regardless of whether the 66411850Sbrandon.potter@amd.com // address is real in preceding code. Not sure sure that this is 66511850Sbrandon.potter@amd.com // correct, but also not sure if it matters at all. 66611850Sbrandon.potter@amd.com tc->getITBPtr()->insert(alignedvaddr, partition_id, context_id, 66711850Sbrandon.potter@amd.com false, entry.pte); 6684997Sgblack@eecs.umich.edu } 6694997Sgblack@eecs.umich.edu} 6704997Sgblack@eecs.umich.edu 6717741Sgblack@eecs.umich.eduvoid 67210417Sandreas.hansson@arm.comFastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst) 6734997Sgblack@eecs.umich.edu{ 6748767Sgblack@eecs.umich.edu if (FullSystem) { 6758767Sgblack@eecs.umich.edu SparcFaultBase::invoke(tc, inst); 6768806Sgblack@eecs.umich.edu return; 6778806Sgblack@eecs.umich.edu } 6788806Sgblack@eecs.umich.edu 6798806Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 6808806Sgblack@eecs.umich.edu TlbEntry entry; 6818806Sgblack@eecs.umich.edu bool success = p->pTable->lookup(vaddr, entry); 6828806Sgblack@eecs.umich.edu if (!success) { 6838806Sgblack@eecs.umich.edu if (p->fixupStackFault(vaddr)) 6848806Sgblack@eecs.umich.edu success = p->pTable->lookup(vaddr, entry); 6858806Sgblack@eecs.umich.edu } 6868806Sgblack@eecs.umich.edu if (!success) { 6878806Sgblack@eecs.umich.edu panic("Tried to access unmapped address %#x.\n", vaddr); 6888767Sgblack@eecs.umich.edu } else { 68911850Sbrandon.potter@amd.com Addr alignedvaddr = p->pTable->pageAlign(vaddr); 69011850Sbrandon.potter@amd.com 69111850Sbrandon.potter@amd.com // Grab fields used during data translation to figure out 69211850Sbrandon.potter@amd.com // which context to use. 69311850Sbrandon.potter@amd.com uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 69411850Sbrandon.potter@amd.com 69511850Sbrandon.potter@amd.com // The primary context acts as a PASID. It allows the MMU to 69611850Sbrandon.potter@amd.com // distinguish between virtual addresses that would alias to the 69711850Sbrandon.potter@amd.com // same physical address (if two or more processes shared the same 69811850Sbrandon.potter@amd.com // virtual address mapping). There's a secondary context used in the 69911850Sbrandon.potter@amd.com // DTLB translation code, but it should __probably__ be zero for 70011850Sbrandon.potter@amd.com // syscall emulation code. (The secondary context is used by Solaris 70111850Sbrandon.potter@amd.com // to allow kernel privilege code to access user space code: 70211850Sbrandon.potter@amd.com // [ISBN 0-13-022496-0]:PG199.) 70311850Sbrandon.potter@amd.com int primary_context = bits(tlbdata, 47, 32); 70411850Sbrandon.potter@amd.com 70511850Sbrandon.potter@amd.com // "Hyper-Privileged Mode" is in use. There are three main modes of 70611850Sbrandon.potter@amd.com // operation for Sparc: Hyper-Privileged Mode, Privileged Mode, and 70711850Sbrandon.potter@amd.com // User Mode. 70811850Sbrandon.potter@amd.com int hpriv = bits(tlbdata, 0); 70911850Sbrandon.potter@amd.com 71011850Sbrandon.potter@amd.com // Reset, Error and Debug state is in use. Something horrible has 71111850Sbrandon.potter@amd.com // happened or the system is operating in Reset Mode. 71211850Sbrandon.potter@amd.com int red = bits(tlbdata, 1); 71311850Sbrandon.potter@amd.com 71411850Sbrandon.potter@amd.com // Inside a VM, a real address is the address that guest OS would 71511850Sbrandon.potter@amd.com // interpret to be a physical address. To map to the physical address, 71611850Sbrandon.potter@amd.com // it still needs to undergo a translation. The instruction 71711850Sbrandon.potter@amd.com // translation code in the SPARC ITLB code assumes that the context is 71811850Sbrandon.potter@amd.com // zero (kernel-level) if real addressing is being used. 71911850Sbrandon.potter@amd.com int is_real_address = !bits(tlbdata, 5); 72011850Sbrandon.potter@amd.com 72111850Sbrandon.potter@amd.com // Grab the address space identifier register from the thread context. 72211850Sbrandon.potter@amd.com // XXX: Inspecting how setMiscReg and setMiscRegNoEffect behave for 72311850Sbrandon.potter@amd.com // MISCREG_ASI causes me to think that the ASI register implementation 72411850Sbrandon.potter@amd.com // might be bugged. The NoEffect variant changes the ASI register 72511850Sbrandon.potter@amd.com // value in the architectural state while the normal variant changes 72611850Sbrandon.potter@amd.com // the context field in the thread context's currently decoded request 72711850Sbrandon.potter@amd.com // but does not directly affect the ASI register value in the 72811850Sbrandon.potter@amd.com // architectural state. The ASI values and the context field in the 72911850Sbrandon.potter@amd.com // request packet seem to have completely different uses. 73011850Sbrandon.potter@amd.com MiscReg reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI); 73111850Sbrandon.potter@amd.com ASI asi = static_cast<ASI>(reg_asi); 73211850Sbrandon.potter@amd.com 73311850Sbrandon.potter@amd.com // The SPARC DTLB code assumes that traps are executed in context 73411850Sbrandon.potter@amd.com // zero if the asi value is ASI_IMPLICIT (which is 0x0). There's also 73511850Sbrandon.potter@amd.com // an assumption that the nucleus address space is being used, but 73611850Sbrandon.potter@amd.com // the context is the relevant issue since we need to pass it to TLB. 73711850Sbrandon.potter@amd.com bool trapped = bits(tlbdata, 18, 16) > 0; 73811850Sbrandon.potter@amd.com 73911850Sbrandon.potter@amd.com // Given the assumptions in the translateData code in the SPARC DTLB, 74011850Sbrandon.potter@amd.com // the logic works out to the following for the context. 74111850Sbrandon.potter@amd.com int context_id = ((!hpriv && !red && is_real_address) || 74211850Sbrandon.potter@amd.com asiIsReal(asi) || 74311850Sbrandon.potter@amd.com (trapped && asi == ASI_IMPLICIT)) 74411850Sbrandon.potter@amd.com ? 0 : primary_context; 74511850Sbrandon.potter@amd.com 74611850Sbrandon.potter@amd.com // The partition id distinguishes between virtualized environments. 74711850Sbrandon.potter@amd.com int const partition_id = 0; 74811850Sbrandon.potter@amd.com 74911850Sbrandon.potter@amd.com // Insert the TLB entry. 75011850Sbrandon.potter@amd.com // The entry specifying whether the address is "real" is set to 75111850Sbrandon.potter@amd.com // false for syscall emulation mode regardless of whether the 75211850Sbrandon.potter@amd.com // address is real in preceding code. Not sure sure that this is 75311850Sbrandon.potter@amd.com // correct, but also not sure if it matters at all. 75411850Sbrandon.potter@amd.com tc->getDTBPtr()->insert(alignedvaddr, partition_id, context_id, 75511850Sbrandon.potter@amd.com false, entry.pte); 7564997Sgblack@eecs.umich.edu } 7574997Sgblack@eecs.umich.edu} 7584997Sgblack@eecs.umich.edu 7597741Sgblack@eecs.umich.eduvoid 76010417Sandreas.hansson@arm.comSpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7613415Sgblack@eecs.umich.edu{ 7628778Sgblack@eecs.umich.edu if (FullSystem) { 7638778Sgblack@eecs.umich.edu SparcFaultBase::invoke(tc, inst); 7648806Sgblack@eecs.umich.edu return; 7658806Sgblack@eecs.umich.edu } 7663415Sgblack@eecs.umich.edu 7678806Sgblack@eecs.umich.edu doNormalFault(tc, trapType(), false); 7683415Sgblack@eecs.umich.edu 7698806Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 7703415Sgblack@eecs.umich.edu 77111851Sbrandon.potter@amd.com SparcProcess *sp = dynamic_cast<SparcProcess *>(p); 77211851Sbrandon.potter@amd.com assert(sp); 7738806Sgblack@eecs.umich.edu 7748806Sgblack@eecs.umich.edu // Then adjust the PC and NPC 77511851Sbrandon.potter@amd.com tc->pcState(sp->readSpillStart()); 7763415Sgblack@eecs.umich.edu} 7773415Sgblack@eecs.umich.edu 7787741Sgblack@eecs.umich.eduvoid 77910417Sandreas.hansson@arm.comFillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7803415Sgblack@eecs.umich.edu{ 7818778Sgblack@eecs.umich.edu if (FullSystem) { 7828778Sgblack@eecs.umich.edu SparcFaultBase::invoke(tc, inst); 7838806Sgblack@eecs.umich.edu return; 7848806Sgblack@eecs.umich.edu } 7853415Sgblack@eecs.umich.edu 7868806Sgblack@eecs.umich.edu doNormalFault(tc, trapType(), false); 7873415Sgblack@eecs.umich.edu 7888806Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 7893415Sgblack@eecs.umich.edu 79011851Sbrandon.potter@amd.com SparcProcess *sp = dynamic_cast<SparcProcess *>(p); 79111851Sbrandon.potter@amd.com assert(sp); 7928806Sgblack@eecs.umich.edu 7938806Sgblack@eecs.umich.edu // Then adjust the PC and NPC 79411851Sbrandon.potter@amd.com tc->pcState(sp->readFillStart()); 7953415Sgblack@eecs.umich.edu} 7963415Sgblack@eecs.umich.edu 7977741Sgblack@eecs.umich.eduvoid 79810417Sandreas.hansson@arm.comTrapInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7994111Sgblack@eecs.umich.edu{ 8008778Sgblack@eecs.umich.edu if (FullSystem) { 8018778Sgblack@eecs.umich.edu SparcFaultBase::invoke(tc, inst); 8028806Sgblack@eecs.umich.edu return; 8038806Sgblack@eecs.umich.edu } 8044111Sgblack@eecs.umich.edu 8058806Sgblack@eecs.umich.edu // In SE, this mechanism is how the process requests a service from 8068806Sgblack@eecs.umich.edu // the operating system. We'll get the process object from the thread 8078806Sgblack@eecs.umich.edu // context and let it service the request. 8084111Sgblack@eecs.umich.edu 8098806Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 8104111Sgblack@eecs.umich.edu 81111851Sbrandon.potter@amd.com SparcProcess *sp = dynamic_cast<SparcProcess *>(p); 81211851Sbrandon.potter@amd.com assert(sp); 8134111Sgblack@eecs.umich.edu 81411851Sbrandon.potter@amd.com sp->handleTrap(_n, tc); 8158806Sgblack@eecs.umich.edu 8168806Sgblack@eecs.umich.edu // We need to explicitly advance the pc, since that's not done for us 8178806Sgblack@eecs.umich.edu // on a faulting instruction 8188806Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 8198806Sgblack@eecs.umich.edu pc.advance(); 8208806Sgblack@eecs.umich.edu tc->pcState(pc); 8214111Sgblack@eecs.umich.edu} 8224111Sgblack@eecs.umich.edu 8232223SN/A} // namespace SparcISA 8242221SN/A 825