decoder.hh revision 9478
19020Sgblack@eecs.umich.edu/* 29020Sgblack@eecs.umich.edu * Copyright (c) 2012 Google 39020Sgblack@eecs.umich.edu * All rights reserved. 49020Sgblack@eecs.umich.edu * 59020Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 69020Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 79020Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 89020Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 99020Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 109020Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 119020Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 129020Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 139020Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 149020Sgblack@eecs.umich.edu * this software without specific prior written permission. 159020Sgblack@eecs.umich.edu * 169020Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179020Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189020Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199020Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209020Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219020Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229020Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239020Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249020Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259020Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269020Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279020Sgblack@eecs.umich.edu * 289020Sgblack@eecs.umich.edu * Authors: Gabe Black 299020Sgblack@eecs.umich.edu */ 309020Sgblack@eecs.umich.edu 319020Sgblack@eecs.umich.edu#ifndef __ARCH_SPARC_DECODER_HH__ 329020Sgblack@eecs.umich.edu#define __ARCH_SPARC_DECODER_HH__ 339020Sgblack@eecs.umich.edu 349024Sgblack@eecs.umich.edu#include "arch/generic/decode_cache.hh" 359023Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 369022Sgblack@eecs.umich.edu#include "arch/types.hh" 379024Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 389020Sgblack@eecs.umich.edu 399020Sgblack@eecs.umich.edunamespace SparcISA 409020Sgblack@eecs.umich.edu{ 419020Sgblack@eecs.umich.edu 429022Sgblack@eecs.umich.educlass Decoder 439022Sgblack@eecs.umich.edu{ 449022Sgblack@eecs.umich.edu protected: 459023Sgblack@eecs.umich.edu // The extended machine instruction being generated 469023Sgblack@eecs.umich.edu ExtMachInst emi; 479023Sgblack@eecs.umich.edu bool instDone; 489375Sgblack@eecs.umich.edu MiscReg asi; 499023Sgblack@eecs.umich.edu 509023Sgblack@eecs.umich.edu public: 519377Sgblack@eecs.umich.edu Decoder() : instDone(false), asi(0) 529023Sgblack@eecs.umich.edu {} 539023Sgblack@eecs.umich.edu 549023Sgblack@eecs.umich.edu void process() {} 559023Sgblack@eecs.umich.edu 569023Sgblack@eecs.umich.edu void 579023Sgblack@eecs.umich.edu reset() 589023Sgblack@eecs.umich.edu { 599023Sgblack@eecs.umich.edu instDone = false; 609023Sgblack@eecs.umich.edu } 619023Sgblack@eecs.umich.edu 629023Sgblack@eecs.umich.edu // Use this to give data to the predecoder. This should be used 639023Sgblack@eecs.umich.edu // when there is control flow. 649023Sgblack@eecs.umich.edu void 659023Sgblack@eecs.umich.edu moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) 669023Sgblack@eecs.umich.edu { 679023Sgblack@eecs.umich.edu emi = inst; 689023Sgblack@eecs.umich.edu // The I bit, bit 13, is used to figure out where the ASI 699023Sgblack@eecs.umich.edu // should come from. Use that in the ExtMachInst. This is 709023Sgblack@eecs.umich.edu // slightly redundant, but it removes the need to put a condition 719023Sgblack@eecs.umich.edu // into all the execute functions 729023Sgblack@eecs.umich.edu if (inst & (1 << 13)) { 739023Sgblack@eecs.umich.edu emi |= (static_cast<ExtMachInst>( 749375Sgblack@eecs.umich.edu asi << (sizeof(MachInst) * 8))); 759023Sgblack@eecs.umich.edu } else { 769023Sgblack@eecs.umich.edu emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5)) 779023Sgblack@eecs.umich.edu << (sizeof(MachInst) * 8)); 789023Sgblack@eecs.umich.edu } 799023Sgblack@eecs.umich.edu instDone = true; 809023Sgblack@eecs.umich.edu } 819023Sgblack@eecs.umich.edu 829023Sgblack@eecs.umich.edu bool 839023Sgblack@eecs.umich.edu needMoreBytes() 849023Sgblack@eecs.umich.edu { 859023Sgblack@eecs.umich.edu return true; 869023Sgblack@eecs.umich.edu } 879023Sgblack@eecs.umich.edu 889023Sgblack@eecs.umich.edu bool 899023Sgblack@eecs.umich.edu instReady() 909023Sgblack@eecs.umich.edu { 919023Sgblack@eecs.umich.edu return instDone; 929023Sgblack@eecs.umich.edu } 939023Sgblack@eecs.umich.edu 949375Sgblack@eecs.umich.edu void 959375Sgblack@eecs.umich.edu setContext(MiscReg _asi) 969375Sgblack@eecs.umich.edu { 979375Sgblack@eecs.umich.edu asi = _asi; 989375Sgblack@eecs.umich.edu } 999375Sgblack@eecs.umich.edu 1009478Snilay@cs.wisc.edu void takeOverFrom(Decoder *old) {} 1019478Snilay@cs.wisc.edu 1029023Sgblack@eecs.umich.edu protected: 1039022Sgblack@eecs.umich.edu /// A cache of decoded instruction objects. 1049024Sgblack@eecs.umich.edu static GenericISA::BasicDecodeCache defaultCache; 1059022Sgblack@eecs.umich.edu 1069022Sgblack@eecs.umich.edu public: 1079022Sgblack@eecs.umich.edu StaticInstPtr decodeInst(ExtMachInst mach_inst); 1089022Sgblack@eecs.umich.edu 1099022Sgblack@eecs.umich.edu /// Decode a machine instruction. 1109022Sgblack@eecs.umich.edu /// @param mach_inst The binary instruction to decode. 1119022Sgblack@eecs.umich.edu /// @retval A pointer to the corresponding StaticInst object. 1129022Sgblack@eecs.umich.edu StaticInstPtr 1139022Sgblack@eecs.umich.edu decode(ExtMachInst mach_inst, Addr addr) 1149022Sgblack@eecs.umich.edu { 1159022Sgblack@eecs.umich.edu return defaultCache.decode(this, mach_inst, addr); 1169022Sgblack@eecs.umich.edu } 1179023Sgblack@eecs.umich.edu 1189023Sgblack@eecs.umich.edu StaticInstPtr 1199023Sgblack@eecs.umich.edu decode(SparcISA::PCState &nextPC) 1209023Sgblack@eecs.umich.edu { 1219023Sgblack@eecs.umich.edu if (!instDone) 1229023Sgblack@eecs.umich.edu return NULL; 1239023Sgblack@eecs.umich.edu instDone = false; 1249023Sgblack@eecs.umich.edu return decode(emi, nextPC.instAddr()); 1259023Sgblack@eecs.umich.edu } 1269022Sgblack@eecs.umich.edu}; 1279020Sgblack@eecs.umich.edu 1289020Sgblack@eecs.umich.edu} // namespace SparcISA 1299020Sgblack@eecs.umich.edu 1309020Sgblack@eecs.umich.edu#endif // __ARCH_SPARC_DECODER_HH__ 131