decoder.hh revision 9023
19020Sgblack@eecs.umich.edu/* 29020Sgblack@eecs.umich.edu * Copyright (c) 2012 Google 39020Sgblack@eecs.umich.edu * All rights reserved. 49020Sgblack@eecs.umich.edu * 59020Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 69020Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 79020Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 89020Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 99020Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 109020Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 119020Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 129020Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 139020Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 149020Sgblack@eecs.umich.edu * this software without specific prior written permission. 159020Sgblack@eecs.umich.edu * 169020Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179020Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189020Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199020Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209020Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219020Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229020Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239020Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249020Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259020Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269020Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279020Sgblack@eecs.umich.edu * 289020Sgblack@eecs.umich.edu * Authors: Gabe Black 299020Sgblack@eecs.umich.edu */ 309020Sgblack@eecs.umich.edu 319020Sgblack@eecs.umich.edu#ifndef __ARCH_SPARC_DECODER_HH__ 329020Sgblack@eecs.umich.edu#define __ARCH_SPARC_DECODER_HH__ 339020Sgblack@eecs.umich.edu 349023Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 359022Sgblack@eecs.umich.edu#include "arch/types.hh" 369022Sgblack@eecs.umich.edu#include "cpu/decode_cache.hh" 379022Sgblack@eecs.umich.edu#include "cpu/static_inst_fwd.hh" 389023Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 399023Sgblack@eecs.umich.edu 409023Sgblack@eecs.umich.educlass ThreadContext; 419020Sgblack@eecs.umich.edu 429020Sgblack@eecs.umich.edunamespace SparcISA 439020Sgblack@eecs.umich.edu{ 449020Sgblack@eecs.umich.edu 459022Sgblack@eecs.umich.educlass Decoder 469022Sgblack@eecs.umich.edu{ 479022Sgblack@eecs.umich.edu protected: 489023Sgblack@eecs.umich.edu ThreadContext * tc; 499023Sgblack@eecs.umich.edu // The extended machine instruction being generated 509023Sgblack@eecs.umich.edu ExtMachInst emi; 519023Sgblack@eecs.umich.edu bool instDone; 529023Sgblack@eecs.umich.edu 539023Sgblack@eecs.umich.edu public: 549023Sgblack@eecs.umich.edu Decoder(ThreadContext * _tc) : tc(_tc), instDone(false) 559023Sgblack@eecs.umich.edu {} 569023Sgblack@eecs.umich.edu 579023Sgblack@eecs.umich.edu ThreadContext * 589023Sgblack@eecs.umich.edu getTC() 599023Sgblack@eecs.umich.edu { 609023Sgblack@eecs.umich.edu return tc; 619023Sgblack@eecs.umich.edu } 629023Sgblack@eecs.umich.edu 639023Sgblack@eecs.umich.edu void 649023Sgblack@eecs.umich.edu setTC(ThreadContext * _tc) 659023Sgblack@eecs.umich.edu { 669023Sgblack@eecs.umich.edu tc = _tc; 679023Sgblack@eecs.umich.edu } 689023Sgblack@eecs.umich.edu 699023Sgblack@eecs.umich.edu void process() {} 709023Sgblack@eecs.umich.edu 719023Sgblack@eecs.umich.edu void 729023Sgblack@eecs.umich.edu reset() 739023Sgblack@eecs.umich.edu { 749023Sgblack@eecs.umich.edu instDone = false; 759023Sgblack@eecs.umich.edu } 769023Sgblack@eecs.umich.edu 779023Sgblack@eecs.umich.edu // Use this to give data to the predecoder. This should be used 789023Sgblack@eecs.umich.edu // when there is control flow. 799023Sgblack@eecs.umich.edu void 809023Sgblack@eecs.umich.edu moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) 819023Sgblack@eecs.umich.edu { 829023Sgblack@eecs.umich.edu emi = inst; 839023Sgblack@eecs.umich.edu // The I bit, bit 13, is used to figure out where the ASI 849023Sgblack@eecs.umich.edu // should come from. Use that in the ExtMachInst. This is 859023Sgblack@eecs.umich.edu // slightly redundant, but it removes the need to put a condition 869023Sgblack@eecs.umich.edu // into all the execute functions 879023Sgblack@eecs.umich.edu if (inst & (1 << 13)) { 889023Sgblack@eecs.umich.edu emi |= (static_cast<ExtMachInst>( 899023Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_ASI)) 909023Sgblack@eecs.umich.edu << (sizeof(MachInst) * 8)); 919023Sgblack@eecs.umich.edu } else { 929023Sgblack@eecs.umich.edu emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5)) 939023Sgblack@eecs.umich.edu << (sizeof(MachInst) * 8)); 949023Sgblack@eecs.umich.edu } 959023Sgblack@eecs.umich.edu instDone = true; 969023Sgblack@eecs.umich.edu } 979023Sgblack@eecs.umich.edu 989023Sgblack@eecs.umich.edu bool 999023Sgblack@eecs.umich.edu needMoreBytes() 1009023Sgblack@eecs.umich.edu { 1019023Sgblack@eecs.umich.edu return true; 1029023Sgblack@eecs.umich.edu } 1039023Sgblack@eecs.umich.edu 1049023Sgblack@eecs.umich.edu bool 1059023Sgblack@eecs.umich.edu instReady() 1069023Sgblack@eecs.umich.edu { 1079023Sgblack@eecs.umich.edu return instDone; 1089023Sgblack@eecs.umich.edu } 1099023Sgblack@eecs.umich.edu 1109023Sgblack@eecs.umich.edu protected: 1119022Sgblack@eecs.umich.edu /// A cache of decoded instruction objects. 1129022Sgblack@eecs.umich.edu static DecodeCache defaultCache; 1139022Sgblack@eecs.umich.edu 1149022Sgblack@eecs.umich.edu public: 1159022Sgblack@eecs.umich.edu StaticInstPtr decodeInst(ExtMachInst mach_inst); 1169022Sgblack@eecs.umich.edu 1179022Sgblack@eecs.umich.edu /// Decode a machine instruction. 1189022Sgblack@eecs.umich.edu /// @param mach_inst The binary instruction to decode. 1199022Sgblack@eecs.umich.edu /// @retval A pointer to the corresponding StaticInst object. 1209022Sgblack@eecs.umich.edu StaticInstPtr 1219022Sgblack@eecs.umich.edu decode(ExtMachInst mach_inst, Addr addr) 1229022Sgblack@eecs.umich.edu { 1239022Sgblack@eecs.umich.edu return defaultCache.decode(this, mach_inst, addr); 1249022Sgblack@eecs.umich.edu } 1259023Sgblack@eecs.umich.edu 1269023Sgblack@eecs.umich.edu StaticInstPtr 1279023Sgblack@eecs.umich.edu decode(SparcISA::PCState &nextPC) 1289023Sgblack@eecs.umich.edu { 1299023Sgblack@eecs.umich.edu if (!instDone) 1309023Sgblack@eecs.umich.edu return NULL; 1319023Sgblack@eecs.umich.edu instDone = false; 1329023Sgblack@eecs.umich.edu return decode(emi, nextPC.instAddr()); 1339023Sgblack@eecs.umich.edu } 1349022Sgblack@eecs.umich.edu}; 1359020Sgblack@eecs.umich.edu 1369020Sgblack@eecs.umich.edu} // namespace SparcISA 1379020Sgblack@eecs.umich.edu 1389020Sgblack@eecs.umich.edu#endif // __ARCH_SPARC_DECODER_HH__ 139