utility.hh revision 11723
111723Sar4jc@virginia.edu/* 211723Sar4jc@virginia.edu * Copyright (c) 2013 ARM Limited 311723Sar4jc@virginia.edu * Copyright (c) 2014-2015 Sven Karlsson 411723Sar4jc@virginia.edu * All rights reserved 511723Sar4jc@virginia.edu * 611723Sar4jc@virginia.edu * The license below extends only to copyright in the software and shall 711723Sar4jc@virginia.edu * not be construed as granting a license to any other intellectual 811723Sar4jc@virginia.edu * property including but not limited to intellectual property relating 911723Sar4jc@virginia.edu * to a hardware implementation of the functionality of the software 1011723Sar4jc@virginia.edu * licensed hereunder. You may use the software subject to the license 1111723Sar4jc@virginia.edu * terms below provided that you ensure that this notice is replicated 1211723Sar4jc@virginia.edu * unmodified and in its entirety in all distributions of the software, 1311723Sar4jc@virginia.edu * modified or unmodified, in source code or in binary form. 1411723Sar4jc@virginia.edu * 1511723Sar4jc@virginia.edu * Copyright (c) 2016 The University of Virginia 1611723Sar4jc@virginia.edu * All rights reserved. 1711723Sar4jc@virginia.edu * 1811723Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 1911723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 2011723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 2111723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 2211723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 2311723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 2411723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 2511723Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 2611723Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 2711723Sar4jc@virginia.edu * this software without specific prior written permission. 2811723Sar4jc@virginia.edu * 2911723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3011723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3211723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3811723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011723Sar4jc@virginia.edu * 4111723Sar4jc@virginia.edu * Authors: Andreas Hansson 4211723Sar4jc@virginia.edu * Sven Karlsson 4311723Sar4jc@virginia.edu * Alec Roelke 4411723Sar4jc@virginia.edu */ 4511723Sar4jc@virginia.edu 4611723Sar4jc@virginia.edu#ifndef __ARCH_RISCV_UTILITY_HH__ 4711723Sar4jc@virginia.edu#define __ARCH_RISCV_UTILITY_HH__ 4811723Sar4jc@virginia.edu 4911723Sar4jc@virginia.edu#include <cmath> 5011723Sar4jc@virginia.edu#include <cstdint> 5111723Sar4jc@virginia.edu 5211723Sar4jc@virginia.edu#include "base/types.hh" 5311723Sar4jc@virginia.edu#include "cpu/static_inst.hh" 5411723Sar4jc@virginia.edu#include "cpu/thread_context.hh" 5511723Sar4jc@virginia.edu 5611723Sar4jc@virginia.edunamespace RiscvISA 5711723Sar4jc@virginia.edu{ 5811723Sar4jc@virginia.edu 5911723Sar4jc@virginia.eduinline PCState 6011723Sar4jc@virginia.edubuildRetPC(const PCState &curPC, const PCState &callPC) 6111723Sar4jc@virginia.edu{ 6211723Sar4jc@virginia.edu PCState retPC = callPC; 6311723Sar4jc@virginia.edu retPC.advance(); 6411723Sar4jc@virginia.edu retPC.pc(curPC.npc()); 6511723Sar4jc@virginia.edu return retPC; 6611723Sar4jc@virginia.edu} 6711723Sar4jc@virginia.edu 6811723Sar4jc@virginia.eduinline uint64_t 6911723Sar4jc@virginia.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 7011723Sar4jc@virginia.edu{ 7111723Sar4jc@virginia.edu return 0; 7211723Sar4jc@virginia.edu} 7311723Sar4jc@virginia.edu 7411723Sar4jc@virginia.eduinline void startupCPU(ThreadContext *tc, int cpuId) 7511723Sar4jc@virginia.edu{ 7611723Sar4jc@virginia.edu} 7711723Sar4jc@virginia.edu 7811723Sar4jc@virginia.eduinline void 7911723Sar4jc@virginia.educopyRegs(ThreadContext *src, ThreadContext *dest) 8011723Sar4jc@virginia.edu{ 8111723Sar4jc@virginia.edu // First loop through the integer registers. 8211723Sar4jc@virginia.edu for (int i = 0; i < NumIntRegs; ++i) 8311723Sar4jc@virginia.edu dest->setIntReg(i, src->readIntReg(i)); 8411723Sar4jc@virginia.edu 8511723Sar4jc@virginia.edu // Lastly copy PC/NPC 8611723Sar4jc@virginia.edu dest->pcState(src->pcState()); 8711723Sar4jc@virginia.edu} 8811723Sar4jc@virginia.edu 8911723Sar4jc@virginia.eduinline void 9011723Sar4jc@virginia.eduskipFunction(ThreadContext *tc) 9111723Sar4jc@virginia.edu{ 9211723Sar4jc@virginia.edu panic("Not Implemented for Riscv"); 9311723Sar4jc@virginia.edu} 9411723Sar4jc@virginia.edu 9511723Sar4jc@virginia.eduinline void 9611723Sar4jc@virginia.eduadvancePC(PCState &pc, const StaticInstPtr &inst) 9711723Sar4jc@virginia.edu{ 9811723Sar4jc@virginia.edu inst->advancePC(pc); 9911723Sar4jc@virginia.edu} 10011723Sar4jc@virginia.edu 10111723Sar4jc@virginia.edustatic inline bool 10211723Sar4jc@virginia.eduinUserMode(ThreadContext *tc) 10311723Sar4jc@virginia.edu{ 10411723Sar4jc@virginia.edu return true; 10511723Sar4jc@virginia.edu} 10611723Sar4jc@virginia.edu 10711723Sar4jc@virginia.eduinline uint64_t 10811723Sar4jc@virginia.edugetExecutingAsid(ThreadContext *tc) 10911723Sar4jc@virginia.edu{ 11011723Sar4jc@virginia.edu return 0; 11111723Sar4jc@virginia.edu} 11211723Sar4jc@virginia.edu 11311723Sar4jc@virginia.eduinline void 11411723Sar4jc@virginia.eduinitCPU(ThreadContext *, int cpuId) 11511723Sar4jc@virginia.edu{ 11611723Sar4jc@virginia.edu panic("initCPU not implemented for Riscv.\n"); 11711723Sar4jc@virginia.edu} 11811723Sar4jc@virginia.edu 11911723Sar4jc@virginia.edu} // namespace RiscvISA 12011723Sar4jc@virginia.edu 12111723Sar4jc@virginia.edu#endif // __ARCH_RISCV_UTILITY_HH__ 122