tlb.cc revision 12808:f275fd1244ce
110801Srene.dejong@arm.com/* 210801Srene.dejong@arm.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 310801Srene.dejong@arm.com * Copyright (c) 2007 MIPS Technologies, Inc. 410801Srene.dejong@arm.com * All rights reserved. 510801Srene.dejong@arm.com * 610801Srene.dejong@arm.com * Redistribution and use in source and binary forms, with or without 710801Srene.dejong@arm.com * modification, are permitted provided that the following conditions are 810801Srene.dejong@arm.com * met: redistributions of source code must retain the above copyright 910801Srene.dejong@arm.com * notice, this list of conditions and the following disclaimer; 1010801Srene.dejong@arm.com * redistributions in binary form must reproduce the above copyright 1110801Srene.dejong@arm.com * notice, this list of conditions and the following disclaimer in the 1210801Srene.dejong@arm.com * documentation and/or other materials provided with the distribution; 1310801Srene.dejong@arm.com * neither the name of the copyright holders nor the names of its 1410801Srene.dejong@arm.com * contributors may be used to endorse or promote products derived from 1510801Srene.dejong@arm.com * this software without specific prior written permission. 1610801Srene.dejong@arm.com * 1710801Srene.dejong@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1810801Srene.dejong@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1910801Srene.dejong@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2010801Srene.dejong@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2110801Srene.dejong@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2210801Srene.dejong@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2310801Srene.dejong@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2410801Srene.dejong@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2510801Srene.dejong@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2610801Srene.dejong@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2710801Srene.dejong@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2810801Srene.dejong@arm.com * 2910801Srene.dejong@arm.com * Authors: Nathan Binkert 3010801Srene.dejong@arm.com * Steve Reinhardt 3110801Srene.dejong@arm.com * Jaidev Patwardhan 3210801Srene.dejong@arm.com * Zhengxing Li 3310801Srene.dejong@arm.com * Deyuan Guo 3410801Srene.dejong@arm.com */ 3510801Srene.dejong@arm.com 3610801Srene.dejong@arm.com#include "arch/riscv/tlb.hh" 3710801Srene.dejong@arm.com 3810801Srene.dejong@arm.com#include <string> 3910801Srene.dejong@arm.com#include <vector> 4010801Srene.dejong@arm.com 4110801Srene.dejong@arm.com#include "arch/riscv/faults.hh" 4210801Srene.dejong@arm.com#include "arch/riscv/pagetable.hh" 4310801Srene.dejong@arm.com#include "arch/riscv/pra_constants.hh" 4410801Srene.dejong@arm.com#include "arch/riscv/system.hh" 4510801Srene.dejong@arm.com#include "arch/riscv/utility.hh" 4610801Srene.dejong@arm.com#include "base/inifile.hh" 4710801Srene.dejong@arm.com#include "base/str.hh" 4810801Srene.dejong@arm.com#include "base/trace.hh" 4910801Srene.dejong@arm.com#include "cpu/thread_context.hh" 5010801Srene.dejong@arm.com#include "debug/RiscvTLB.hh" 5110801Srene.dejong@arm.com#include "debug/TLB.hh" 5210801Srene.dejong@arm.com#include "mem/page_table.hh" 5310801Srene.dejong@arm.com#include "params/RiscvTLB.hh" 5410801Srene.dejong@arm.com#include "sim/full_system.hh" 5510801Srene.dejong@arm.com#include "sim/process.hh" 5610801Srene.dejong@arm.com 5710801Srene.dejong@arm.comusing namespace std; 5810801Srene.dejong@arm.comusing namespace RiscvISA; 5910801Srene.dejong@arm.com 6010801Srene.dejong@arm.com/////////////////////////////////////////////////////////////////////// 6110801Srene.dejong@arm.com// 6210801Srene.dejong@arm.com// RISC-V TLB 6310801Srene.dejong@arm.com// 6410801Srene.dejong@arm.com 6510801Srene.dejong@arm.comTLB::TLB(const Params *p) 6610801Srene.dejong@arm.com : BaseTLB(p), size(p->size), nlu(0) 6710801Srene.dejong@arm.com{ 6810801Srene.dejong@arm.com table = new PTE[size]; 6910801Srene.dejong@arm.com memset(table, 0, sizeof(PTE[size])); 7010801Srene.dejong@arm.com smallPages = 0; 7110801Srene.dejong@arm.com} 7210801Srene.dejong@arm.com 7310801Srene.dejong@arm.comTLB::~TLB() 7410801Srene.dejong@arm.com{ 7510801Srene.dejong@arm.com if (table) 7610801Srene.dejong@arm.com delete [] table; 7710801Srene.dejong@arm.com} 7810801Srene.dejong@arm.com 7910801Srene.dejong@arm.com// look up an entry in the TLB 8010801Srene.dejong@arm.comRiscvISA::PTE * 8110801Srene.dejong@arm.comTLB::lookup(Addr vpn, uint8_t asn) const 8210801Srene.dejong@arm.com{ 8310801Srene.dejong@arm.com // assume not found... 8410801Srene.dejong@arm.com PTE *retval = nullptr; 8510801Srene.dejong@arm.com PageTable::const_iterator i = lookupTable.find(vpn); 8610801Srene.dejong@arm.com if (i != lookupTable.end()) { 8710801Srene.dejong@arm.com while (i->first == vpn) { 8810801Srene.dejong@arm.com int index = i->second; 8910801Srene.dejong@arm.com PTE *pte = &table[index]; 9010801Srene.dejong@arm.com 9110801Srene.dejong@arm.com /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 9210801Srene.dejong@arm.com Addr Mask = pte->Mask; 9310801Srene.dejong@arm.com Addr InvMask = ~Mask; 9410801Srene.dejong@arm.com Addr VPN = pte->VPN; 9510801Srene.dejong@arm.com if (((vpn & InvMask) == (VPN & InvMask)) && 9610801Srene.dejong@arm.com (pte->G || (asn == pte->asid))) { 9710801Srene.dejong@arm.com // We have a VPN + ASID Match 9810801Srene.dejong@arm.com retval = pte; 9910801Srene.dejong@arm.com break; 10010801Srene.dejong@arm.com } 10110801Srene.dejong@arm.com ++i; 10210801Srene.dejong@arm.com } 10310801Srene.dejong@arm.com } 10410801Srene.dejong@arm.com 10510801Srene.dejong@arm.com DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 10610801Srene.dejong@arm.com retval ? "hit" : "miss", retval ? retval->PFN1 : 0); 10710801Srene.dejong@arm.com return retval; 10810801Srene.dejong@arm.com} 10910801Srene.dejong@arm.com 11010801Srene.dejong@arm.comRiscvISA::PTE* 11110801Srene.dejong@arm.comTLB::getEntry(unsigned Index) const 11210801Srene.dejong@arm.com{ 11310801Srene.dejong@arm.com // Make sure that Index is valid 11410801Srene.dejong@arm.com assert(Index<size); 11510801Srene.dejong@arm.com return &table[Index]; 11610801Srene.dejong@arm.com} 11710801Srene.dejong@arm.com 11810801Srene.dejong@arm.comint 11910801Srene.dejong@arm.comTLB::probeEntry(Addr vpn, uint8_t asn) const 12010801Srene.dejong@arm.com{ 12110801Srene.dejong@arm.com // assume not found... 12210801Srene.dejong@arm.com int Ind = -1; 12310801Srene.dejong@arm.com PageTable::const_iterator i = lookupTable.find(vpn); 12410801Srene.dejong@arm.com if (i != lookupTable.end()) { 12510801Srene.dejong@arm.com while (i->first == vpn) { 12610801Srene.dejong@arm.com int index = i->second; 12710801Srene.dejong@arm.com PTE *pte = &table[index]; 12810801Srene.dejong@arm.com 12910801Srene.dejong@arm.com /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 13010801Srene.dejong@arm.com Addr Mask = pte->Mask; 13110801Srene.dejong@arm.com Addr InvMask = ~Mask; 13210801Srene.dejong@arm.com Addr VPN = pte->VPN; 13310801Srene.dejong@arm.com if (((vpn & InvMask) == (VPN & InvMask)) && 13410801Srene.dejong@arm.com (pte->G || (asn == pte->asid))) { 13510801Srene.dejong@arm.com // We have a VPN + ASID Match 13610801Srene.dejong@arm.com Ind = index; 13710801Srene.dejong@arm.com break; 13810801Srene.dejong@arm.com } 13910801Srene.dejong@arm.com ++i; 14010801Srene.dejong@arm.com } 14110801Srene.dejong@arm.com } 14210801Srene.dejong@arm.com DPRINTF(RiscvTLB,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind); 14310801Srene.dejong@arm.com return Ind; 14410801Srene.dejong@arm.com} 14510801Srene.dejong@arm.com 14610801Srene.dejong@arm.cominline Fault 14710801Srene.dejong@arm.comTLB::checkCacheability(const RequestPtr &req) 14810801Srene.dejong@arm.com{ 14910801Srene.dejong@arm.com Addr VAddrUncacheable = 0xA0000000; 15010801Srene.dejong@arm.com // In MIPS, cacheability is controlled by certain bits of the virtual 15110801Srene.dejong@arm.com // address or by the TLB entry 15210801Srene.dejong@arm.com if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { 15310801Srene.dejong@arm.com // mark request as uncacheable 15410801Srene.dejong@arm.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 15510801Srene.dejong@arm.com } 15610801Srene.dejong@arm.com return NoFault; 15710801Srene.dejong@arm.com} 15810801Srene.dejong@arm.com 15910801Srene.dejong@arm.comvoid 16010801Srene.dejong@arm.comTLB::insertAt(PTE &pte, unsigned Index, int _smallPages) 16110801Srene.dejong@arm.com{ 16210801Srene.dejong@arm.com smallPages = _smallPages; 16310801Srene.dejong@arm.com if (Index > size) { 16410801Srene.dejong@arm.com warn("Attempted to write at index (%d) beyond TLB size (%d)", 16510801Srene.dejong@arm.com Index, size); 16610801Srene.dejong@arm.com } else { 16710801Srene.dejong@arm.com // Update TLB 16810801Srene.dejong@arm.com DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n", 16910801Srene.dejong@arm.com Index, pte.Mask << 11, 17010801Srene.dejong@arm.com ((pte.VPN << 11) | pte.asid), 17110801Srene.dejong@arm.com ((pte.PFN0 << 6) | (pte.C0 << 3) | 17210801Srene.dejong@arm.com (pte.D0 << 2) | (pte.V0 <<1) | pte.G), 17310801Srene.dejong@arm.com ((pte.PFN1 <<6) | (pte.C1 << 3) | 17410801Srene.dejong@arm.com (pte.D1 << 2) | (pte.V1 <<1) | pte.G)); 17510801Srene.dejong@arm.com if (table[Index].V0 || table[Index].V1) { 17610801Srene.dejong@arm.com // Previous entry is valid 17710801Srene.dejong@arm.com PageTable::iterator i = lookupTable.find(table[Index].VPN); 17810801Srene.dejong@arm.com lookupTable.erase(i); 17910801Srene.dejong@arm.com } 18010801Srene.dejong@arm.com table[Index]=pte; 18110801Srene.dejong@arm.com // Update fast lookup table 18210801Srene.dejong@arm.com lookupTable.insert(make_pair(table[Index].VPN, Index)); 18310801Srene.dejong@arm.com } 18410801Srene.dejong@arm.com} 18510801Srene.dejong@arm.com 18610801Srene.dejong@arm.com// insert a new TLB entry 18710801Srene.dejong@arm.comvoid 18810801Srene.dejong@arm.comTLB::insert(Addr addr, PTE &pte) 18910801Srene.dejong@arm.com{ 19010801Srene.dejong@arm.com fatal("TLB Insert not yet implemented\n"); 19110801Srene.dejong@arm.com} 19210801Srene.dejong@arm.com 19310801Srene.dejong@arm.comvoid 19410801Srene.dejong@arm.comTLB::flushAll() 19510801Srene.dejong@arm.com{ 19610801Srene.dejong@arm.com DPRINTF(TLB, "flushAll\n"); 19710801Srene.dejong@arm.com memset(table, 0, sizeof(PTE[size])); 19810801Srene.dejong@arm.com lookupTable.clear(); 19910801Srene.dejong@arm.com nlu = 0; 20010801Srene.dejong@arm.com} 20110801Srene.dejong@arm.com 20210801Srene.dejong@arm.comvoid 20310801Srene.dejong@arm.comTLB::serialize(CheckpointOut &cp) const 20410801Srene.dejong@arm.com{ 20510801Srene.dejong@arm.com SERIALIZE_SCALAR(size); 20610801Srene.dejong@arm.com SERIALIZE_SCALAR(nlu); 20710801Srene.dejong@arm.com 20810801Srene.dejong@arm.com for (int i = 0; i < size; i++) { 20910801Srene.dejong@arm.com ScopedCheckpointSection sec(cp, csprintf("PTE%d", i)); 21010801Srene.dejong@arm.com table[i].serialize(cp); 21110801Srene.dejong@arm.com } 21210801Srene.dejong@arm.com} 21310801Srene.dejong@arm.com 21410801Srene.dejong@arm.comvoid 21510801Srene.dejong@arm.comTLB::unserialize(CheckpointIn &cp) 21610801Srene.dejong@arm.com{ 21710801Srene.dejong@arm.com UNSERIALIZE_SCALAR(size); 21810801Srene.dejong@arm.com UNSERIALIZE_SCALAR(nlu); 21910801Srene.dejong@arm.com 22010801Srene.dejong@arm.com for (int i = 0; i < size; i++) { 22110801Srene.dejong@arm.com ScopedCheckpointSection sec(cp, csprintf("PTE%d", i)); 22210801Srene.dejong@arm.com table[i].unserialize(cp); 22310801Srene.dejong@arm.com if (table[i].V0 || table[i].V1) { 22410801Srene.dejong@arm.com lookupTable.insert(make_pair(table[i].VPN, i)); 22510801Srene.dejong@arm.com } 22610801Srene.dejong@arm.com } 22710801Srene.dejong@arm.com} 22810801Srene.dejong@arm.com 22910801Srene.dejong@arm.comvoid 23010801Srene.dejong@arm.comTLB::regStats() 23110801Srene.dejong@arm.com{ 23210801Srene.dejong@arm.com BaseTLB::regStats(); 23310801Srene.dejong@arm.com 23410801Srene.dejong@arm.com read_hits 23510801Srene.dejong@arm.com .name(name() + ".read_hits") 23610801Srene.dejong@arm.com .desc("DTB read hits") 23710801Srene.dejong@arm.com ; 23810801Srene.dejong@arm.com 23910801Srene.dejong@arm.com read_misses 24010801Srene.dejong@arm.com .name(name() + ".read_misses") 24110801Srene.dejong@arm.com .desc("DTB read misses") 24210801Srene.dejong@arm.com ; 24310801Srene.dejong@arm.com 24410801Srene.dejong@arm.com 24510801Srene.dejong@arm.com read_accesses 24610801Srene.dejong@arm.com .name(name() + ".read_accesses") 24710801Srene.dejong@arm.com .desc("DTB read accesses") 24810801Srene.dejong@arm.com ; 24910801Srene.dejong@arm.com 25010801Srene.dejong@arm.com write_hits 25110801Srene.dejong@arm.com .name(name() + ".write_hits") 25210801Srene.dejong@arm.com .desc("DTB write hits") 25310801Srene.dejong@arm.com ; 25410801Srene.dejong@arm.com 25510801Srene.dejong@arm.com write_misses 25610801Srene.dejong@arm.com .name(name() + ".write_misses") 25710801Srene.dejong@arm.com .desc("DTB write misses") 25810801Srene.dejong@arm.com ; 25910801Srene.dejong@arm.com 26010801Srene.dejong@arm.com 26110801Srene.dejong@arm.com write_accesses 26210801Srene.dejong@arm.com .name(name() + ".write_accesses") 26310801Srene.dejong@arm.com .desc("DTB write accesses") 26410801Srene.dejong@arm.com ; 26510801Srene.dejong@arm.com 26610801Srene.dejong@arm.com hits 26710801Srene.dejong@arm.com .name(name() + ".hits") 26810801Srene.dejong@arm.com .desc("DTB hits") 26910801Srene.dejong@arm.com ; 27010801Srene.dejong@arm.com 27110801Srene.dejong@arm.com misses 27210801Srene.dejong@arm.com .name(name() + ".misses") 27310801Srene.dejong@arm.com .desc("DTB misses") 27410801Srene.dejong@arm.com ; 27510801Srene.dejong@arm.com 27610801Srene.dejong@arm.com accesses 27710801Srene.dejong@arm.com .name(name() + ".accesses") 27810801Srene.dejong@arm.com .desc("DTB accesses") 27910801Srene.dejong@arm.com ; 28010801Srene.dejong@arm.com 28110801Srene.dejong@arm.com hits = read_hits + write_hits; 28210801Srene.dejong@arm.com misses = read_misses + write_misses; 28310801Srene.dejong@arm.com accesses = read_accesses + write_accesses; 28410801Srene.dejong@arm.com} 28510801Srene.dejong@arm.com 28610801Srene.dejong@arm.comFault 28710801Srene.dejong@arm.comTLB::translateInst(const RequestPtr &req, ThreadContext *tc) 28810801Srene.dejong@arm.com{ 28910801Srene.dejong@arm.com if (FullSystem) { 29010801Srene.dejong@arm.com /** 29110801Srene.dejong@arm.com * check if we simulate a bare metal system 29210801Srene.dejong@arm.com * if so, we have no tlb, phys addr == virt addr 29310801Srene.dejong@arm.com */ 29410801Srene.dejong@arm.com if (static_cast<RiscvSystem *>(tc->getSystemPtr())->isBareMetal()) 29510801Srene.dejong@arm.com req->setFlags(Request::PHYSICAL); 29610801Srene.dejong@arm.com 29710801Srene.dejong@arm.com if (req->getFlags() & Request::PHYSICAL) { 29810801Srene.dejong@arm.com /** 29910801Srene.dejong@arm.com * we simply set the virtual address to physical address 30010801Srene.dejong@arm.com */ 30110801Srene.dejong@arm.com req->setPaddr(req->getVaddr()); 30210801Srene.dejong@arm.com return checkCacheability(req); 30310801Srene.dejong@arm.com } else { 30410801Srene.dejong@arm.com /** 30510801Srene.dejong@arm.com * as we currently support bare metal only, we throw a panic, 30610801Srene.dejong@arm.com * if it is not a bare metal system 30710801Srene.dejong@arm.com */ 30810801Srene.dejong@arm.com panic("translateInst not implemented in RISC-V.\n"); 30910801Srene.dejong@arm.com } 31010801Srene.dejong@arm.com } else { 31110801Srene.dejong@arm.com Process * p = tc->getProcessPtr(); 31210801Srene.dejong@arm.com 31310801Srene.dejong@arm.com Fault fault = p->pTable->translate(req); 31410801Srene.dejong@arm.com if (fault != NoFault) 31510801Srene.dejong@arm.com return fault; 31610801Srene.dejong@arm.com 31710801Srene.dejong@arm.com return NoFault; 31810801Srene.dejong@arm.com } 31910801Srene.dejong@arm.com} 32010801Srene.dejong@arm.com 32110801Srene.dejong@arm.comFault 32210801Srene.dejong@arm.comTLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write) 32310801Srene.dejong@arm.com{ 32410801Srene.dejong@arm.com if (FullSystem) { 32510801Srene.dejong@arm.com /** 32610801Srene.dejong@arm.com * check if we simulate a bare metal system 32710801Srene.dejong@arm.com * if so, we have no tlb, phys addr == virt addr 32810801Srene.dejong@arm.com */ 32910801Srene.dejong@arm.com if (static_cast<RiscvSystem *>(tc->getSystemPtr())->isBareMetal()) 33010801Srene.dejong@arm.com req->setFlags(Request::PHYSICAL); 33110801Srene.dejong@arm.com 33210801Srene.dejong@arm.com if (req->getFlags() & Request::PHYSICAL) { 33310801Srene.dejong@arm.com /** 33410801Srene.dejong@arm.com * we simply set the virtual address to physical address 33510801Srene.dejong@arm.com */ 33610801Srene.dejong@arm.com req->setPaddr(req->getVaddr()); 33710801Srene.dejong@arm.com return checkCacheability(req); 33810801Srene.dejong@arm.com } else { 33910801Srene.dejong@arm.com /** 34010801Srene.dejong@arm.com * as we currently support bare metal only, we throw a panic, 34110801Srene.dejong@arm.com * if it is not a bare metal system 34210801Srene.dejong@arm.com */ 34310801Srene.dejong@arm.com panic("translateData not implemented in RISC-V.\n"); 34410801Srene.dejong@arm.com } 34510801Srene.dejong@arm.com } else { 34610801Srene.dejong@arm.com // In the O3 CPU model, sometimes a memory access will be speculatively 34710801Srene.dejong@arm.com // executed along a branch that will end up not being taken where the 34810801Srene.dejong@arm.com // address is invalid. In that case, return a fault rather than trying 34910801Srene.dejong@arm.com // to translate it (which will cause a panic). Since RISC-V allows 35010801Srene.dejong@arm.com // unaligned memory accesses, this should only happen if the request's 35110801Srene.dejong@arm.com // length is long enough to wrap around from the end of the memory to 35210801Srene.dejong@arm.com // the start. 35310801Srene.dejong@arm.com assert(req->getSize() > 0); 35410801Srene.dejong@arm.com if (req->getVaddr() + req->getSize() - 1 < req->getVaddr()) 35510801Srene.dejong@arm.com return make_shared<GenericPageTableFault>(req->getVaddr()); 35610801Srene.dejong@arm.com 35710801Srene.dejong@arm.com Process * p = tc->getProcessPtr(); 35810801Srene.dejong@arm.com 35910801Srene.dejong@arm.com Fault fault = p->pTable->translate(req); 36010801Srene.dejong@arm.com if (fault != NoFault) 36110801Srene.dejong@arm.com return fault; 36210801Srene.dejong@arm.com 36310801Srene.dejong@arm.com return NoFault; 36410801Srene.dejong@arm.com } 36510801Srene.dejong@arm.com} 36610801Srene.dejong@arm.com 36710801Srene.dejong@arm.comFault 36810801Srene.dejong@arm.comTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) 36910801Srene.dejong@arm.com{ 37010801Srene.dejong@arm.com if (mode == Execute) 37110801Srene.dejong@arm.com return translateInst(req, tc); 37210801Srene.dejong@arm.com else 37310801Srene.dejong@arm.com return translateData(req, tc, mode == Write); 37410801Srene.dejong@arm.com} 37510801Srene.dejong@arm.com 37610801Srene.dejong@arm.comvoid 37710801Srene.dejong@arm.comTLB::translateTiming(const RequestPtr &req, ThreadContext *tc, 37810801Srene.dejong@arm.com Translation *translation, Mode mode) 37910801Srene.dejong@arm.com{ 38010801Srene.dejong@arm.com assert(translation); 38110801Srene.dejong@arm.com translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 38211180Ssascha.bischoff@ARM.com} 38311180Ssascha.bischoff@ARM.com 38410801Srene.dejong@arm.comFault 38510801Srene.dejong@arm.comTLB::finalizePhysical(const RequestPtr &req, 38610801Srene.dejong@arm.com ThreadContext *tc, Mode mode) const 38710801Srene.dejong@arm.com{ 38810801Srene.dejong@arm.com return NoFault; 38910801Srene.dejong@arm.com} 39010801Srene.dejong@arm.com 39110801Srene.dejong@arm.com 39210801Srene.dejong@arm.comRiscvISA::PTE & 39310801Srene.dejong@arm.comTLB::index(bool advance) 39410801Srene.dejong@arm.com{ 39510801Srene.dejong@arm.com PTE *pte = &table[nlu]; 39610801Srene.dejong@arm.com 39710801Srene.dejong@arm.com if (advance) 39810801Srene.dejong@arm.com nextnlu(); 39910801Srene.dejong@arm.com 40010801Srene.dejong@arm.com return *pte; 40110801Srene.dejong@arm.com} 40210801Srene.dejong@arm.com 40310801Srene.dejong@arm.comRiscvISA::TLB * 40410801Srene.dejong@arm.comRiscvTLBParams::create() 40510801Srene.dejong@arm.com{ 40610801Srene.dejong@arm.com return new TLB(this); 40710801Srene.dejong@arm.com} 40810801Srene.dejong@arm.com