registers.hh revision 13622:ba31c2a23eca 
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2016 RISC-V Foundation
16 * Copyright (c) 2016 The University of Virginia
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Andreas Hansson
43 *          Sven Karlsson
44 *          Alec Roelke
45 */
46
47#ifndef __ARCH_RISCV_REGISTERS_HH__
48#define __ARCH_RISCV_REGISTERS_HH__
49
50#include <map>
51#include <string>
52#include <vector>
53
54#include "arch/generic/types.hh"
55#include "arch/generic/vec_pred_reg.hh"
56#include "arch/generic/vec_reg.hh"
57#include "arch/isa_traits.hh"
58#include "arch/riscv/generated/max_inst_regs.hh"
59#include "base/types.hh"
60
61namespace RiscvISA {
62
63using RiscvISAInst::MaxInstSrcRegs;
64using RiscvISAInst::MaxInstDestRegs;
65const int MaxMiscDestRegs = 1;
66
67// Not applicable to RISC-V
68using VecElem = ::DummyVecElem;
69using VecReg = ::DummyVecReg;
70using ConstVecReg = ::DummyConstVecReg;
71using VecRegContainer = ::DummyVecRegContainer;
72constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
73constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
74
75// Not applicable to RISC-V
76using VecPredReg = ::DummyVecPredReg;
77using ConstVecPredReg = ::DummyConstVecPredReg;
78using VecPredRegContainer = ::DummyVecPredRegContainer;
79constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
80constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
81
82const int NumIntArchRegs = 32;
83const int NumMicroIntRegs = 1;
84const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
85const int NumFloatRegs = 32;
86
87const unsigned NumVecRegs = 1;  // Not applicable to RISC-V
88                                // (1 to prevent warnings)
89const int NumVecPredRegs = 1;  // Not applicable to RISC-V
90                               // (1 to prevent warnings)
91
92const int NumCCRegs = 0;
93
94// Semantically meaningful register indices
95const int ZeroReg = 0;
96const int ReturnAddrReg = 1;
97const int StackPointerReg = 2;
98const int GlobalPointerReg = 3;
99const int ThreadPointerReg = 4;
100const int FramePointerReg = 8;
101const int ReturnValueReg = 10;
102const std::vector<int> ReturnValueRegs = {10, 11};
103const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
104const int AMOTempReg = 32;
105
106const int SyscallPseudoReturnReg = 10;
107const std::vector<int> SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
108const int SyscallNumReg = 17;
109
110const std::vector<std::string> IntRegNames = {
111    "zero", "ra", "sp", "gp",
112    "tp", "t0", "t1", "t2",
113    "s0", "s1", "a0", "a1",
114    "a2", "a3", "a4", "a5",
115    "a6", "a7", "s2", "s3",
116    "s4", "s5", "s6", "s7",
117    "s8", "s9", "s10", "s11",
118    "t3", "t4", "t5", "t6"
119};
120const std::vector<std::string> FloatRegNames = {
121    "ft0", "ft1", "ft2", "ft3",
122    "ft4", "ft5", "ft6", "ft7",
123    "fs0", "fs1", "fa0", "fa1",
124    "fa2", "fa3", "fa4", "fa5",
125    "fa6", "fa7", "fs2", "fs3",
126    "fs4", "fs5", "fs6", "fs7",
127    "fs8", "fs9", "fs10", "fs11",
128    "ft8", "ft9", "ft10", "ft11"
129};
130
131enum MiscRegIndex {
132    MISCREG_PRV = 0,
133    MISCREG_ISA,
134    MISCREG_VENDORID,
135    MISCREG_ARCHID,
136    MISCREG_IMPID,
137    MISCREG_HARTID,
138    MISCREG_STATUS,
139    MISCREG_IP,
140    MISCREG_IE,
141    MISCREG_CYCLE,
142    MISCREG_TIME,
143    MISCREG_INSTRET,
144    MISCREG_HPMCOUNTER03,
145    MISCREG_HPMCOUNTER04,
146    MISCREG_HPMCOUNTER05,
147    MISCREG_HPMCOUNTER06,
148    MISCREG_HPMCOUNTER07,
149    MISCREG_HPMCOUNTER08,
150    MISCREG_HPMCOUNTER09,
151    MISCREG_HPMCOUNTER10,
152    MISCREG_HPMCOUNTER11,
153    MISCREG_HPMCOUNTER12,
154    MISCREG_HPMCOUNTER13,
155    MISCREG_HPMCOUNTER14,
156    MISCREG_HPMCOUNTER15,
157    MISCREG_HPMCOUNTER16,
158    MISCREG_HPMCOUNTER17,
159    MISCREG_HPMCOUNTER18,
160    MISCREG_HPMCOUNTER19,
161    MISCREG_HPMCOUNTER20,
162    MISCREG_HPMCOUNTER21,
163    MISCREG_HPMCOUNTER22,
164    MISCREG_HPMCOUNTER23,
165    MISCREG_HPMCOUNTER24,
166    MISCREG_HPMCOUNTER25,
167    MISCREG_HPMCOUNTER26,
168    MISCREG_HPMCOUNTER27,
169    MISCREG_HPMCOUNTER28,
170    MISCREG_HPMCOUNTER29,
171    MISCREG_HPMCOUNTER30,
172    MISCREG_HPMCOUNTER31,
173    MISCREG_HPMEVENT03,
174    MISCREG_HPMEVENT04,
175    MISCREG_HPMEVENT05,
176    MISCREG_HPMEVENT06,
177    MISCREG_HPMEVENT07,
178    MISCREG_HPMEVENT08,
179    MISCREG_HPMEVENT09,
180    MISCREG_HPMEVENT10,
181    MISCREG_HPMEVENT11,
182    MISCREG_HPMEVENT12,
183    MISCREG_HPMEVENT13,
184    MISCREG_HPMEVENT14,
185    MISCREG_HPMEVENT15,
186    MISCREG_HPMEVENT16,
187    MISCREG_HPMEVENT17,
188    MISCREG_HPMEVENT18,
189    MISCREG_HPMEVENT19,
190    MISCREG_HPMEVENT20,
191    MISCREG_HPMEVENT21,
192    MISCREG_HPMEVENT22,
193    MISCREG_HPMEVENT23,
194    MISCREG_HPMEVENT24,
195    MISCREG_HPMEVENT25,
196    MISCREG_HPMEVENT26,
197    MISCREG_HPMEVENT27,
198    MISCREG_HPMEVENT28,
199    MISCREG_HPMEVENT29,
200    MISCREG_HPMEVENT30,
201    MISCREG_HPMEVENT31,
202    MISCREG_TSELECT,
203    MISCREG_TDATA1,
204    MISCREG_TDATA2,
205    MISCREG_TDATA3,
206    MISCREG_DCSR,
207    MISCREG_DPC,
208    MISCREG_DSCRATCH,
209
210    MISCREG_MEDELEG,
211    MISCREG_MIDELEG,
212    MISCREG_MTVEC,
213    MISCREG_MCOUNTEREN,
214    MISCREG_MSCRATCH,
215    MISCREG_MEPC,
216    MISCREG_MCAUSE,
217    MISCREG_MTVAL,
218    MISCREG_PMPCFG0,
219    // pmpcfg1 rv32 only
220    MISCREG_PMPCFG2,
221    // pmpcfg3 rv32 only
222    MISCREG_PMPADDR00,
223    MISCREG_PMPADDR01,
224    MISCREG_PMPADDR02,
225    MISCREG_PMPADDR03,
226    MISCREG_PMPADDR04,
227    MISCREG_PMPADDR05,
228    MISCREG_PMPADDR06,
229    MISCREG_PMPADDR07,
230    MISCREG_PMPADDR08,
231    MISCREG_PMPADDR09,
232    MISCREG_PMPADDR10,
233    MISCREG_PMPADDR11,
234    MISCREG_PMPADDR12,
235    MISCREG_PMPADDR13,
236    MISCREG_PMPADDR14,
237    MISCREG_PMPADDR15,
238
239    MISCREG_SEDELEG,
240    MISCREG_SIDELEG,
241    MISCREG_STVEC,
242    MISCREG_SCOUNTEREN,
243    MISCREG_SSCRATCH,
244    MISCREG_SEPC,
245    MISCREG_SCAUSE,
246    MISCREG_STVAL,
247    MISCREG_SATP,
248
249    MISCREG_UTVEC,
250    MISCREG_USCRATCH,
251    MISCREG_UEPC,
252    MISCREG_UCAUSE,
253    MISCREG_UTVAL,
254    MISCREG_FFLAGS,
255    MISCREG_FRM,
256
257    NUM_MISCREGS
258};
259const int NumMiscRegs = NUM_MISCREGS;
260
261enum CSRIndex {
262    CSR_USTATUS = 0x000,
263    CSR_UIE = 0x004,
264    CSR_UTVEC = 0x005,
265    CSR_USCRATCH = 0x040,
266    CSR_UEPC = 0x041,
267    CSR_UCAUSE = 0x042,
268    CSR_UTVAL = 0x043,
269    CSR_UIP = 0x044,
270    CSR_FFLAGS = 0x001,
271    CSR_FRM = 0x002,
272    CSR_FCSR = 0x003,
273    CSR_CYCLE = 0xC00,
274    CSR_TIME = 0xC01,
275    CSR_INSTRET = 0xC02,
276    CSR_HPMCOUNTER03 = 0xC03,
277    CSR_HPMCOUNTER04 = 0xC04,
278    CSR_HPMCOUNTER05 = 0xC05,
279    CSR_HPMCOUNTER06 = 0xC06,
280    CSR_HPMCOUNTER07 = 0xC07,
281    CSR_HPMCOUNTER08 = 0xC08,
282    CSR_HPMCOUNTER09 = 0xC09,
283    CSR_HPMCOUNTER10 = 0xC0A,
284    CSR_HPMCOUNTER11 = 0xC0B,
285    CSR_HPMCOUNTER12 = 0xC0C,
286    CSR_HPMCOUNTER13 = 0xC0D,
287    CSR_HPMCOUNTER14 = 0xC0E,
288    CSR_HPMCOUNTER15 = 0xC0F,
289    CSR_HPMCOUNTER16 = 0xC10,
290    CSR_HPMCOUNTER17 = 0xC11,
291    CSR_HPMCOUNTER18 = 0xC12,
292    CSR_HPMCOUNTER19 = 0xC13,
293    CSR_HPMCOUNTER20 = 0xC14,
294    CSR_HPMCOUNTER21 = 0xC15,
295    CSR_HPMCOUNTER22 = 0xC16,
296    CSR_HPMCOUNTER23 = 0xC17,
297    CSR_HPMCOUNTER24 = 0xC18,
298    CSR_HPMCOUNTER25 = 0xC19,
299    CSR_HPMCOUNTER26 = 0xC1A,
300    CSR_HPMCOUNTER27 = 0xC1B,
301    CSR_HPMCOUNTER28 = 0xC1C,
302    CSR_HPMCOUNTER29 = 0xC1D,
303    CSR_HPMCOUNTER30 = 0xC1E,
304    CSR_HPMCOUNTER31 = 0xC1F,
305    // HPMCOUNTERH rv32 only
306
307    CSR_SSTATUS = 0x100,
308    CSR_SEDELEG = 0x102,
309    CSR_SIDELEG = 0x103,
310    CSR_SIE = 0x104,
311    CSR_STVEC = 0x105,
312    CSR_SSCRATCH = 0x140,
313    CSR_SEPC = 0x141,
314    CSR_SCAUSE = 0x142,
315    CSR_STVAL = 0x143,
316    CSR_SIP = 0x144,
317    CSR_SATP = 0x180,
318
319    CSR_MVENDORID = 0xF11,
320    CSR_MARCHID = 0xF12,
321    CSR_MIMPID = 0xF13,
322    CSR_MHARTID = 0xF14,
323    CSR_MSTATUS = 0x300,
324    CSR_MISA = 0x301,
325    CSR_MEDELEG = 0x302,
326    CSR_MIDELEG = 0x303,
327    CSR_MIE = 0x304,
328    CSR_MTVEC = 0x305,
329    CSR_MSCRATCH = 0x340,
330    CSR_MEPC = 0x341,
331    CSR_MCAUSE = 0x342,
332    CSR_MTVAL = 0x343,
333    CSR_MIP = 0x344,
334    CSR_PMPCFG0 = 0x3A0,
335    // pmpcfg1 rv32 only
336    CSR_PMPCFG2 = 0x3A2,
337    // pmpcfg3 rv32 only
338    CSR_PMPADDR00 = 0x3B0,
339    CSR_PMPADDR01 = 0x3B1,
340    CSR_PMPADDR02 = 0x3B2,
341    CSR_PMPADDR03 = 0x3B3,
342    CSR_PMPADDR04 = 0x3B4,
343    CSR_PMPADDR05 = 0x3B5,
344    CSR_PMPADDR06 = 0x3B6,
345    CSR_PMPADDR07 = 0x3B7,
346    CSR_PMPADDR08 = 0x3B8,
347    CSR_PMPADDR09 = 0x3B9,
348    CSR_PMPADDR10 = 0x3BA,
349    CSR_PMPADDR11 = 0x3BB,
350    CSR_PMPADDR12 = 0x3BC,
351    CSR_PMPADDR13 = 0x3BD,
352    CSR_PMPADDR14 = 0x3BE,
353    CSR_PMPADDR15 = 0x3BF,
354    CSR_MCYCLE = 0xB00,
355    CSR_MINSTRET = 0xB02,
356    CSR_MHPMCOUNTER03 = 0xC03,
357    CSR_MHPMCOUNTER04 = 0xC04,
358    CSR_MHPMCOUNTER05 = 0xC05,
359    CSR_MHPMCOUNTER06 = 0xC06,
360    CSR_MHPMCOUNTER07 = 0xC07,
361    CSR_MHPMCOUNTER08 = 0xC08,
362    CSR_MHPMCOUNTER09 = 0xC09,
363    CSR_MHPMCOUNTER10 = 0xC0A,
364    CSR_MHPMCOUNTER11 = 0xC0B,
365    CSR_MHPMCOUNTER12 = 0xC0C,
366    CSR_MHPMCOUNTER13 = 0xC0D,
367    CSR_MHPMCOUNTER14 = 0xC0E,
368    CSR_MHPMCOUNTER15 = 0xC0F,
369    CSR_MHPMCOUNTER16 = 0xC10,
370    CSR_MHPMCOUNTER17 = 0xC11,
371    CSR_MHPMCOUNTER18 = 0xC12,
372    CSR_MHPMCOUNTER19 = 0xC13,
373    CSR_MHPMCOUNTER20 = 0xC14,
374    CSR_MHPMCOUNTER21 = 0xC15,
375    CSR_MHPMCOUNTER22 = 0xC16,
376    CSR_MHPMCOUNTER23 = 0xC17,
377    CSR_MHPMCOUNTER24 = 0xC18,
378    CSR_MHPMCOUNTER25 = 0xC19,
379    CSR_MHPMCOUNTER26 = 0xC1A,
380    CSR_MHPMCOUNTER27 = 0xC1B,
381    CSR_MHPMCOUNTER28 = 0xC1C,
382    CSR_MHPMCOUNTER29 = 0xC1D,
383    CSR_MHPMCOUNTER30 = 0xC1E,
384    CSR_MHPMCOUNTER31 = 0xC1F,
385    // MHPMCOUNTERH rv32 only
386    CSR_MHPMEVENT03 = 0x323,
387    CSR_MHPMEVENT04 = 0x324,
388    CSR_MHPMEVENT05 = 0x325,
389    CSR_MHPMEVENT06 = 0x326,
390    CSR_MHPMEVENT07 = 0x327,
391    CSR_MHPMEVENT08 = 0x328,
392    CSR_MHPMEVENT09 = 0x329,
393    CSR_MHPMEVENT10 = 0x32A,
394    CSR_MHPMEVENT11 = 0x32B,
395    CSR_MHPMEVENT12 = 0x32C,
396    CSR_MHPMEVENT13 = 0x32D,
397    CSR_MHPMEVENT14 = 0x32E,
398    CSR_MHPMEVENT15 = 0x32F,
399    CSR_MHPMEVENT16 = 0x330,
400    CSR_MHPMEVENT17 = 0x331,
401    CSR_MHPMEVENT18 = 0x332,
402    CSR_MHPMEVENT19 = 0x333,
403    CSR_MHPMEVENT20 = 0x334,
404    CSR_MHPMEVENT21 = 0x335,
405    CSR_MHPMEVENT22 = 0x336,
406    CSR_MHPMEVENT23 = 0x337,
407    CSR_MHPMEVENT24 = 0x338,
408    CSR_MHPMEVENT25 = 0x339,
409    CSR_MHPMEVENT26 = 0x33A,
410    CSR_MHPMEVENT27 = 0x33B,
411    CSR_MHPMEVENT28 = 0x33C,
412    CSR_MHPMEVENT29 = 0x33D,
413    CSR_MHPMEVENT30 = 0x33E,
414    CSR_MHPMEVENT31 = 0x33F,
415
416    CSR_TSELECT = 0x7A0,
417    CSR_TDATA1 = 0x7A1,
418    CSR_TDATA2 = 0x7A2,
419    CSR_TDATA3 = 0x7A3,
420    CSR_DCSR = 0x7B0,
421    CSR_DPC = 0x7B1,
422    CSR_DSCRATCH = 0x7B2
423};
424
425struct CSRMetadata
426{
427    const std::string name;
428    const int physIndex;
429};
430
431const std::map<int, CSRMetadata> CSRData = {
432    {CSR_USTATUS, {"ustatus", MISCREG_STATUS}},
433    {CSR_UIE, {"uie", MISCREG_IE}},
434    {CSR_UTVEC, {"utvec", MISCREG_UTVEC}},
435    {CSR_USCRATCH, {"uscratch", MISCREG_USCRATCH}},
436    {CSR_UEPC, {"uepc", MISCREG_UEPC}},
437    {CSR_UCAUSE, {"ucause", MISCREG_UCAUSE}},
438    {CSR_UTVAL, {"utval", MISCREG_UTVAL}},
439    {CSR_UIP, {"uip", MISCREG_IP}},
440    {CSR_FFLAGS, {"fflags", MISCREG_FFLAGS}},
441    {CSR_FRM, {"frm", MISCREG_FRM}},
442    {CSR_FCSR, {"fcsr", MISCREG_FFLAGS}}, // Actually FRM << 5 | FFLAGS
443    {CSR_CYCLE, {"cycle", MISCREG_CYCLE}},
444    {CSR_TIME, {"time", MISCREG_TIME}},
445    {CSR_INSTRET, {"instret", MISCREG_INSTRET}},
446    {CSR_HPMCOUNTER03, {"hpmcounter03", MISCREG_HPMCOUNTER03}},
447    {CSR_HPMCOUNTER04, {"hpmcounter04", MISCREG_HPMCOUNTER04}},
448    {CSR_HPMCOUNTER05, {"hpmcounter05", MISCREG_HPMCOUNTER05}},
449    {CSR_HPMCOUNTER06, {"hpmcounter06", MISCREG_HPMCOUNTER06}},
450    {CSR_HPMCOUNTER07, {"hpmcounter07", MISCREG_HPMCOUNTER07}},
451    {CSR_HPMCOUNTER08, {"hpmcounter08", MISCREG_HPMCOUNTER08}},
452    {CSR_HPMCOUNTER09, {"hpmcounter09", MISCREG_HPMCOUNTER09}},
453    {CSR_HPMCOUNTER10, {"hpmcounter10", MISCREG_HPMCOUNTER10}},
454    {CSR_HPMCOUNTER11, {"hpmcounter11", MISCREG_HPMCOUNTER11}},
455    {CSR_HPMCOUNTER12, {"hpmcounter12", MISCREG_HPMCOUNTER12}},
456    {CSR_HPMCOUNTER13, {"hpmcounter13", MISCREG_HPMCOUNTER13}},
457    {CSR_HPMCOUNTER14, {"hpmcounter14", MISCREG_HPMCOUNTER14}},
458    {CSR_HPMCOUNTER15, {"hpmcounter15", MISCREG_HPMCOUNTER15}},
459    {CSR_HPMCOUNTER16, {"hpmcounter16", MISCREG_HPMCOUNTER16}},
460    {CSR_HPMCOUNTER17, {"hpmcounter17", MISCREG_HPMCOUNTER17}},
461    {CSR_HPMCOUNTER18, {"hpmcounter18", MISCREG_HPMCOUNTER18}},
462    {CSR_HPMCOUNTER19, {"hpmcounter19", MISCREG_HPMCOUNTER19}},
463    {CSR_HPMCOUNTER20, {"hpmcounter20", MISCREG_HPMCOUNTER20}},
464    {CSR_HPMCOUNTER21, {"hpmcounter21", MISCREG_HPMCOUNTER21}},
465    {CSR_HPMCOUNTER22, {"hpmcounter22", MISCREG_HPMCOUNTER22}},
466    {CSR_HPMCOUNTER23, {"hpmcounter23", MISCREG_HPMCOUNTER23}},
467    {CSR_HPMCOUNTER24, {"hpmcounter24", MISCREG_HPMCOUNTER24}},
468    {CSR_HPMCOUNTER25, {"hpmcounter25", MISCREG_HPMCOUNTER25}},
469    {CSR_HPMCOUNTER26, {"hpmcounter26", MISCREG_HPMCOUNTER26}},
470    {CSR_HPMCOUNTER27, {"hpmcounter27", MISCREG_HPMCOUNTER27}},
471    {CSR_HPMCOUNTER28, {"hpmcounter28", MISCREG_HPMCOUNTER28}},
472    {CSR_HPMCOUNTER29, {"hpmcounter29", MISCREG_HPMCOUNTER29}},
473    {CSR_HPMCOUNTER30, {"hpmcounter30", MISCREG_HPMCOUNTER30}},
474    {CSR_HPMCOUNTER31, {"hpmcounter31", MISCREG_HPMCOUNTER31}},
475
476    {CSR_SSTATUS, {"sstatus", MISCREG_STATUS}},
477    {CSR_SEDELEG, {"sedeleg", MISCREG_SEDELEG}},
478    {CSR_SIDELEG, {"sideleg", MISCREG_SIDELEG}},
479    {CSR_SIE, {"sie", MISCREG_IE}},
480    {CSR_STVEC, {"stvec", MISCREG_STVEC}},
481    {CSR_SSCRATCH, {"sscratch", MISCREG_SSCRATCH}},
482    {CSR_SEPC, {"sepc", MISCREG_SEPC}},
483    {CSR_SCAUSE, {"scause", MISCREG_SCAUSE}},
484    {CSR_STVAL, {"stval", MISCREG_STVAL}},
485    {CSR_SIP, {"sip", MISCREG_IP}},
486    {CSR_SATP, {"satp", MISCREG_SATP}},
487
488    {CSR_MVENDORID, {"mvendorid", MISCREG_VENDORID}},
489    {CSR_MARCHID, {"marchid", MISCREG_ARCHID}},
490    {CSR_MIMPID, {"mimpid", MISCREG_IMPID}},
491    {CSR_MHARTID, {"mhartid", MISCREG_HARTID}},
492    {CSR_MSTATUS, {"mstatus", MISCREG_STATUS}},
493    {CSR_MISA, {"misa", MISCREG_ISA}},
494    {CSR_MEDELEG, {"medeleg", MISCREG_MEDELEG}},
495    {CSR_MIDELEG, {"mideleg", MISCREG_MIDELEG}},
496    {CSR_MIE, {"mie", MISCREG_IE}},
497    {CSR_MTVEC, {"mtvec", MISCREG_MTVEC}},
498    {CSR_MSCRATCH, {"mscratch", MISCREG_MSCRATCH}},
499    {CSR_MEPC, {"mepc", MISCREG_MEPC}},
500    {CSR_MCAUSE, {"mcause", MISCREG_MCAUSE}},
501    {CSR_MTVAL, {"mtval", MISCREG_MTVAL}},
502    {CSR_MIP, {"mip", MISCREG_IP}},
503    {CSR_PMPCFG0, {"pmpcfg0", MISCREG_PMPCFG0}},
504    // pmpcfg1 rv32 only
505    {CSR_PMPCFG2, {"pmpcfg2", MISCREG_PMPCFG2}},
506    // pmpcfg3 rv32 only
507    {CSR_PMPADDR00, {"pmpaddr0", MISCREG_PMPADDR00}},
508    {CSR_PMPADDR01, {"pmpaddr1", MISCREG_PMPADDR01}},
509    {CSR_PMPADDR02, {"pmpaddr2", MISCREG_PMPADDR02}},
510    {CSR_PMPADDR03, {"pmpaddr3", MISCREG_PMPADDR03}},
511    {CSR_PMPADDR04, {"pmpaddr4", MISCREG_PMPADDR04}},
512    {CSR_PMPADDR05, {"pmpaddr5", MISCREG_PMPADDR05}},
513    {CSR_PMPADDR06, {"pmpaddr6", MISCREG_PMPADDR06}},
514    {CSR_PMPADDR07, {"pmpaddr7", MISCREG_PMPADDR07}},
515    {CSR_PMPADDR08, {"pmpaddr8", MISCREG_PMPADDR08}},
516    {CSR_PMPADDR09, {"pmpaddr9", MISCREG_PMPADDR09}},
517    {CSR_PMPADDR10, {"pmpaddr10", MISCREG_PMPADDR10}},
518    {CSR_PMPADDR11, {"pmpaddr11", MISCREG_PMPADDR11}},
519    {CSR_PMPADDR12, {"pmpaddr12", MISCREG_PMPADDR12}},
520    {CSR_PMPADDR13, {"pmpaddr13", MISCREG_PMPADDR13}},
521    {CSR_PMPADDR14, {"pmpaddr14", MISCREG_PMPADDR14}},
522    {CSR_PMPADDR15, {"pmpaddr15", MISCREG_PMPADDR15}},
523    {CSR_MCYCLE, {"mcycle", MISCREG_CYCLE}},
524    {CSR_MINSTRET, {"minstret", MISCREG_INSTRET}},
525    {CSR_MHPMCOUNTER03, {"mhpmcounter03", MISCREG_HPMCOUNTER03}},
526    {CSR_MHPMCOUNTER04, {"mhpmcounter04", MISCREG_HPMCOUNTER04}},
527    {CSR_MHPMCOUNTER05, {"mhpmcounter05", MISCREG_HPMCOUNTER05}},
528    {CSR_MHPMCOUNTER06, {"mhpmcounter06", MISCREG_HPMCOUNTER06}},
529    {CSR_MHPMCOUNTER07, {"mhpmcounter07", MISCREG_HPMCOUNTER07}},
530    {CSR_MHPMCOUNTER08, {"mhpmcounter08", MISCREG_HPMCOUNTER08}},
531    {CSR_MHPMCOUNTER09, {"mhpmcounter09", MISCREG_HPMCOUNTER09}},
532    {CSR_MHPMCOUNTER10, {"mhpmcounter10", MISCREG_HPMCOUNTER10}},
533    {CSR_MHPMCOUNTER11, {"mhpmcounter11", MISCREG_HPMCOUNTER11}},
534    {CSR_MHPMCOUNTER12, {"mhpmcounter12", MISCREG_HPMCOUNTER12}},
535    {CSR_MHPMCOUNTER13, {"mhpmcounter13", MISCREG_HPMCOUNTER13}},
536    {CSR_MHPMCOUNTER14, {"mhpmcounter14", MISCREG_HPMCOUNTER14}},
537    {CSR_MHPMCOUNTER15, {"mhpmcounter15", MISCREG_HPMCOUNTER15}},
538    {CSR_MHPMCOUNTER16, {"mhpmcounter16", MISCREG_HPMCOUNTER16}},
539    {CSR_MHPMCOUNTER17, {"mhpmcounter17", MISCREG_HPMCOUNTER17}},
540    {CSR_MHPMCOUNTER18, {"mhpmcounter18", MISCREG_HPMCOUNTER18}},
541    {CSR_MHPMCOUNTER19, {"mhpmcounter19", MISCREG_HPMCOUNTER19}},
542    {CSR_MHPMCOUNTER20, {"mhpmcounter20", MISCREG_HPMCOUNTER20}},
543    {CSR_MHPMCOUNTER21, {"mhpmcounter21", MISCREG_HPMCOUNTER21}},
544    {CSR_MHPMCOUNTER22, {"mhpmcounter22", MISCREG_HPMCOUNTER22}},
545    {CSR_MHPMCOUNTER23, {"mhpmcounter23", MISCREG_HPMCOUNTER23}},
546    {CSR_MHPMCOUNTER24, {"mhpmcounter24", MISCREG_HPMCOUNTER24}},
547    {CSR_MHPMCOUNTER25, {"mhpmcounter25", MISCREG_HPMCOUNTER25}},
548    {CSR_MHPMCOUNTER26, {"mhpmcounter26", MISCREG_HPMCOUNTER26}},
549    {CSR_MHPMCOUNTER27, {"mhpmcounter27", MISCREG_HPMCOUNTER27}},
550    {CSR_MHPMCOUNTER28, {"mhpmcounter28", MISCREG_HPMCOUNTER28}},
551    {CSR_MHPMCOUNTER29, {"mhpmcounter29", MISCREG_HPMCOUNTER29}},
552    {CSR_MHPMCOUNTER30, {"mhpmcounter30", MISCREG_HPMCOUNTER30}},
553    {CSR_MHPMCOUNTER31, {"mhpmcounter31", MISCREG_HPMCOUNTER31}},
554    {CSR_MHPMEVENT03, {"mhpmevent03", MISCREG_HPMEVENT03}},
555    {CSR_MHPMEVENT04, {"mhpmevent04", MISCREG_HPMEVENT04}},
556    {CSR_MHPMEVENT05, {"mhpmevent05", MISCREG_HPMEVENT05}},
557    {CSR_MHPMEVENT06, {"mhpmevent06", MISCREG_HPMEVENT06}},
558    {CSR_MHPMEVENT07, {"mhpmevent07", MISCREG_HPMEVENT07}},
559    {CSR_MHPMEVENT08, {"mhpmevent08", MISCREG_HPMEVENT08}},
560    {CSR_MHPMEVENT09, {"mhpmevent09", MISCREG_HPMEVENT09}},
561    {CSR_MHPMEVENT10, {"mhpmevent10", MISCREG_HPMEVENT10}},
562    {CSR_MHPMEVENT11, {"mhpmevent11", MISCREG_HPMEVENT11}},
563    {CSR_MHPMEVENT12, {"mhpmevent12", MISCREG_HPMEVENT12}},
564    {CSR_MHPMEVENT13, {"mhpmevent13", MISCREG_HPMEVENT13}},
565    {CSR_MHPMEVENT14, {"mhpmevent14", MISCREG_HPMEVENT14}},
566    {CSR_MHPMEVENT15, {"mhpmevent15", MISCREG_HPMEVENT15}},
567    {CSR_MHPMEVENT16, {"mhpmevent16", MISCREG_HPMEVENT16}},
568    {CSR_MHPMEVENT17, {"mhpmevent17", MISCREG_HPMEVENT17}},
569    {CSR_MHPMEVENT18, {"mhpmevent18", MISCREG_HPMEVENT18}},
570    {CSR_MHPMEVENT19, {"mhpmevent19", MISCREG_HPMEVENT19}},
571    {CSR_MHPMEVENT20, {"mhpmevent20", MISCREG_HPMEVENT20}},
572    {CSR_MHPMEVENT21, {"mhpmevent21", MISCREG_HPMEVENT21}},
573    {CSR_MHPMEVENT22, {"mhpmevent22", MISCREG_HPMEVENT22}},
574    {CSR_MHPMEVENT23, {"mhpmevent23", MISCREG_HPMEVENT23}},
575    {CSR_MHPMEVENT24, {"mhpmevent24", MISCREG_HPMEVENT24}},
576    {CSR_MHPMEVENT25, {"mhpmevent25", MISCREG_HPMEVENT25}},
577    {CSR_MHPMEVENT26, {"mhpmevent26", MISCREG_HPMEVENT26}},
578    {CSR_MHPMEVENT27, {"mhpmevent27", MISCREG_HPMEVENT27}},
579    {CSR_MHPMEVENT28, {"mhpmevent28", MISCREG_HPMEVENT28}},
580    {CSR_MHPMEVENT29, {"mhpmevent29", MISCREG_HPMEVENT29}},
581    {CSR_MHPMEVENT30, {"mhpmevent30", MISCREG_HPMEVENT30}},
582    {CSR_MHPMEVENT31, {"mhpmevent31", MISCREG_HPMEVENT31}},
583
584    {CSR_TSELECT, {"tselect", MISCREG_TSELECT}},
585    {CSR_TDATA1, {"tdata1", MISCREG_TDATA1}},
586    {CSR_TDATA2, {"tdata2", MISCREG_TDATA2}},
587    {CSR_TDATA3, {"tdata3", MISCREG_TDATA3}},
588    {CSR_DCSR, {"dcsr", MISCREG_DCSR}},
589    {CSR_DPC, {"dpc", MISCREG_DPC}},
590    {CSR_DSCRATCH, {"dscratch", MISCREG_DSCRATCH}}
591};
592
593/**
594 * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
595 * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that
596 * uses these fields is the MSTATUS register, which is shadowed by two others
597 * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see
598 * the fields for higher privileges.
599 */
600BitUnion64(STATUS)
601    Bitfield<63> sd;
602    Bitfield<35, 34> sxl;
603    Bitfield<33, 32> uxl;
604    Bitfield<22> tsr;
605    Bitfield<21> tw;
606    Bitfield<20> tvm;
607    Bitfield<19> mxr;
608    Bitfield<18> sum;
609    Bitfield<17> mprv;
610    Bitfield<16, 15> xs;
611    Bitfield<14, 13> fs;
612    Bitfield<12, 11> mpp;
613    Bitfield<8> spp;
614    Bitfield<7> mpie;
615    Bitfield<5> spie;
616    Bitfield<4> upie;
617    Bitfield<3> mie;
618    Bitfield<1> sie;
619    Bitfield<0> uie;
620EndBitUnion(STATUS)
621
622/**
623 * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
624 * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP
625 * and MIE registers have the same fields, so accesses to either should use
626 * this bit union.
627 */
628BitUnion64(INTERRUPT)
629    Bitfield<11> mei;
630    Bitfield<9> sei;
631    Bitfield<8> uei;
632    Bitfield<7> mti;
633    Bitfield<5> sti;
634    Bitfield<4> uti;
635    Bitfield<3> msi;
636    Bitfield<1> ssi;
637    Bitfield<0> usi;
638EndBitUnion(INTERRUPT)
639
640const off_t MXL_OFFSET = (sizeof(uint64_t) * 8 - 2);
641const off_t SXL_OFFSET = 34;
642const off_t UXL_OFFSET = 32;
643const off_t FS_OFFSET = 13;
644const off_t FRM_OFFSET = 5;
645
646const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET;
647const RegVal ISA_EXT_MASK = mask(26);
648const RegVal MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;
649
650const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1);
651const RegVal STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
652const RegVal STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
653const RegVal STATUS_TSR_MASK = 1ULL << 22;
654const RegVal STATUS_TW_MASK = 1ULL << 21;
655const RegVal STATUS_TVM_MASK = 1ULL << 20;
656const RegVal STATUS_MXR_MASK = 1ULL << 19;
657const RegVal STATUS_SUM_MASK = 1ULL << 18;
658const RegVal STATUS_MPRV_MASK = 1ULL << 17;
659const RegVal STATUS_XS_MASK = 3ULL << 15;
660const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET;
661const RegVal STATUS_MPP_MASK = 3ULL << 11;
662const RegVal STATUS_SPP_MASK = 1ULL << 8;
663const RegVal STATUS_MPIE_MASK = 1ULL << 7;
664const RegVal STATUS_SPIE_MASK = 1ULL << 5;
665const RegVal STATUS_UPIE_MASK = 1ULL << 4;
666const RegVal STATUS_MIE_MASK = 1ULL << 3;
667const RegVal STATUS_SIE_MASK = 1ULL << 1;
668const RegVal STATUS_UIE_MASK = 1ULL << 0;
669const RegVal MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK |
670                            STATUS_UXL_MASK | STATUS_TSR_MASK |
671                            STATUS_TW_MASK | STATUS_TVM_MASK |
672                            STATUS_MXR_MASK | STATUS_SUM_MASK |
673                            STATUS_MPRV_MASK | STATUS_XS_MASK |
674                            STATUS_FS_MASK | STATUS_MPP_MASK |
675                            STATUS_SPP_MASK | STATUS_MPIE_MASK |
676                            STATUS_SPIE_MASK | STATUS_UPIE_MASK |
677                            STATUS_MIE_MASK | STATUS_SIE_MASK |
678                            STATUS_UIE_MASK;
679const RegVal SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
680                            STATUS_MXR_MASK | STATUS_SUM_MASK |
681                            STATUS_XS_MASK | STATUS_FS_MASK |
682                            STATUS_SPP_MASK | STATUS_SPIE_MASK |
683                            STATUS_UPIE_MASK | STATUS_SIE_MASK |
684                            STATUS_UIE_MASK;
685const RegVal USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
686                            STATUS_SUM_MASK | STATUS_XS_MASK |
687                            STATUS_FS_MASK | STATUS_UPIE_MASK |
688                            STATUS_UIE_MASK;
689
690const RegVal MEI_MASK = 1ULL << 11;
691const RegVal SEI_MASK = 1ULL << 9;
692const RegVal UEI_MASK = 1ULL << 8;
693const RegVal MTI_MASK = 1ULL << 7;
694const RegVal STI_MASK = 1ULL << 5;
695const RegVal UTI_MASK = 1ULL << 4;
696const RegVal MSI_MASK = 1ULL << 3;
697const RegVal SSI_MASK = 1ULL << 1;
698const RegVal USI_MASK = 1ULL << 0;
699const RegVal MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK |
700                       MTI_MASK | STI_MASK | UTI_MASK |
701                       MSI_MASK | SSI_MASK | USI_MASK;
702const RegVal SI_MASK = SEI_MASK | UEI_MASK |
703                       STI_MASK | UTI_MASK |
704                       SSI_MASK | USI_MASK;
705const RegVal UI_MASK = UEI_MASK | UTI_MASK | USI_MASK;
706const RegVal FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
707const RegVal FRM_MASK = 0x7;
708
709const std::map<int, RegVal> CSRMasks = {
710    {CSR_USTATUS, USTATUS_MASK},
711    {CSR_UIE, UI_MASK},
712    {CSR_UIP, UI_MASK},
713    {CSR_FFLAGS, FFLAGS_MASK},
714    {CSR_FRM, FRM_MASK},
715    {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
716    {CSR_SSTATUS, SSTATUS_MASK},
717    {CSR_SIE, SI_MASK},
718    {CSR_SIP, SI_MASK},
719    {CSR_MSTATUS, MSTATUS_MASK},
720    {CSR_MISA, MISA_MASK},
721    {CSR_MIE, MI_MASK},
722    {CSR_MIP, MI_MASK}
723};
724
725}
726
727#endif // __ARCH_RISCV_REGISTERS_HH__
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